Synthesis of Mealy FSM with transformation of system of microoperations in excitation functions Текст научной статьи по специальности «Математика»

UDC 519.713:681.326

SYNTHESIS OF MEALY FSM WITH TRANSFORMATION OF SYSTEM OF MICROOPERATIONS IN EXCITATION FUNCTIONS

BARKALOVA., BUKOWIECA.

The method of hardware optimization of Mealy FSM is proposed. Method is based on the representation of the system of excitation functions terms as the pairs 6microinstruction in the initial state, microinstruction in the state of transactionc and unitary encoding of microoperations. An example of application of proposed method is given.

1. Introduction

A control unit of digital system can be implemented as Mealy finite-state-machine (FSM) [ 1]. The programmable logic devices (PLD) such as PLA, PAL, CPLD and FPGA are wide used today to implement the logical circuits of FSM [2, 3]. This basis is characterized by the high cost and one of the most important tasks arousing under the FSM design is minimization of the circuit cost. This task can be solved by applying the methods of structural reduction [4] but it leads to the decreasing of the digital system performance. This article proposes the method of synthesis based on unitary encoding of microoperations, maximal encoding of the sets of microoperations [5] and unstandard representation of the terms of the excitation functions system as pairs 6microinstruction in the initial state, microinstruction in the state of transactionc. Such approach permits to save a high performance of single-level circuit of FSM and to minimize the price of the circuit of excitation functions formation.

2. The main idea of the Method

Let Mealy FSM is set up by the direct structural table (DST) with the columns [1]: am, K(am), as, K(as), Xh, Yh, Fh and h. Here am is an initial state of FSM, am є A where A=|ai,...,aM| is a set of FSM internal states; K(am) is binary code of the state amgA heaving R=]log2M[ bits, the internal variables Tr eT={T1, ...,TR| are used to encode the states amgA; as є A is a state of transaction with code K(as); Xh is an input signal causing a transaction <am,as> that is equal to conjunction of some elements of the set of logic conditions X={x1 ,...,xL|; Yh is an output signal (microinstruction) forming during the transaction <am,as>, Yh c Y where Y={y1,...,yN| is a set ofmicrooperations; Фh is a subset of the excitation functions set Ф = (ф j,..., ф R } that are equal to 1 to switch a FSM memory from K(am) to K(as); h is a number of the table line (h=1,...,H). Each line of DST corresponds to the term

F, = a!;,x„ (h=і......h), a>

where A^ is aconjunction ofinternalvariables corresponding to the initial state ame A from the hth line ofDST. These terms form the disjunctional normal forms of the systems

Y = Y(T,X), (2)

ф = ф(т,х) . (3)

Systems (2)-(3) are implemented by the subcircuit P of the single-level circuit U1 of Mealy FSM (Fig.1).

X-

Y

Fig. 1. Structural diagram of single-level Mealy FSM U1

The memory of FSM is represented by register RG. As a rule this register has informational inputs of the D-type [2].

The single-level circuit has a maximal performance but its disadvantage is a high cost. It is connected with repetition of the functions ф r єФ in the outputs of the different PLD of subcircuit P.

Let initial DST includes Q different microinstructions Yq c Y. Let’s encode each microinstruction Yq c Y by a binary code K(Yq) with R1=] log2Q [ bits. In this article it is proposed to use representation (1) for the terms of system (2) and to represent the terms of the system F as a pairs Eh such as

Eh =<K(Yqm),K(Yq) > (h = 1,...,H). (4)

Here Yqm is a microinstruction forming under the transaction in the initial state ame A, Yq is a microinstruction forming in the state of transaction as є A. It is natural that the microinstructions should be encoded using the different variables. It is possible if FSM circuit includes a special register RY that leads to the Mealy FSM U2 (Fig. 2).

■Y

V

T

Fig. 2. Structural diagram of Mealy FSM U2

Here subcircuit P implements a system (2) and the functions

W = W(T,X) (5)

to identify the microinstruction from hth line of initial DST. The code converter CC forms the functions

Z = z(y,w) (6)

to encode the microinstruction Yqs c Y, register RY keeps a code K(Yqm) represented by the variables Vr є V, |Z|=|V|=R2 < R1.

Subcircuit F forms the excitation functions

® = ®(V,Z). (7)

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A comparison of FSM Ui and U2 shows that delay times for functions yne Y are the same for both FSMs: t(Y)=tp where tP is a delay time of the subcircuit P. The delay

time for functions фr єФ in FSM U1 t(Y)1= tф and

in FSM U2 t(Y)2=tP+tCC+1 ф where too, t ф are a delay time of CC and subcircuit F respectively. If cycle time tD of data-path satisfies to condition

tD > tCC +1® , (8)

then the digital systems with FSMs U1 and U2 have the same performance.

The proposed method is effective if total cost of subcircuits P, CC and F of FSM U2 is less than cost of subcircuit P of FSM U1.

3. Method of design of Mealy FSM U2 and example of its application

The method of Mealy FSM U2 design is proposed in this article, and it is illustrated by the example of design using the direct structural table of Mealy FSM S1 (Table 1).

The proposed method includes the following steps:

1. Formation of the set of microinstructions. It is clear, that microinstruction (MI) Yq c Y should one-to-one determine the state am є A. If MI Yq c Y formed during the transactions in the states am,aje A, then it should correspond to two identical microinstructions Yqm=Yq

Table 1

Direct structural table of Mealy FSM S1

am K(am) as K(as) Xh Yh Фь h

a2 01 x1 y3 D2 1

ai 00 a3 10 ~x1 x3 Y1 y2 D1 2

a4 11 ~x1 ~x3 y3 D1 D2 3

a2 01 a3 10 x2 y2 y4 D1 4

a4 11 ~x2 y3 D1 D2 5

a2 01 x2 y2 y4 D2 6

a3 10 a3 10 ~x2 x3 y1 y2 D1 7

a4 11 ~x2 ~x3 y3 Уз D1 D2 8

a4 11 a1 00 1 - - 9

with different codes K(Yqm) ф K(Yqj). Let A(Yq) is a set of the states such as MI Yq c Y is formed under the transactions in the states ame A(Yq), then mq=|A(Yq)| identical microinstructions Yqm with different codes should correspond to the microinstruction Yq c Y. Therefore, set of microinstructions Y(U2) of Mealy FSM U2 contains the microinstructions Y11,..., Y1m1, ..., Yq1,..., YqmQ and its cardinality number

Qi =£ mq . (9)

q=1

The initial DST contains the microinstructions Y1={y3}, Y2={y1,y2}, Y3={y2,y3}, Y4={y3,y5}, Y5= 0 and Q=5. These microinstructions correspond to the sets A(Y1)={a2,a4}, A(Y2)={a3}, A(Y3)={a2,a3}, A(Y4)={a4} and A(Y5) = {a1}. In this case m1=m3=2 and m2=m4=m5=1. According to (9) Q1=7 and Y(U2)={ Y12, Y14, Y23, Y32, Y33, Y44, Y51}. It is enough

R2=]log2Q1[ bits to encode the microinstructions Yqm c Y(U2) and |Z|=|V|=3.

2. Optimal encoding of microinstructions. Representation (4) shows that excitation functionsфr єФ depend on all microinstructions Yqm c Y(U2). It is clear that hth line of DST with initial state ameA corresponds to Km=nY(am)nterms of the kind (4). Here Y(am) is a set of microinstructions that are formed under the transactions in the state am є A. Therefore, disjunction normal forms

of functions фr єФ will include a disjunction

Vimzq v...v VkmmZSq . (10)

Where Vkm is a conjunction of variables vreV corresponding to the code K(Ykm) (k=1,...,km), Zqs is a conjunction of variables zr є Z corresponding to the code K(Yqs) of microinstruction that are formed under the transaction in the state of transaction as є A from the hth line of initial DST. If codes K(Y1m),...,K(Ykmm) belong to the same generalized interval of R2 — dimensional Boolean space, then the expression (10) corresponds to single term

f R2 Л v

r=1

r

fR2 1

л zrsr

r=1

(11)

Here lmr є {0,1,*} is a value of the rth bit of the code C(am) corresponding to this generalized interval, vr0=~vr, vr1=vr, vr*=1, lsr є {0,1} is a value of the rth bit of the code K(Yqs), Zr0=~Zr, Zr1=Zr (r=1,,R2).

Therefore, the codes of microinstructions with equal upper index should be included in one generalized interval ofR2-dimensional Boolean space. Such encoding for Mealy FSM S1 is shown by the Karnaugh map (Fig.3).

Fig. 3. Optimal encoding of the microinstructions of Mealy FSM S1

Now generalized interval C(a3)=10* covers the codes K(Y23)=100 and K(Y33)=10L From Fig.3 the following codes can be formed: C(a1)=00*, C(a2)=01* and C(a4)=11*. If state ameA corresponds to Im < km generalized intervals, then subtable of initial DST corresponding to the state am є A should be represented by Im identical subtables with different codes C(am)i

(i=1,...,Im).

3.Identification of the microinstructions. Let M1=max(m1,...,mQ), then it is enough

R3 = Jog2Mi[ (12)

variables to identify all microinstructions Yqm c Y(U2). Let’s use the variables wre W={w1,...,wR3}to encode each microinstruction Yqm c Y(U2) by binary code

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C(Yqm). In this case each MI Yqm c Y(U2) corresponds to the code E(Yqm) that is determined as a concatenation

e(y;)=(lq,...,lN) * CYqm) • (13)

Here lnqe {0,1} and lnq=1 if yneYqm (n=1,...,N), *is a sign of concatenation.

For our example we have Mi=2, R3=1, W={wi}. Let C(Yi2)=C(Y23)=C(Y32)=C(Y44)=C(Y51)=0 and C(Yi4)=C(Y33)=1.

4.Formation of transformed DST. This table is a base to form the systems (1) and (5). It is formed by elimination of columns as, K(as), Fh from initial DST and including columns Yqs, C(Yqs) and Wh. The column Wh contains the variables wre W which are equal to 1 in the code C(Yqs) of MI from the hth line of initial DST.

In our case, the transformed DST is shown in the Table 2.

From table 2 functions can be formed, for example,

Уі = F2 V F7 = T1T2X1X3 V T1T2X2X3 ;

W1 = F3 V F4 V F5 = T1 T2 X1 X 3 V T1T2 .

Table 2

Transformed DST of Mealy FSM S1

am K(am) Xh Yh Yqs C(Yqs) Wh h

x1 y3 Y12 0 - 1

a1 00 ~x1 x3 y1 y2 Y23 0 - 2

~x1 ~x3 y3 Y14 1 w1 3

a2 01 x2 y 2 y4 Y33 1 w1 4

~x2 y3 Y14 1 w1 5

x2 у 2 y4 Y32 0 - 6

a3 10 ~x2 x3 y1 У2 Y23 0 - 7

~x2 ~x3 У3 У5 Y44 0 - 8

a4 11 1 - Y51 0 - 9

5.Formation of the table of code converter. This table is a base to form a system (6). It includes the columns Yqm, E(Yqm), Zq, q and column Zq that contains the variables zr є Z which are equal to 1 in code E(Yqm), q is a number of the line (q=1,...,Q1).

In our case this table includes Q1=7 lines (Table3).

Let F(Yqm) is a conjunction corresponding to the code E(Yqm). From table 3 functions Z can be formed, for example,

Z1 = Fy4) vf(y3) V f(y33) у Fy;) =

= У^У3У4У5^ V y1y2y3y4y5w1 V .

V У^У3У4У5^ V y1y2y3y4y5w1

Table 3

Table of the code converter of Mealy FSMS1

Y m 1 q E(Yqm) K(Yqm) Zq q

Y12 001000 011 z2 z3 1

Y14 001001 111 z1 z2 z3 2

Y23 110000 100 z1 3

Y32 010100 010 z2 4

Y33 010101 101 z1 z3 5

Y44 001010 110 z1 z2 6

Y51 000000 000 - 7

These functions can be minimized because they are depend only on Q1 from M2 = 2R+N possible terms. In

our case, for example, function z1 = y1 v y3 v y1w1 is formed from the Karnaugh map (Fig.4).

6.Formation of the table of excitation functions. This table is the base for formation of the system (7). It includes columns: am, C(am)i, Yqs, K(Yqs), Fh and h.

Fig. 4. Karnaugh map of the function z1

The subtables for each state ame A are duplicated Im times in such manner that there is subtable for each code C(am)i (i=1,...,Im). In common case this table has

M

Ho = 1 ImHm (14)

m=1

lines, where Hm is an amount of transactions from the state ameA.

In our case thanks to encoding shown in Karnaugh map (Fig. 3) Im=1 (m=1,...,4) and H0=H=9 (Tab.4).

Table 4

Table of excitation function of Mealy FSM S1

am C(8m)i Yqs K(Yqs) Oh h

Y12 011 D2 1

a1 00* Y23 100 D1 2

Y14 111 D1 D2 3

a2 01* Y33 101 D1 4

Y14 111 D1 D2 5

Y32 010 D2 6

a3 10* Y23 100 D1 7

Y44 110 D1 D2 8

a4 11* Y51 000 - 9

From this table functions F can be formed, for example,

D1 = E2 v E3 v E4 v E5 v E7 v E8 =

= v1v2z1z2z3 v v1v2z1z2z3 v v1v2z1z2z3 v

V v 1v2 z1z 2 z3

V v1v2z1z2z3

V v1v2z1z2z3

7.Synthesis of logic circuit of Mealy FSM U2. All combinational circuits of Mealy FSM U2 are implemented using PLDs. The problems related with design of such circuits are discussed in [2,6] and they are under the scope of this article.

4. Conclusion

The proposed method permits to save the maximal possible performance of digital system and to decrease the cost of the control unit in comparison with the

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system using a single-level implementation of Mealy FSM. The optimal encoding of microinstructions permits to decrease the amount of the terms of the system of excitation functions to the amount of the direct structural table lines of initial Mealy FSM.

The method is the most effective if L+R>2R2 and if N,...,20. The researchers of authors shown that under such conditions the cost of the Mealy FSM U2 circuit can be 20% less than cost of single-level circuit of equivalent Mealy FSM.

References: 1. Baranov S. Logic Synthesis for Control Automata — Kluwer Academic Publishers, 1994. 312 pp. 2. Grushnitsky R.I., Mursaev A.H., Ugrjumov E.P. Design of the systems using microcircuits of programmable logic — Petersburg: BHV, 2002. 636pp (in Russian). 3. Solovjev V. V. Design of the functional units of digital systems using programmable logic devices. Minsk: Bestprint, 1996. 252pp (in Russian). 4. Barkalov A.A. Synthesis of control units on programmable logic devices. Donetsk: DNTU, 2002. 262pp (in Russian). 5. Barkalov A.A, Palagin A.V. Synthesis of microprogram control units. Kiev: IC NAC of Ukraine,

УДК 519.713:681.326

ПОВЫШЕНИЕ КАЧЕСТВА ТЕСТА НА ОСНОВЕ ТЕХНОЛОГИИ BOUNDARY SCAN

КАКАЛОВ В.И., КАМИНСКАЯ М.А., ЕГОРОВ АА, ПОБЕЖЕНКО И.А.

Предлагается метод повышения качества теста в процессе моделирования неисправностей цифровых систем, основанный на стандарте IEEE 1149.1 Boundary Scan и тестопригодном анализе линий схемы в целях введения дополнительных точек контроля, вычисленных по технологии CAMELOT.

1. Введение

Актуальность исследования определяется необходимостью повышения быстродействия средств моделирования, улучшения качества теста и уменьшения его размерности для цифровых систем на кристаллах, имеющих миллионы вентилей. Высокие затраты, обусловленные трудоемкостью верификации функционально- и структурно-сложных схем, могут достигать 70% от общего времени разработки проекта. Для снижения таких затрат был разработан стандарт IEEE 1149.1 Boundary Scan, предназначенный для уменьшения времени синтеза тестов, моделирования неисправностей и диагностирования физических дефектов на стадиях производства и эксплуатации цифровых изделий . Однако соединить преимущества упомянутого стандарта с известными методами генерации тестов и анализа их качества — непростая проблема, связанная с оптимизацией функционала f = <T, F, Y>, заданного параметрами: <тест, проверяемые дефекты, выходы схемы>. Частичное решение этой проблемы рассматривается ниже.

Обьект тестирования — цифровая схема, представленная структурно-функциональной моделью.

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1997. 136 pp (in Russian). 6. Solovjev V.V. Design of digital systems using the programmable logic integrate circuits. Moscow: Hot line — Telecom, 2001. 636 pp (in Russian).

Поступила в редколлегию 30.03.2004

Рецензент: д-р техн. наук, проф. Хаханов В.И.

Alexander Barkalov, Doctor of Technical Science, professor of The University of Zielona Оуга, Faculty of Electrical Engineering, Computer Science and Telecommunication, Institute of Computer Engineering and Electronics. Address: ul. Podgуma, 50, 65-246 Zielona Оуга, Poland.

Phone: (+48 68) 328 2693. E-mail: a.barkalov@iie.uz.zgora.pl

Arkadiusz Bukowiec, M.Sc.,

university assistant, University of Zielona Gora, Faculty of Electrical Engineering, Computer Science and Telecommunication, Institute of Computer Engineering and Electronics. Address: ul. Podgуma,

50, 65-246 Zielona Gуra, Poland.

Phone: (+48 68) 328 2526. E-mail: a.bukowiec@iie .uz .zgora.pl

Цель исследования - получение минимального теста путем введения дополнительных наблюдаемых линий, используемых в технологии Boundary Scan.

Задачи исследования:

1) минимальное увеличение количества наблюдаемых линий, обеспечивающего повышение качества фиксированного теста до 100% ;

2) минимизация фиксированного теста, имеющего 100% качество, путем увеличения количества наблюдаемых линий и решения задачи покрытия;

3) определение минимального числа дополнительных наблюдаемых линий цифрового устройства на основе метода CAMELOT.

2. Boundary scan архитектура

С начала 80-х годов активно внедряются технологии тестопригодного, а в последнее время и производственно-пригодного проектирования цифровых изделий, ориентированного на непрерывность процесса превращения проекта в производимое электронное изделие. Такая тенденция, впервые отмеченная в 2001 году, получила название “Design for Manufacturability — проектирование для производства” [1]. Это означает не только встроенное самотестирование (BIST), но и встроенное самовосстановление (BISR), а также отказоустойчивость и надежность. Концепция WYSIWYG — what you see is what you get — осталась в прошлом. При этом проблема логического проектирования, связанная с отказоустойчивостью и ремонтопригодностью переносится в плоскость введения избыточности на благо производства — Manufacturability.

Для решения упомянутой проблемы широко используется стандарт Boundary Scan IEEE 1149.1 [2] в целях упрощения тестирования печатных плат, который имеет также и другое наименование — JTAG, по названию группы его создателей — Joint

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