Implementing Control Units for Linear Algorithms Текст научной статьи по специальности «Медицинские технологии»

Implementing Control Units for Linear Algorithms

Alexander Barkalov, IEEE member; Larysa Titarenko; Alexander Miroshkin

Abstract—Two methods are proposed for reducing the number of LUT elements in logic circuits of compositional microprogram control units with code sharing. The methods are based on usage of free resources of embedded memory blocks for representing the codes of the classes of pseudoequivalent operational linear chains. It allows reducing the number of LUTs in the block of microinstruction addressing. The example of application and results of investigations are given.

Keywords: compositional microprogram control unit,

FPGA, LUT elements, embedded memory blocks, hardware reduction.

If a control algorithm is represented by a linear GSA, then a control unit can be implemented as a compositional microprogram control unit (CMCU) [12]. The positive feature of CMCU is usage of all recourses of FPGAs (both LUTs and EMBs). It allows obtaining logic circuits with minimum possible amount of LUTs [12].

In this article, some improvements are proposed for the CMCU with code sharing. They are based on specific of both Moore finite-state-machine (FSM) [3] and EMBs. Let us point out that the proposed approach can be used for any model of CMCU [12].

I. Introduction

II. The model of CMCU with code sharing

As a rule, digital systems include control units responsible for interplay of all system blocks [1]. The behaviour of a control unit (CU) is determined by a control algorithm of a digital system. Such an algorithm can be represented as a graph-scheme of algorithm (GSA) [2]. one of the very important problems connected with design of CUs is a reduction of hardware amount required for implementing the CU’s logic circuit [3]. Methods used for solution of this problem depend on peculiarities of both logic elements used for implementing logic circuits and control algorithms to be interpreted [2].

Now, the field-programmable gate arrays (FPGA) [4, 5] are widely used for implementing logic circuits of digital systems. In this article, we discuss FPGA chips including look-up table (LUT) elements and embedded memory blocks (EMB) [6].

The specific of LUT is the limited number of inputs (up to 6-8). It is known that to decrease the amount of LUTs in a circuit it is necessary to decrease the numbers of both arguments and product terms in a Boolean function to be implemented. The specific of EMBs is their ability for reconfiguration in the frames of particular size. For example, the configurations 16kx1, 8kx2, 4kx4, 2kx8, 1024x18, 512x36, and 256x72 exist for typical EMBs [4, 5]. An EMB targets implementing tabular functions. It is quite possible that either some cells, or outputs, or both are not used under implementing some systems of Boolean functions. There are a lot of researches devoted to FPGA-based design of control units [7-11].

Manuscript received November 8, 2012.

Alexander Barkalov: Uniwersytet Zielonogorski, Zielona Gora, Poland. [email protected]

Larysa Titarenko: Uniwersytet Zielonogorski, Zielona Gora, Poland. [email protected]

Alexander Miroshkin: Donetsk National Technical University, Ukraine. [email protected].

Let a GSA Г include a set of vertices B and a set of arcs E. Let B = {b0, bE} u B1 u B2 where b0 is an initial vertex; bE is a final vertex; B1 is a set of operator vertices; B2 is a set of conditional vertices. Operator vertices bm e B1 include collections of microoperations Y(bm) c Y, where m = 1,M , M = |Bi|, Y = {y1, ...,>v}is a set of

microoperations. Conditional vertices bq e B2 contain elements of a set of logical conditionsX = {xb ...,xL}. Let us introduce some definitions.

Definition 1. An operational linear chain (OLC) ag of GSA Г is a finite vector of operator vertices ag = (bg ,...,bg > such that an arc <bg ,bg )eE

& 61 & Fg 61 *,+1

corresponds to each pair of adjacent components of ag

(i = 1, Fg -1).

Definition 2. An operator vertex bm e Bg, where Bgc B1 is a set of operator vertices from the OLC ag, is called an input of OLC ag if there is an arc {bt, bm> e E, where bt £ Bg.

Definition 3. An operator vertex bm e Bgis called an output of OLC ag if there is an arc (bm, bt> e E, where bt £ Bg.

Definition 4. Operational linear chains a,- and a,- are pseudoequivalent operational linear chains (POLC) if there are arcs {bh bt>, (b,, bt> e E, where bt (bj) is the output of OLC a,- (a,).

Definition 5. A GSA Г is called a linear GSA if the following condition takes place:

M „ — > 2.

G

(1)

So, a GSA Г is a linear GSA if the number of its operator vertices at least twice exceeds the minimum number of OLCs. If condition (1) takes place, then the model of CMCU can be used [12]. Let us point out that an arbitrary OLC ag can have up to Fg = |Bg| inputs and exactly one

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output, Og. The inputs of OLC ag form a set

I (ag ) = {I g, Ig2,...}.

Let us use the approach [12] and find the partition C of the set B1 such that C = {ab aG}. Let G be the

minimum possible number of OLCs for the GSA Г. Let us encode each OLC ag e C by a binary code K(ag) having R1 bits:

Ri = riog2Gl. (2)

Let us encode each component bg e Bg by a binary code K(bg ) having R2 bits:

R2 = riog2(Fmax)l. (3)

The value of Fmax is determined as Fmax = max (Fb FG).

Let us use the elements of a set т for encoding of the OLCs, whereas the elements of the set T are used for encoding of the components (|т| = R1, |T| = R2).

The encoding of the components is executed in the natural order:

K(bg+i) = K(bg ) +1; (g = hG;i = 1,Fg -1). (4)

Now, an operator vertex bm e Bg corresponds to the microinstructionMIm having the address A(MIm) determined

as

A(MIm) = K (ag )* K (bg). (5)

In (5), the sign * means the concatenation, whereas the vertex bm corresponds to the component bg of OLC

ag e C. In address A(MIm), the codes of OLC and its components are included separately (in the different bits of the address). This approach is called a code sharing.

On the base of (5), the model of CMCU with code sharing (CMCU CS) can be obtained (Fig. 1).

Fig. 1. Structure diagram of CMCU with code sharing

In the CMCU CS, a block of microinstruction addressing (BMA) implements systems of input memory functions for flip-flops of a register RG and a counter CT:

х¥ = х¥(т, X ); Ф = Ф(т, X).

(6)

This CMCU operates in the following manner. If Start = 1, then the process begins and zero codes are loaded into both RG and CT. At the same time, a flip-flop of fetching (TF) is set up. Now, there is Fetch = 1, and microinstructions can be fetched out the control memory (CM). Let in the instant t the contents of RG and CT form some address A(MIm) corresponding to the vertex bm e Bg. This microinstruction is fetched out the CM. If bm Ф Og, then a variable y0 is generated causing incrementing the counter CT. It provides the mode of addressing (4). In the instant t+1the next microinstruction is fetched; it still corresponds to some component of the OLC ag. If the output Og is reached, then the variable y0 is not generated. It allows loading both RG and CT from the outputs of BMA. Now, a transition is executed between the output of OLC ag and an input of some other OLC (maybe, the same OLC ag). The process is terminated when a variable yE is generated. It corresponds to the situation (Og, bE) e E.

The LUTs and latches are used for implementing logic circuits of BMA, RG, CT and TF, whereas the EMBs are used for implementing the control memory CM. If EMBs have some free recourses (cells, outputs or both), then we propose to use them for decreasing the number of LUT elements in the circuit of BMA.

III. The main idea of proposed method

As shown in [12], an OLC ag e C is an equivalent of some state of Moore FSM. So, pseudoequivalent OLCs correspond to the pseudoequivalent states of Moore FSM

[3]. It means that the table of transitions of CMCU CS can be reduced by replacing the pseudoequivalent OLCs by the corresponding class of POLC. It allows decreasing the number of product terms in the functions (6) and, therefore, the reduction of the amount of LUT s in the circuit of BMA. We proposed to keep the codes of classes of POLC in free recourses of EMBs. There are two possible approaches for usage of EMBs:

1. If there are enough free outputs, then the codes of classes of POLC can be included as a separate field in the microinstruction format. Let us call this approach as the expansion of microinstruction format (EMF-approach).

2. If there are enough free cells, then an additional microinstruction with the class code can be included into each OLC of a particular class. Let us call this approach as the modification of OLC (MOLC-approach).

Let us form a set C1 c C. Let ag e C1 if (Og, bE) <£ E. Let us find a partition Пс = {Bb ..., BI} of the set C1 by the classes of POLCs. It can be done in a trivial way, using the definition 4 from the section 2. Let us encode each class BI e nCby a binary code K(B) using R3 bits, where:

R3 = Tlog2Il. (7)

Let us use the variables zr e Z for such an encoding, where |Z| = R3. In this case the system (6) can be transformed in the following way:

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Y = ^(Z, X ); Ф = Ф(7, X ).

(8)

In the case of CMCU CS, the control memory should include Mo cells. Each of these cells has to bits:

Mo = 2^+Й2, (9)

to = N + 2. (10)

The value 2 is added to N to take into account the variables yo and yE.

The FPGA chip includes EMBs having Vo cells if the number of outputs tF = 1. Let us point out that the value of tF can be taken from some set of fixed values Of={1,2, 4, 8, 9, 16, 18, 32, 36,72}. Let us choose the value of ty e Of such that the difference At is minimal:

At = tF -to -R3 > o. (11)

Fig. 3. Structure diagram of CMCU MCS

Now, if the condition

(Vo/tF) > M o (12)

takes place, then the EMF-approach can be used. It results

in the CMCU FCS (Fig. 2).

Fig. 2. Structure diagram of CMCU FCS

In the case of MOLC-approach, the number of required memory cells is determined as

M1 = M +G. (13)

Let the following condition take place for any OLC

ag e C\\

Fg < 2R -1. (14)

In this case, the introduction of additional microinstructions does not increase the value of R2 in

comparison with (3). Now, the value of tF is chosen from the following condition

At = tF - to > o; (1

At ^ min.

If condition (14) takes place, then the MOLC-approach can be used leading to the CMCU MCS (Fig. 3).

Let us point out that the EMF-approach is more preferable. It does not require additional (idle) cycles of CMCU. So, it is necessary to start from the model of CMCU FCS. If this model cannot be used, then the model of CMCU MCS should be tried. Let us discuss the case when both models can be used and, moreover, only one EMB is enough for implementing the control memory. In other cases, the proposed methods need some modifications. The modifications are not complex, and, because of it, they are beyond the scope of this article.

The proposed design methods include the following steps:

1. Constructing the sets C, Cb Пс for a given GSA Г.

2. Encoding of OLC ag e C and their components.

3. Encoding of the classes Bt e По

4. Constructing the content of control memory.

5. Constructing the table of transitions of CMCU and finding the system (8).

6. Implementing the logic circuit using given FPGA chip.

The step 1 is executed using the methods from [12].As a

result, the number G of OLC ag e C is minimal. The partition Пс is formed using the definition 4.

The encoding of OLC should be executed in a way minimizing the number of terms in (8). The well-known methods [1] can be used to solve this problem. The components of OLC ag e C are encoded in a trivial way. The first component of any OLC has the code whose decimal equivalent is equal to zero. The codes of the second components are equal to 1, the third - to 2 and so on. This style of encoding satisfies to (4). The codes of classes do not affect the number o LUTs in the circuit of BMA.

The content of CM is represented by the table having the fields A(MIm), Y(bm), yo, yE, K(B) In the case of CMCU FCS, the fields Y(bm) and K(By) require different bits. In the case of CMCU MCS, these fields share the same bits of EMB. The number of required bits is determined as max (N+2; R3).

To construct the table of CM, it is necessary to transform the initial GSA Г [12]. If a vertex bm e Bg is not the output of OLC ag e C, then the variable yo is introduced into this

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vertex. If <bm, bE) e E, then the variable yE is introduced into the vertex bm e B1.

The table of transitions is constructed on the base of generalized formulae of transitions [12]:

H ---

Вг ^ vXhbm ;(i = 1,1). (16)

h=1

In (16), Xh is a conjunction of logical conditions determining the transition from the output of any OLC ag e Вг to the operator vertex bm; Hi is the number of transitions from this output. The system (16) leads to the table of transitions having the following columns: Вг, K(Bi), bm, A(MIm), Xh, Th, Фь, h. Here Th с T is a set of input memory functions for the RG; Фh с Ф is a set of input memory functions for the CT; h is a number of transitions. The system (8) is constructed as the following:

Dr = hhfCrhBhXh;(r = 1R2 + R3). (17)

h=1

In (17), Crh is the Boolean variable equal to 1 iff the function Dr is written in the h-th row of the table, Bh is a conjunction of variables zr e Z corresponding the code К(Вг) for the h-th row of the table (h = 1, H).

The last step is reduced to implementation of the logic circuit of CMCU using some standard tools [4, 5].

IV. An example of application of proposed methods

Let some GSA Г include M = 17 operator vertices. Let these vertices form the set C = {ab ..., a8} where ai = <bi, b2), a2 = <Ьз, b4, b5), аз = <b6, b7), a4 = {b%, b9, bw),

a5 = <b11, b12), a6 = <b13, b14), a7 = <b15, b16) and a8 = <b17).

It means G = 8, condition (1) takes place and the model of CMCU can be used.

Let a8 g C1, L = 4, N = 6 and Пс = {В1, ..., В4}, where

В1 = {ai, a6}, B2 = {a2, a3, a5}, B3 = {a4},

В4 = {a7}.Because there is G = 8, then R1 = 3 and т = {t1, t2, т3}. It can be found that Fmax = 3; it means that R2 = 2 and T = {T1, T2}. Let us encode the oLC ag e C in a trivial way: K(a1) = 000, K(a2) = 001, ..., K(a8) = 111. The first components at any oLC ag e C have the code 00, the second components have the code 01, the third components have the code 10 and the fourth components have the code 11. Let us point out that in the discussed example the fourth components are added into some oLCs of CMCU MCs.

The addresses of microinstructions can be found from Table I. In this table, the symbols (b18) - (b24) denote additional vertices introduced for CMCU MCs.

Let the following system of generalized formulae of transitions can be obtained after analysis of the GSA Г1:

Bj ^vx^b8 vxjxrb6; B2 ^x4bj5 B3 ^x3bji vx3b^; B4 ^x5.

v x4bi7;

(18)

Table I

Addresses of Microinstructions

OLC т3т2т1 T2T1 a1 000 a2 001 a3 010 a4 011 a5 100 a6 101 a7 110 a8 111

00 b1 Ьз b6 b8 bil b13 bl5 (b17)

01 b2 b4 b7 b9 b12 b14 b16 -

10 (b18) b5 (b20) bl0 (b22) (b23) (b24) -

11 - (b 19) - (b21) - - - -

Let us encode the classes Bi e nC in a trivial way: K(B1) = 00, ..., K(B4) = 11. Using these codes and the system (18), the table of transitions can be constructed (Table II).

Table II

Table of Transitions of CMCU

Bi K(B|) bm A(MIm) Xh Th Фь h

b3 00100 x1 Di - 1

Bi 00 b8 01100 x1x2 D2 Di - 2

b6 01000 x1 x2 D2 - 3

b15 11000 x4 D3 D2 - 4

B2 01

b17 11100 x4 D3 D2 D1 - 5

b11 10000 x3 D3 - 6

B3 10

b13 10100 x3 D3 D1 - 7

B4 11 b5 00110 1 Di D4 8

The addresses of microinstructions A(IMm) are taken from Table 1 using the expression (5). For example, b5 e B2 and K(a2) = 001. Therefore, A(MI5) = K(a2)*K(b5) = 00110.

Table 2 is the base for constructing the system (8). In the discussed case, this system is the following one:

Dj = Fj v Fr2 v F5 v F7 v Fg;

D3 = F4 v F5 v Fg v F7 ;

D2 = Fr2 v F3 v F4 v F5 ; D4 = F8,

(19)

where F1 = z1 z2x1, F2 = z1 z2x^2 , F3 = z1 z2x1 x2 , ...,

F8 = z1z2 .

Let У(Ьз) = {yi, уз, У0}, Y(b4) = {y4, У0}, Y(b5) = {У5}, Y(b6) = {y2,y0}, Y(b7) = {y3, y6}. Using addresses from Table I, the following fragment of content of control memory can be created for CMCU FCs (Table III).

Because the relation a2 e B2 takes place, the code K(B2) = 01 is placed into the cell with address 00110. This cell corresponds to the output of OLC a2. This very code is placed into the cell corresponding to the output of OLC a3.

In the case of CMCU MFs, the second and the third bits of microinstruction are used either as microoperations y1, y2 or variables z2, z1 (Table IV).

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Table III

Part of control memory for CMCU FCS

T3 Address T2 Ti T2 T1 yE У1 Microinstruction У2 Уз У4 У5 Уб У0 Z2 Z1 Ьт a

0 0 1 0 0 0 1 0 1 0 0 0 1 0 0 Ьз

0 0 1 0 1 0 0 0 0 1 0 0 1 0 0 b4 «2

0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 Ь5

0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 -

0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 Ьб аз

0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 b

0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 -

0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 -

Table IV

Part of control memory for CMCU MCS

Address Microinstruction

Тз T2 Т1 T2 T1 УЕ У1 Z2 У2 Z1 Уз У4 У5 Уб У0 bm аг-

0 0 1 0 0 0 1 0 1 0 0 0 1 Ьз

0 0 1 0 1 0 0 0 0 1 0 0 1 Ь4 а2

0 0 1 1 0 0 0 0 0 0 1 0 0 b5

0 0 1 1 1 0 0 1 0 0 0 0 0 Ь19

0 1 0 0 0 0 0 1 0 0 0 0 1 Ьб

0 1 0 0 1 0 0 0 1 0 0 1 0 Ь7 аз

0 1 0 1 0 0 0 1 0 0 0 0 0 Ь20

0 1 0 1 1 0 0 0 0 0 0 0 0 -

We do not show the logic circuits of these CMCUs. But we developed CAD tools allowing synthesis of proposed models of CMCU. Our CAD tools use Xilinx ISE WebPack to produce a final implementation.

V. Experimental results

our CAD system is based on the following principles. An initial GSA is represented in the XML format. One of its blocks generates VHDL-description of a given model of CMCU, together with data using for programming EMBs. This information is transferred into the system Xilinx ISE WebPack. Next, the implementation of a logic circuit is executed. The initial GSAs are generated by a special generator, which is the part of CAD tools:

- the number of vertices K is changed from 10 to 500;

- the part of operator vertices is changed from 50 % to 90 %;

- the number of microoperations N = 15;

- the number of logical conditions L = 5.

For each GSA, the following control units were implemented: CMCU with code sharing, CMCU FCS, CMCU MCS, and Mealy FSM. The experimental results are shown on diagrams. Each point on the diagrams is an average result obtained for five different GSAs with similar parameters.

The numbers of LUTs required for implementing logic circuits of different control units are shown on Fig. 4. The results for GSAs with 70 % of operator vertices are shown on Fig. 4, a. The results for GSAs with 90 % of operator vertices are shown on Fig. 4, b. Analysis of Fig. 4 shows that the proposed models of CMCU require fewer amounts of LUTs than both Mealy FSM and the base model of CMCU CS. Moreover, the growth in the number of operator vertices leads to increasing the hardware amount for Mealy FSM. But it has quite opposite effect in the cases

of CMCU.

Fig. 4. Number of LUT elements in logic circuits of control units

The temporal characteristics of different control units

shown in Fig. 5. As in previous case, results for GSAs with 70 % of operator vertices are shown in Fig. 5, a. Results for GSAs with 90 % of operator vertices are shown in Fig. 5, b. Both diagrams show minimal possible propagation time TC for the control units under investigation. The analysis if Fig. 5 shows that the proposed models provide higher performance in comparison with both Mealy FSM and CMCU CS. It is interesting that the propagation time does

Fig. 5. Minimal propagation time for different control units

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So, if the CMCU FCS and MCS require the same amount of EMBs, their characteristics (number of LUT elements and propagation time) are practically identical. Obviously, a control algorithm’s execution requires more cycles in CMCU MCS than in the case of equivalent CMCU FCS. It is connected with existence of additional microinstructions in the control memory of CMCU MCS. So, if there are such conditions that both proposed models can be used, then the model of CMCU FCS is more preferable.

Let us point out that results of investigation are obtained for the FPGA Spartan-3 by Xilinx. If other chips are used, the results can be different. But the tendency remains.

VI. Conclusion

As the results of investigations show, the proposed methods allow decreasing the hardware amount (in average) to 40% in comparison with known design methods.

one of the results of investigation is obtaining the formula showing the hardware amount required for implementing CMCU with code sharing and proposed modifications. Let us point out that this formula is correct for FPGA chips having LUT elements with four inputs (for example, for Spartan-3 family by Xilinx). The formula is the following:

Q = (-0.026Pj2 + 2.56P1 -10.11) • K (20)

In (20), Q is the number of LUTs in a logic circuit, K is the number of vertices in the GSA Г, Pi is a part of operator vertices in a GSA Г (0.5 < Pi < 1). Let us point out that the expression (18) is correct for L = 5. If similar formulae include L as a variable, then they can be used for preliminary estimation of hardware amount in the case of an arbitrary GSA.

The time Clock for proposed models is in the interval [1.7 nsec; 2.5 nsec]. As our investigations show, this interval is equal to [5 nsec; 6 nsec] for Mealy FSM. Moreover, this characteristic for CMCU depends only on the type of FPGA. In the case of Mealy FSM, delays increase with increasing the numbers of vertices in a control algorithm.

So, the proposed models of control units allow designing logic circuits with better hardware and timing characteristics in comparison with known models. Let us point out that they can be used only if a control algorithm is represented by a linear graph-scheme of algorithm.

References

[1] DeMicheli G., Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, 1994.

[2] Baranov S., Logic and System Design of Digital Systems, TUT Press, Tallinn, 2008.

[3] Barkalov A., Titarenko L., Logic Synthesis for FSM-Based Control Units, Springer, Berlin, 2009.

[4] Spartan-3 FPGA Data Sheets, www.xilinx.com/support/documentation/spartan-3.htm (Oct 22,

2012)

[5] Embedded Memory in Altera FPGAs, www.altera.com/technology/memory/embedded/mem-embedded.html (Oct 22, 2012)

[6] Navabi Z., Embedded Core Design with FPGAs, McGraw-Hill, New York, 2007.

[7] R. Senhadji-Navarro, I. Garcia-Vargas, G. Jimenez-Moreno, A. Civit-Ballcels, ROM-based FSM implementation using input multiplexing in FPGA devices, Electronics Letters (2004), 40 (20), 1249-1251.

[8] M. Rawski, H. Selvaraj, T. Luba, An application of functional decomposition in ROM-based FSM implementation in FPGA devices, Journal of Systems Architecture (2005), 51 (6-7), 424-434.

[9] V. Sklyarov, Synthesis and Implementation of RAM-Based Finite

State Machines in FPGAs, 10th International Conference «Field-Programmable Logic and Applications: The Roadmap to

Reconfigurable Computing» Proceedings, FPL 2000 Villach, Austria (August 27-30, 2000), 718-727.

[10] A. Tiwari, K.A. Tomko, Saving power by mapping finite-state machines into embedded memory blocks in FPGAs, Proceedings -Design, Automation and Test in Europe Conference and Exhibition (2004), 2, 916-921.

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Synchronous SelectRAM Blocks, Xcell Journal (2000), Issue 38, 3638.

[12] Barkalov A., Titarenko L., Logic Synthesis for Compositional Microprogram Control Units, Springer, Berlin, 2008.

Alexander A. Barkalov received Doctor of Technical Sciences degree in Computer Science from Institute of Cybernetics named after V.M. Glushkov (Kiev, Ukraine). From 2003 he is a Professor of Computer Engineering at the Department of Informatics and Electronics, University of Zielona Gora, Poland. His current research interests include theory of digital automata, especially the methods of synthesis and optimization of control units implemented with field-programmable logic devices. Address: Campus A, Budynek Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora. E-mail: [email protected]

Alexander N. Miroshkin, PhD student in Computer Science from Donetsk National Technical University (Donetsk, Ukraine). His current research interests include theory of digital automata. Address: Donetsk National Technical University, Ukraine. [email protected].

Larysa A. Titarenko received the M.Sc. (1993), PhD (1996) and Doctor of Technical Sciences (2005) degree in Telecommunications from Kharkov National University of Radioelectronics, Ukraine. From 2007 she is a Professor of Telecommunications at the Institute of Informatics and Electronics, University of Zielona Gora, Poland. Her current research interests include theory of telecommunication systems, theory of antennas and theory of digital automata and its applications. Address: Campus A, Budynek Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora. E-mail: [email protected]

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