Reduction of Hardware Amount for Control Unit with Address Transformer Текст научной статьи по специальности «Математика»

Reduction of Hardware Amount for Control Unit with Address Transformer

Alexandr A. Barkalov, Larisa A. Titarenko, Alexandr S. Lavrik

Abstract — The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given.

Index Terms—Address transformer, CMCU, CPLD.

I. Introduction

Complex programmable logic devices (CPLD) are widely used for implementation of logic circuits of control units [1]. As a rule, CPLD include macrocells of programmable array logic (PAL) [2], [3]. To design a logic circuit with optimal characteristics, some peculiarities of logic elements in use and a control algorithm to be interpreted should be taken into account. If a control algorithm is represented by a linear graph-scheme of algorithm (GSA), thin it can be interpreted using a model of compositional microprogram control unit (CMCU) [4]. One of the distinctive features of CPLD is the wide fan-in of macrocells [5], [6]. It can be used for increasing of the number of sources for classes of pseudoequivalent operational linear chains [7], [8]. The method is proposed in this article based on the abovementioned feature of CPLD, as well as on the replacement of logical conditions [1].

The aim of this research is reduction of the hardware amount in logic circuit of CMCU due to simultaneous use of more than one code source and the replacement of logical conditions. The task of research is the development of design method resulted in the hardware amount decrease for blocks of microinstruction addressing and microinstruction address transformer.

Manuscript received March 7, 2009.

A. A. Barkalov is with University of Zielona Gora, Poland. e-mail: A.Barkalov@iie.uz.zgora.pl

L. A. Titarenko is with University of Zielona Gora, Poland. e-mail: L.Titarenko@iie.uz.zgora.pl

A. S. Lavrik is with Donetsk National Technical University, Donetsk, Ukraine. e-mail: alexandrniordlavrik@gmail.com

II. Features of CMCU with microinstruction

ADDRESS TRANSFORMER

Let GSA Г be represented by sets of vertices B and arcs E. Let B = {b0 , bE }u E1 u E2, where b0 is an initial vertex, bE is a final vertex, Ej is a set of operator vertices, where |E1 = M, and E2 is a set of conditional vertices. A vertex bq e E1 contains a microinstruction Y (bq )c Y , where Y = &,... , yN} is a set of data-path microoperations [1]. Each vertex bq e E2 contains a single element of the set of logical conditions X = {x1,..., xL}. Let GSA Г be a linear GSA, that is a GSA with more than 75% of operator vertices.

Let us form a set of operational linear chains (OLC) C = {a1,...,aG} for GSA Г , where each OLC ag e C is a

sequence of operator vertices and each pair of its adjacent components corresponds to some arc of the GSA. Each OLC ag e C has only one output Og and the arbitrary

number of inputs. Formal definitions of OLC, its input and output can be found in [4]. Each vertex bq e E1 corresponds

to microinstruction MIq kept in a control memory (CM) of CMCU and it has an address A(bq). The microinstructions

can be addressed using

R = rlog 2 M1 (1)

bits, represented by variables Tr eT = {T1,...,TR}. Let OLC ag e C include Fg components and the following condition takes place:

A(bgi+1 ) = A(bgi)+ b (2)

In equation (2) bgi is the i-th component of OLC ag e C , where i = 1,...,Fg -1.

If outputs Oi, Oj are connected with an input of the same vertex, then OLC ai,aq e C are pseudoequivalent OLC (POLC) [2]. Let us construct the partition nC = {B1,..., Bj } of the set C1 c C on the classes of POLC. Let us point out

that ag e C1 if (<Dg,BE^ £ E . Let us encode the classes Bt enC by binary codes K(Bi) with

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R1 = fl°g2 11

4

bits and use the variables

(3)

тг e т = } for the

ag e C1 in such a manner that condition (2) takes place and the maximal possible amount of classes Bt e Пс is

encoding. In this case a GSA Г can be interpreted using the model of CMCU U1 with address transformer (Fig. 1).

The pulse Start causes loading of the first microinstruction address into a counter CT and set up of a fetch flip-flop TF. If Fetch = 1, then microinstructions can

be read out the control memory CM. If a current

microinstruction does not correspond to an OLC output, then a special variable y0 is formed together with microoperations Yq c Y . If y0 = 1, then content of the CT

is incremented according to the addressing mode (2). Otherwise, a block of microinstruction address BMA generates functions

Ф = Ф(, X)

(4

)

to load the next microinstruction address into the CT. In the same time, a block of address transformer BAT generates functions

т = т{Т). (5)

If the output of OLC ag £ C1 is reached, then yE = 1 . It

causes reset of TF and operation of CMCU U1 is terminated.

Such an organization of CMCU permits decrease of the number of terms in functions Ф from H1 till H0, where H1, H 0 is the number of terms for equivalent Moore

and Mealy finite state machines (FSM) respectively. But the block BAT consumes some macrocells or cells of PROM used for implementation of CM. In this article we propose some CMCU U2 , where H2 = H0 and the block BAT consumes less hardware then its counterpart in U1 . Here

represented by a single generalized interval of R-dimensional Boolean space. Such an addressing needs a special algorithm which should be developed.

Let Пс = ПA u ПB , where Bt e П A if this class is represented by one interval, and Bt e ПB otherwise. The counter CT is a source of the codes for Bt e ПA . If condition

П b = 0 (6)

takes place, then the block BAT is absent. Otherwise, only output addresses for OLC from classes Bt e ПB should be transformed. It is enough

R2 =|bg2 (ib + 1)l (7)

bits for such an encoding, where IB = |nB | and 1 is added

to take into account the case when B{ e ПA . Let us point out that some part of these codes can be implemented using free outputs of PROM. Let us use the hot-one encoding of microoperations [2] when CM word has N+2 bits. In this case the CM can be implemented using

R0 =

N + 2 t

(8)

chips with enough amount of cells (not less than M). Obviously, that R3 outputs of PROM are free, where

R3 = R0 * t - N - 2. (9)

If condition

R3 ^ R2 (10)

takes place, then the CM is a source of the codes for Bt e ПB and the block BAT is absent. This approach

permits to decrease the number of PAL macrocells in the logic circuit of block BMA, as well as the number of PROM chips used for the address transformation.

Further optimization of the block BMA logic circuit is possible due to the logical condition replacement [1]. In this case the set X is replaced by some set P = {p,... Pq }, where

Q << L . The structural diagram of CMCU U2 based on this principle is shown in Fig. 2.

In CMCU U2 , codes KA(Bt) of the classes Bt enA

are represented by variables Tr e T, whereas codes KB (Bj) of the classes Bt e ПB by variables vr eV , where

H 2

U 2

means the number of terms in functions Ф for CMCU

III. Main idea of proposed method

Let us point out that logic circuits for BMA, CT, TF and BAT are implemented as the parts of CPLD. To implement the CM one should use PROM chips with t outputs, where t e {l,2,4,8,16}. Let us address the components of OLC

IV = R2. In contrast to CMCU U1, there is no block BAT, and the block BMA implements functions

Ф = Ф(Т ,V, P). (11)

Variables pq e P are generated by a block of logical

conditions (BLC) as the following system

P = P(T ,V, X). (12)

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Let the symbol Ut (Гу) mean that CMCU U1 interprets Гу, and symbol Qi (Гу) determine the number of macrocells in the logic circuit of BMA for CMCU Ui (Гу), where i = 1,2. Let each macrocell have S inputs, where Gq variables pq e P are connected with inputs of the macrocell number q . The proposed method can be applied if the following condition

Qq + R + R2 < S (13)

takes place, where q = 1,...,Q1(ry-). If condition (13) is violated, the number Q2 (Гу) exceeds tremendously the number Q1(fy ).

The following method is proposed in our article for synthesis of CMCU U2 :

1. Constructions of sets C , C1, and ПC for GSA Г .

2. Microinstruction addressing.

3. Constructions of sets ПA and ПB .

4. Encoding of classes Bi e ПB .

5. Construction of control memory content.

6. Replacement of logical conditions.

7. Construction of CMCU transition table.

8. Specification of block BLC.

7. Implementation of CMCU logic circuit.

IV. Example of application of proposed method

Let the sets C = {a1,...,a9}, C1 ={,...,a8} and

nC ={,.. ., B5} be formed for a GSA Г1 , where

a1 = b2, , a2 = (b3,.. ., b6>; a 3 =(b7,b%),

a4 = " (b5,..., bu), a5 = (b4,... , b17 ) ■ a6 = oo Ъ-

a7 = : (b22,.. ., b2^, oo II CL ., b28 ) , a9 = b29,. .,b3^ ,

B1 = {a;1}, to II IT , a3 }, B3 = {4 ,a5}, B4 = {a6, a7 } ,

B5 = :{a}. Thus, I = 5 , R1 = 3, т = : {^"1, ^^, T3 },

M = -31, R =5.

Let us address the microinstructions using some modification of the algorithm from [4]. Now we have A(b1) = 00000,..., A(b25) = 110000, A(b26) = 11100,..., A(b28 ) = 11110, A(b29 ) = 11001,..., A(b31 ) = 11011. Let us construct the Karnaugh map marked by the variables

Tr e T = {Г1,...,T5} (Fig. 3). This map contains outputs of OLC ag e C and code space intervals corresponding to the classes Bi e nC .

The sign * in this map stands for the case when a vertex bq e E1 with address A(bq) is not the output of OLC

ag e C1. The following code intervals can be derived from Fig. 3: the class B1 corresponds to interval 0000*, the class B2to 001**, the class B3 to 01*** and 10000, the class B4 to 101** and 11000, the class B5 to 111**. Let us point out that a9 g C1 and the class B6 = [a9} is not considered here.

The obtained intervals determine the sets

ПA ={B1,B2,B5} and ПB ={B3,B4}. Let N = 12 for the GSA Г1 and t = 4 . In this case we have R3 = 2, condition (10) takes place, because R2 = |"log2 (2 +1) = R3.

Therefore, the model of CMCU U2 (Г1) can be applied and the block BAT is absent.

Let us encode the classes Bi e ПB in the following way: KB (B3 ) = 01, KB (B4 ) = 10. Now the code 00 corresponds to the case, when Bi e П A . The code 11 can be used for optimization of other codes. Finally we get KB (B3 ) = *1 and KB (B4) = 1*. Besides, the following codes can be derived from the Karnaugh map shown in Fig. 3: KA (B1 ) = 0000*, KA (b2 ) = 001**, KA (b5 ) = 111**.

The following procedure is proposed for construction of the control memory content, which can be viewed as some modification of the known method [4]:

1. q = 1.

2. If bq e E1, then the memory cell with address A(bq) contains Y (bq). Otherwise, go to point 6.

3. If bq is not the output of OLC ag e C, then the memory cell with address A(bg) contains yo .

4. If bq is the output of OLC ag g C1, then the memory cell with address A(bq) contains yE .

5. If bq is the output of OLC ag e C1, where ag e Bt, then the memory cell A(bq) contains code KB (Bi).

6. If all vertices of GSA Г are analyzed, then go to step

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7. Otherwise, q := q +1, go to point 2.

7. End.

There are no problems in this procedure application. So, this step in our article is omitted.

Let the transitions for classes Bj e Пс be specified by the following system of generalized formulae of transitions (GFT) [4]:

Bj ^ xjb3 v xjx4b5 v xj x4b7;

B2 ^ x3b9 v x3b26;

B3 ^ xjb18 v xjx2b20 v xJ x2b26; (j4)

B4 ^ x5b27 v x5b5;

B5 ^ x6b24 v x6x7b29 v x6 x7b19.

A GFT is a some modification of transition formulae using for finite-state-machines (FSM) [1]. The fact that OLCs replace FSM states is taken into account. Because all transitions are the same for OLC ag e Bj, then the classes

Bj e Пс are written into GFT. The expression “GFT”

underlines the fact of OLC outputs replacement by corresponding classes. Obviously, the transition for class Bj g Пс are not considered, because CMCU operation is terminated after generation of the variable yE .

Let X(Bj) be a set of logical conditions determing transitions from the class Bj e Пс , where |X(Bj) = Qj. Let Q = max(Qj|Bj e Пс), then logical conditions xt e X can be replaced by Q elements of the set P .

Using system (14), the following sets can be obtained: X (Bj) = {xj, x4 }, X (B2) = {x3}, X (B3) = {xj, x2 },

X (B4) = {5}, X (B5 ) = {x6, x7 }, Qj = Q3 = Q5 = 2,

Q2 = Q4 = j и Q = 2. Now we have the set P = {pj,p2}. Let us form a table for logical condition replacement having columns Bj e Пс and rows pq e P . If logic condition

xj e X is replaced by variable pq e P for class Bj e Пс ,

then the symbol xj is written on intersection of the row pq

and column Bj . The replacement is executed in a way

minimizing appearance of the same variable xt in the

different rows of the table (Table I).

tableI

Logical Condition Replacement for CMCU U2 (rj)

Bj Bi B2 B3 B4 Bs

pi xi xs xi - x6

F2 x4 - x2 xs xj

Let us transform the system of GFT by replacement of conditions xj e X by variables pq e P (using Table I in

our case):

bj ^ pjb3 v pjp2b5 v pj p2b7;

B2 ^ pjb9 v pjb26;

B3 ^ pjbj8 v pj p2b20 v pj p2b26; (j5)

B4 ^ p2b27 v p2b5;

B5 ^ pjb24 v pjp2b29 v pj p2bj9.

Such a system is used to construct the CMCU U2 transition table (Table II) having columns Bj,K(Bj),bq,A(bq),Ph,Фй,h . The system (j5) is used to

construct such a table for the CMCU U2 (rj). The table includes H = j3 lines, it is determined by the number of terms in system (j5). In this table there are two columns, KA (Bj) and KB (Bj), to represent the codes corresponding to the classes ПA and ПB .

table ii

Table of Transitions for CMCU U2 (rj)

Bj Ka (Bj) Kb (Bj) bq A(bq ) Ph Ф h h

bs 000j0 pj D4 j

Bi 0000* 00 bs 00Ю0 pj p2 Ds 2

bj 00П0 pj p2 Ds D4 3

bg 0Ю00 pj D2 4

B2 00!** 00 b26 Ш00 pj Di D2 Ds 5

bis j000j pj Di Ds 6

Bs ***** *0 b20 Ю0П pj p2 Di D4 Ds 7

b26 Ш00 pj p2 Di D2 Ds 8

B4 ***** j* b27 ПШ p2 Di D2 Ds Ds 9

bs 00Ю0 p2 Ds Ю

b24 ЮШ pj Di Ds D4 Ds П

Bs ш** 00 b2g n00j pj p2 Di D2 Ds j2

big Ю0Ю pj p2 Di D4 j3

The table of transitions is used to derive equations (П), having the following terms:

( R > ( r2 ^

Л Trrh * ЛVrE'h * Ph . (j6)

V r= J Vr=j s

In Q6), the symbol lrh e {0Д,*} stands for the value of bit r of the code KA (Bj) from the line h of the table, where Tr0 = T~r,Trl = Tr,Tr* = j (r = k...,R). The symbol

Erh e {0Д,*} stands for the value of bit r of the code KB (Bj) from the line h of the table, where Vr0 = Vr ,Vr1 = Vr ,Vr = j (r = k..., R2). In both cases we have h = j,.,H . For example, the following sum-of-the-products (SOP) can be derived from Table II:

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D = F5 v ... v F9 v Fn v F12 v F13 =

= T1T2T3 V1V2 P1 v V2 v V1P2 v T1T2T3 V1V2 (after minimizing of initial SOP).

The block BLC is specified by its table having the following columns: в,,KA(Bi),KB(Bi), P1,...,Pq,i (Table

III). The table is constructed using the initial table of logical replacement (see Table I).

TABLE III

Specification of Block BLC for CMCU U2 (Г)

в, Ka (B, ) Kb (B, ) p, P2 i

B, 0000* 00 x, X4 1

B2 001** 00 x5 - 2

B3 ***** *1 x, x2 3

B4 ***** 1* - X5 4

B5 111** 00 x6 x7 5

This table is used to derive system (12). For example, the following equation can be derived from Table III:

P1 = T1T2T3T4V1V2x1 vT1T2T3V1V2x3 v V2x1 v T1T2T3V1V2x6 .

Implementation of CMCU U2 logic circuit is reduced to

the implementation of systems (12)-(13) with PAL macrocells and control memory with PROM chips. There are many effective methods for solution of these tasks [3], because of it we do not discuss this step in our article.

V. Conclusion

The proposed method is oriented on hardware amount decrease in the logic circuit of microinstruction address transformer, which is the part of CMCU. This task solution is based on use of more than one source of codes for classes of pseudoequivalent OLC. As a limit, three sources can be used. Optimization of the logic circuit of block of microinstruction addressing is reached due to usage of the know method of logical condition replacement. It allows decrease for the number of required inputs of PAL macrocells. It gives an additional possibility in use of these free inputs for receiving of variables used for OLC classes encoding.

Unfortunately, the gain in hardware is accompanied by decrease of CMCU performance because of the propagation time of additional block BLC. Besides, this block consumes some recourses of the chip. Therefore, the proposed method can be applied if total hardware amount for BMA and BLC is less than hardware amount for BMA of equivalent CMCU U1 .

The scientific novelty of proposed method is determined by simultaneous use the PLA macrocells wide fan-in and logical condition replacement. It leads to hardware amount decrease for blocks BMA and BAT. If condition (10) takes place, then the block BAT is absent. The practical significance of this method is determined in decrease for the number of macrocells in CMCU logic circuit. It allows getting logic circuits with less hardware than for control units known from literature. Our investigation shows that

the number of macrocells is decreased up to 10% for cmcu u2 (r,) in comparison with equivalent CMCU

U1(r,).

There are two directions of our further research. The first, we should develop an algorithm permitting decrease for the number of OLC with outputs addresses to be transformed. The second, we should try this approach for CPLD based on programmable logic arrays [9], as well as on FPGA [10].

References

[1] Baranov S. Logic Synthesis for Control Automata. Kluwer Academic Publishers, 1994. 312 pp.

[2] Grushvitskiy R.I., Mursaev A.H., Ugrumov E.P. System’s Design by Using Programmable Logic Microchips - St. Petersburg: BHV, 2002. 608 p. (in Russian).

[3] Solov’ev V.V. Digital System Design based on Programmable Logic Integral Schemas - Moscow: Hot Line-TELEKOM, 2001. 636 p. (in Russian).

[4] Barkalov A., Titarenko L. Logic Synthesis for Compositional Microprogram Control Units. - Berlin: Springer, 2008. 272 p.

[5] Altera devices overview. http://www.altera.com/products/devices/common/dev-family_overview.html.

[6] Xilinx CPLDs

http://www.xilinx.com/products/silicon_solutions/cplds/index.htm.

[7] Barkalov A.A., Zeleneva I.Y., Lavrik A.S. Using PLIS peculiarities for control device schema optimization / Scinse Trans. of Donetsk Nationality Technical University. Series «Informatics, Cybernetics and Calculation Techniques». Issue 9 (132) - Donetsk: DonNTU. -2008. P. 178-182. (in Russian).

[8] Barkalov A.A., Kovalev S.A., Krasichkov А.А., Lavrik A.S. Control Devise Optimization with transformation of microcommands address с / Proc. of IX International Semnar.- Taganrog. Book. 3. 2008. P. 12-20.

[9] CoolRunner CPLD Datasheet. http://www.xilinx.com/support/documentation/coolrunner-ii.htm

[10] Maxfield C. The Design Warrior’s Guide to FPGAs. - Amsterdam: Elseveir, 2004. - 541 pp.

Alexandr A. Barkalov — Doctor of Science, Professor of the Donetsk National Technical University (Ukraine), Professor of the Uniwersytet Zielonogorski (Poland).

Scientific interests: digital control units, SoPC Address: Campus A, Budynek Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora E-mail: A.Barkalov@iie.uz.zgora.pl

Larisa A. Titarenko - Doctor of Science, Professor of the Kharkov National University of

Radioelectronics (Ukraine), Professor of the Uniwersytet Zielonogorski (Poland). Scientific interests: digital control units, telecommunication systems. Address: Campus A, Budynek

Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora

E-mail: L.Titarenko@iie.uz.zgora.pl

Alexandr S. Lavrik - Post graduate Student of the Donetsk National Technical University.

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