Organization of Control Units with Operational Addressing Текст научной статьи по специальности «Медицинские технологии»

Organization of Control Units with Operational Addressing

Barkalov A. A., Babakov R. M., Titarenko L. A.

Abstract — The using of operational addressing unit as the block of control unit is proposed. The new structure model of Moore finite-state machine with reduced hardware amount is developed. The generalized structure of operational addressing unit is suggested. An example of synthesis process for Moore finite-state machine with operational addressing unit is given. The analytical researches of proposed structure of control unit are executed.

Index Terms — control unit, graph-scheme of algorithm, operational addressing, hardware amount, operation of transition

I. Introduction

A control unit is one of the most important blocks of a vast majority of digital systems [1]. It can be organized as a finite-state-machine (FSM) where the input memory functions are represented by a system of Boolean equations [2]. As a rule, the hardware amount in the FSM’s logic circuit increases with the growth for the number of vertices and their interconnections in a control algorithm to be implemented [3].

The system of input memory functions is implemented as an irregular circuit. As a rule, it does not include standard functional blocks such as adders, decoders and so on [4]. Because of it, the process of control unit’s design causes many problems for designers of digital systems [1].

Now, the field programmable logic devices such as CPLD or FPGA are widely used for implementing logic circuits of digital systems [5]. There is a contradiction between the abilities of design libraries of CAD tools and the level of their usage in the design process of FSM’s circuits. The libraries include adders, shifters, multiplexors and other blocks up to microprocessor [6, 7]. On the other hand, only low-level elements are used for designing control units. It could be either look-up table (LUT) elements and embedded memory blocks (EMB) in the case of FPGAs or the macrocells based on programmable array logic elements in the case of CPLDs

[4]. In this article, we propose a new approach allowing

Manuscript received November 18, 2012.

A. A. Barkalov is a Professor of Computer Engineering at the Department of Informatics and Electronics, University of Zielona Gora, Poland. (corresponding author to provide e-mail: [email protected]).

R. M. Babakov is an Associate Professor at the Department of Informatics and Artificial Intelligence of Donetsk National Technical University, Donetsk, Ukraine (e-mail: [email protected]).

L. A. Titarenko is a Professor of Telecommunications at the Institute of Informatics and Electronics, University of Zielona Gora, Poland.

overcoming the gap between the content of CAD libraries and the current usage of primitive elements for designing FSM’s circuits.

In many practical cases, the FPGA-based Moore FSM is used [8]. There are a lot of methods using for minimizing the number of LUTs in an FSM logic circuit. The most efficient methods are connected with using multiplexers and EMBs for implementing the FSM logic circuits [9 - 11]. Application of these methods leads to decreasing for both the number of interconnections and power consuming. But it is quite possible situations when all resources of EMBs for a given chip are used for implementing other parts of a particular project. In these situations, it is impossible to use the EMB-based design methods for implementing control units. So, the problem of decreasing for the number of LUTs in the FSM logic circuit is still very important.

In this article, we propose the method of operational addressing which allows implementing the input memory functions using standard functional devices such as adders, shifters and so on. Our approach is based on implementing the input memory functions using some arithmetical and logical operations [12].

II. Proposed Organization of Control Unit

The main task of a control unit is the generation of a sequence of microoperations to control the actions of a system data-path [1]. This sequence is determined by both a control algorithm to be implemented and values of logical conditions to be checked. Let us use the term “operational automaton” for the system data-path. The operational automaton (OA) executes primitive operations (microoperations) using such blocks as adders, subtractors, multipliers, shifters and so on [13]. Let us name these blocks as “operational blocks”. There are no operational blocks in control units. The only exception is the application of counters in the microprogram control units [14]. In the case of FSM, the data processing is executed with help of logical operations. Sometimes, tabular functions are executed using some memory blocks. For example, the system of microoperations of the Moore FSM can be implemented using PROMs [4].

Let us consider a control unit represented by the Moore FSM (Fig. 1).

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Fig. 1. Structure diagram of Moore FSM

In this model, the block of input memory functions (BIMF) implements the system of input memory functions:

Let us use the term “an FSM with operational addressing” for the resulting FSM shown in Fig. 2.

Fig. 2. Structure diagram of FSM with operational addressing

Ф= Ф(Т, X). (1)

In the system (1), the set T=(Th TR} is a set of state

variables used for the state assignment, the setX={xh, xL} is

a set of logical conditions [3]. The set of internal states A includes M elements. It is known [3] that the minimum number of bits for state assignment is determined by the following equation:

R = Uog2M~\. (2)

The block of microoperations (BMO) implements the system of microoperations Y={yh, ..., yN}:

Y = Y(T). (3)

The system (3) can be implemented using, for example, PROM, whereas the system (1) requires logic elements for its implementing. The logic elements can be either gates, or macrocells of CPLD, or LUT elements of FPGA. The circuit of BIMF is irregular and its implementation causes the most of design problems. To diminish the number of logic elements in the BIMF very complex methods of functional decomposition are used [15-17], as well as different methods of state assignment [18-20]. When large library elements are used, these problems are solved before the implementing proposed FSM with operational addressing (OA).

Let us point out that the pulse Start is used to load the code of initial state into register RG. The pulse Clock is used for changing the content of RG (it is a code of a current state

am sA).

Let us transform the Moore FSM (Fig. 1) in the following way:

1. Each line of a table representing BMO includes two fields. The field FY contains information about microoperations to be executed in the state ameA. The field FO contains information about operations to be executed using K(a„) as an operand to obtain the code of the next state as sA.

2. The BIMF is represented as an operational addressing

unit (OAU). In each cycle of FSM’s operation, the OAU executes one of S operations fseF={fh, fS}. This operation

uses both the code of current state and values of logical conditions to calculate the code of the next state.

The proposed FSM with OA operates in the following order. If there is Start = 1, then the zero code is loaded into the register RG. It corresponds to the beginning of the operation. In each cycle the register contains a code of current state ameA. The BMO generates microoperations y„eY(am), where Y(a„)^Y is a set of microoperations generated in the state ameA. At the same time, the code K(am) determines the variables from the field FY. These variables enter the input of OAU and causes execution of some arithmetical or logic operations. As a result, new values of input memory functions ВгеФ are generated to load the code of the next state aseA into RG.

The very important specific feature of OAU is a limited number of operational blocks in use. It is connected with the fact that the number of operations f„eF is limited, too. For example, the following operations can be executed: the addition, the subtraction, the logic shift, the bit-wise inversion. The operations can be complex. It means they can be represented by a sequence of some asynchronous operations (for example, “shift ^ plus constant ^ negation ^ minus constant”). The set of operations F is constructed by the designer on the base of analysis of a control algorithm to be implemented. Let a control algorithm be represented by a graph-scheme of algorithm (GSA) [1].

III. General Synthesis Methods for FSM with Operational Addressing

Let us name the proposed approach for calculating codes of states the operational addressing. In this article, we propose two general methods for synthesis of the FSM with OA. In the case of operational addressing, each transition for a particular FSM is executed using only operations f„eF:

K(at+1) = fS(K(at),Xt). (4)

In (4), the symbol t stands for time (/=0, 1, 2, ...), ateA is a current state, at+1 is the next state (state of transition), f is some operation, determined by the field FO, Xt is a vector of logical conditions in the instant t, X =<x1t, x2, ...>, xite{0, 1}.

It follows from (4) that the state codes cannot be assigned in an arbitrary manner. They should “obey” to the operations f„eF. Therefore, two different approaches are possible for state assignment. In the first approach, the state codes are

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determined after the choice of operations f eF. In the second approach, the operations f„eF are determined after executing the state assignment. In both cases, a state code should be treated as a number (arithmetical value) used in the operations f„eF. At the same time, this number can be considered as a binary code used for addressing BMO.

So, two methods are possible for synthesis of FSM with OA. Let us denote them as M2 and M2 respectively.

The proposed method M2 includes the following steps:

1. Constructing the set of operations F.

2. Executing the state assignment on the base of operations fs^F.

3. Constructing content of the BMO.

4. Implementing logic circuit using given logic elements.

The proposed method M2 includes the following steps:

1. Executing the state assignment.

2. Constructing the set of operations F on the base of state codes.

3. Constructing content of the BMO.

4. Implementing logic circuit using given logic elements.

Let us point out the most important issue of the proposed

approach. The logic circuit of OAU is synthesized using standard operational blocks implementing operations fseF. It differ our approach from the classical one, where the logic circuit of BIMF is implemented using a system of Boolean functions. In the case of Moore FSM (Fig. 1), each transition corresponds to a unique product term. In the case of FSM with operational addressing, each operation from F can determine a lot of transitions. As a rule, the more transitions some FSM has, the more hardware its logic circuit needs. But the FSM with operational addressing does not obey this rule.

If each operationf eF is used for calculation more than one state code, then the hardware amount in the logic circuit of FSM with operational addressing can be less than in the logic circuit of Moore FSM. Moreover, the standard operational blocks are optimized on the transistor level [4]. It means that the hardware amount in the final circuit is optimal, too. Besides, the performance of FSM with OA can be higher in comparison with a multilevel circuit of BIFM.

To minimize the hardware amount of OAU, the authors recommend using the following rules:

1. The set of operations F should be minimally sufficient for implementing all possible transitions between the FSM states.

2. Functional blocks should be taken from the standard library elements. They should have the minimum possible number of bits.

As a conclusion, we can say that the using operational addressing leads to representing an FSM as a composition of an operational automaton, a register and a memory block. The proper choice of operations f eF provides a rigid connection between the FSM with OA and an initial control algorithm.

IV. Example of Synthesis

Let us discuss an example of synthesis for FSM with OA. In this example, we only show the basic design principles. Because the example is small, it cannot illustrate possible

gains in both hardware and performance. Of course, we cannot show a big example due to the lack of the article space.

Let the control algorithm be represented by a GSA Г1 (Fig.

3).

Fig. 3. Initial GSA Г1

Let us use the first design method and start from choosing the system F. Let us use the symbol a as a code of the state am eA in the instant t. Let it be the set F=ffh f2, f3} and let the functions f eF have the following meaning:

1) The function f corresponds to direct unconditional jump:

fi(a) = a — k. (5)

In (5), the symbol k stands for some constant.

2) The function f2 executes the conditional jump. It has two outcomes depended on the value of a logical condition to be checked:

t t \[2at + k, ifxt = 0; f2(at, xt) = \ (6)

[2at -k, if xt = 1,

Obviously, this function can be represented as two

subfunctions f20 (d) = 2d + k; (7)

f2j (a) = 2d — k. (8)

3) The function f3 corresponds to indirect unconditional

jump: f3(at) = d — l. (9)

In (9), the symbol l stands for some constant value.

Let us point out that these functions correspond only to GSA Г1. They can be different in the case of other GSAs.

Let us form a system of equations such that their roots determine the numbers corresponding to state codes. Each equation of the system is equal to the number H of possible transitions. Each transition is determined by one of the functions frf3.

Of course, any function from the set F can be used for executing some particular transition. But let us use the “transparent” approach. It means that transitions <a1y a2>, <a2, a3> and <a6, a> are executed using the function fj; the transitions <a3, a4> and <a4, a2> are executed using the

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subfunction f21; the transitions <a3, a5> and <a4, a6> are executed using the subfunction f20; the transition <a5, a3> is executed using the function f3. Taking it into account, the following system of equations can be created:

ai = f1(a6); a2 = f1(a1);

a2 = f1(a4); a3 = f1(a1);

1 (10)

a3 = f3(a5); a4 = f2(a3);

a5 = f2 (a3); a6 = f2 (a4 )■

Obviously, the roots of (10) should be integer. The integer values of roots are provided by values k=3, /=7. The solution of the system (10) gives the following state codes: K(a1)=10, K(a2)=7, K(a3)=4, K(a4)=5, K(a5)=ll, and K(a6)=13. Now we have a solution for the second step of the method M1.

The solution of the system (10) can be shown as a graph G(r1) (Fig. 4). Its initial, final and operator vertices contain the state codes. The arcs of G(T 1) are marked by the operations to be executed.

Fig. 4. Graph G(r 1) corresponding to GSA Г1

Let us denote the Moore FSM (Fig. 1) by the symbol U1, whereas the Moore FSM (Fig. 2) by U2. Let the symbol Ц(Г^) mean that the GSA Fj is implemented using an FSM Ui (i = 12).

There are only M=6 states in the FSM и1(Г1), but the maximum value of K(am) for и2(Г1) if equal 13. Therefore, there is R=3 in the case of и1(Г1), but R=r/og213]=4 for the FSM и2(Г1).

Let us execute the step 3 of the method M1. Because the outcome of operation f2 depends on the values of logical conditions, then these conditions should be encoded. Let K(x1)=0 and K(x2)=1, where K(x) is a code of a logical condition x/. It means that the table of BMO for the discussed case should include the one-bit field FX containing the codes of logical conditions. Let us encode the functions fS eF using binary codes having R1 bits where

R1 = Uog2S]. (11)

Let Щ)=00, K(f2)=01 and K(f3)=10. The table of the block BMO is constructed using the one-hot codes of collections of microoperations yneY, the codes of operations and the codes of logical conditions (Table I).

In this table the codes of states (addresses of cells) are determined by the binary equivalents of the roots of system (10).

The one-hot codes of collections of microoperations (field FY) correspond to the vector <y1y y2, y5>, whereyne{0,1}.

The symbol * in the table 1 corresponds to the “don’t care” situation for a given field. Obviously, there is a redundancy in the block BMO because only 6 from its 16 possible cells are used. The redundancy can be eliminated using the following approach.

tableI

Content of the BMO of Moore FSM и2(Г Q

at K(a) Address FY Y Z

0 0 0 0 * ** *

0 0 0 1 * ** *

0 0 1 0 * ** *

0 0 1 1 * ** *

a3 4 0 1 0 0 00100 01 0

a4 5 0 1 0 1 00110 01 1

0 1 1 0 * ** *

a2 7 0 1 1 1 11000 00 *

1 0 0 0 * ** *

1 0 0 1 * ** *

a1 10 1 0 1 0 00000 00 *

a5 11 1 0 1 1 01100 10 *

1 1 0 0 * ** *

a6 13 1 1 0 1 10011 00 *

1 1 1 0 * ** *

1 1 1 1 * ** *

Let us delete the second bit from all codes of states am eA. It results in obtaining different three-bit codes for states of FSM и2(Г1). These codes are the following: A'(a1)=110, A'(a2)=011, A'(a3)=000, A'(a4)=001, A'(a5)=111, and

A’(a6)=101. Because all codes are different, they can be used for the unambiguous identification of corresponding cells in the BMO (Table II).

TABLE II

Final content of the BMO of Moore FSM и2(Г Q

at A'(a) FY Y Z

a3 000 00100 01 0

a4 001 00110 01 1

010 * * *

a2 011 11000 00 *

100 * * *

a6 101 10011 00 *

a1 110 00000 00 *

a5 111 01100 10 *

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The last step of the method M1 leads to the structure diagram of FSM U2(T j) shown in Fig. 5.

X

Y

Fig. 5. Structure diagram of FSM ^(ГО

Now the minimum possible number of memory blocks (for example, PROMs) is necessary to implement the logic circuit of block BMO. The number of bits can be decreased using well-known methods of encoding of the collections of microoperations [13]. But these methods are beyond the scope of this article.

In FSM и2(Г1), the operational blocks f1-f3 implement the corresponding functions (5), (6), and (9). It is necessary to use a shifter one position to the left to multiply a state code by 2 [12]. If the numbers k, l are represented in the two’s-complement form, then all other operations can be executed using a binary adder [12]. The multiplexor of logical conditions MX1 generates the values of a logical condition xleX to be checked. The code K(xl) is represented by the field FX. The multiplexor MX2 chooses one from three possible codes of the next state. The choice is determined by the code from the field FO. The first, third and fourth bits of K(a„) form the address A' used for choosing a particular cell of BMO.

In the discussed example, we use the simplest possible structure of OAU. We merely wanted to illustrate the main principles of organization and design for proposed FSM with operational addressing. We do not discuss the method M2 in this article because it is very similar to the method M1.

V. Investigation of Moore FSM with Operational Addressing

Let us use the minimum hardware amount as an efficiency criterion of a particular FSM model. Let us

compare the hardware amount for blocks BIMF and OAU for equivalent FSMs. Let us use two-input gates as equivalent gates (EG) to make the required comparison.

Let the block BIMF of Moore FSM U1 implement the system of Boolean functions (1). Let these functions be represented in the sum-of-product (SOP) form [2]. The number of equations in (1) is equal to R, where the value of R is determined by (2). Let RLC be an average number of logical conditions in each term of the system (1). It means each term is represented by a conjunction having RT=RLC+R literals. Obviously, it is necessary H1 equivalent gates to implement each term:

H = Rt -1 = Rlc + R -1. (12)

Let each equation Dj-еФ includes T terms. This value corresponds to the amount of different paths in a GSA Г (different interstate transitions). Then, the number of EGs necessary to combine T terms is equal to

H 2 = T-1. (13)

The system Ф includes R functions; therefore, the value RH1 corresponds to a hardware amount necessary for implementing one transition. The value RH2 determines the hardware amount necessary for implementing the interterm connections for all equations of (1). Taking into account that a GSA includes T transitions, the total amount of EGs in the logic circuit of BIMF is determined as

Hk = R(THr + H2) = R(T(Rlc + R -1) + T -1). (14)

Usage some optimization methods [2] leads to decreasing the value of HK. To take it into account, let us introduce a coefficient of minimization k1=(0,1]. Now the formula (14) is transformed into the following one:

Hk = kRTRLc + R -1) + T -1). (15)

Let us estimate the hardware amount in the logic circuit of Moore FSM U2. Let us represent the hardware amount for OAU as

H OAU = H3 + H4. (16)

In (16), the symbol H3 stands for the hardware amount required by operational blocks f1-fS and the symbol H4 for implementing the multiplexor MX2.

The value of H3 depends on both the number of different operations of transitions and their complexity. To rough estimation of hardware amount in OAU, let us consider an average hardware amount HOP for implementing one operation of transition. In this case, the value of H3 is determined as

H3 = S • Hop. (17)

Let us point out that each new transition increases HK by some value HT, where

HT = R • H1. (18)

The value of (18) is constant for constant values of R and RLC. In the case of OAU, the situation is a bit different. If this new transition cannot be implemented using already existed operational blocks (OB), then some new OB should be introduced. It increases HOAU by the value HOP. This value is a constant too (if the growth of hardware in MX2 is neglected).

Let us introduce some coefficient k2 in (17). It is used for representing HOP through HT:

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Hop = k2HT = k2 RHV (19)

The value S in (17) is the most difficult for forecasting. It depends on many factors such as the structure of GSA and types of OBs to be used. Of course, the value of S is some function on T (the number of transitions), but it is impossible to find the exact universal function S(T) correct for any GSA Г. It is connected with the heuristic approach used for choosing both types and numbers of operations of transitions in the case of each GSA Г.

We conduct some experimental investigations allowing making the following conclusions. If T e[0, 10], then a new operation is added for approximately 2 new transitions. It means that S&T/2. If Te[10, 30], then a new operation is added for 5-7 new transitions. If Te[30, 100], then it is added for 10-20 transitions and so on. This dependence can be represented as the following expression:

S = k3ln (T/ 2 ) + 2. (20)

In (20), the coefficient k3 was obtained in the experimental way. For different GSAs, it belongs to interval from 2,5 to 5.

Using (19) and (20), the expression (17) can be represented as

H3 = (k3 ln (T/2) + 2)k2RHj ). (21)

The multiplexor MX2 generates the code of the next state (R bits) and it is controlled by the code from FO having RS=log2S] bits. Each output of MX2 generates a SOP having S terms. Taking into account the interterm disjunctions, the number of EGs required for implementing the MX2 is determined as:

H4 = R(S {log2 S]+ S-1. (22)

Using (21) and (22), the following expression can be obtained for (16):

Hoau = k ln(T/2) + 2)k2RBl + R(S^ S]+ S-1). (23) Let us find the efficiency of OAU respectively to BIMF of equivalent Moore FSM Uj as the following relation:

eoau = HK/HOAU. (24)

Obviously, if Eoau>1, then OAU has less amount of hardware than BIMF.

Let us find the dependence of EOAU from different parameters affecting the circuits of both OAU and BIMF. Let us use the following values for constants: R=10, T=2000, Rlc=2, k1=0,8, k2=30, and k3=3,5.

The function EOAU(T) is shown in both Table III and Fig. 6.

eoau

T

Fig. 6. Dependence of Eoau from the number of transitions T

As follows from both Table III and Fig. 6, this function is linear. The FSM U2 becomes more effective when T>800. The further growth of the number of transitions leads to growth of the gain.

The function Eoau(R) is shown in both Table IV and Fig. 7.

TABLE IV

Tabular form of function Eoau(R)

R

Eqal

R

Eqal

3 2,43 10 2,18

4 2,35 15 2,14

5 2,30 20 2,11

6 2,26 25 2,10

7 2,24 30 2,09

Eo

Fig. 7. Dependence of EOAU from the number of transitions R

TABLE III

Tabular form of function Eoau(T)

T Eoau T Eoau

200 0,32 1200 1,41

400 0,56 1400 1,60

600 0,78 1600 1,80

800 1,00 1800 2,00

1000 1,20 2000 2,18

Analysis of both Table IV and Fig. 7 shows that this function is restricted by the value 2,05. So, the circuit of OAU always needs less amount of equivalent gates than the circuits of BIMF.

The function EOAU(k1) is shown in both Table V and Fig. 8.

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TABLEV

Tabular form of function Eoau(k1)

ki Eoau ki Eoau

0,3 0,82 0,6 1,64

0,35 0,96 0,7 1,91

0,4 1,09 0,8 2,18

0,45 1,23 0,9 2,46

0,5 1,36 1,0 2,73

eoau

Fig. 8. Dependence of Eoau from the coefficient k

As follows from both Table 6 and Fig. 9, the growth of the average complexity of operational blocks used for executing transitions leads to decreasing of the efficiency of FSM U2. For used values of arguments, out approach can be applied till k2<65.

At last, the function EOAU(k3) is shown in both Table VII and Fig. 10.

TABLE VII

Tabular form of function Eoau(k3)

кз Eoau кз Eoau

1 6,44 6 1,31

2 3,62 7 1,13

3 2,51 8 0,99

4 1,93 9 0,89

5 1,56 10 0,80

The nature of this diagram is determined by the influence of k3 on the value of logarithmic function (20). The growth of k3 leads to increase for the number of operational blocks. If k3<8, then the proposed approach makes sense. Let us point out that an appropriate choice of operations of transitions leads to decrease of k3.

eoau

As follows from both Table V and Fig. 8, the increasing of coefficient of minimization for functions Ф leads to the linear growth of the efficiency Eoau. If ki=i (no minimization is possible), then Eoau reaches its maximum value equal to 2,73. only in the cases when the usage of minimization simplifies the system Ф up to 60% the application of FSM Uj makes sense.

The function EOAU(k2) is shown in both Table VI and Fig. 9.

TABLE VI

Tabular form of function Eoau(k2)

k2 Eoau k2 Eoau

10 6,32 60 1,10

20 3,25 70 0,95

30 2,18 80 0,83

40 1,64 90 0,74

50 1,32 100 0,66

eoau

k

2

Fig. 9. Dependence of Eoau from the coefficient k2

k

3

Fig. 10. Dependence of Eoau from the coefficient кз

Analysis of functions shown in Fig. 6 - Fig. 10 allows making the following conclusions. The following factors provide increasing for the efficiency of FSM with operational addressing in comparison with known models of Moore FSM:

1. The growth of the amount of transitions: the FSM with OA should be applied for implementing complex control algorithms.

2. The decrease of the value of bits in the states codes: in the ideal case these values should be equal for both equivalent Moore FSM and FSM with OA.

3. Implementing control algorithms with small rate of minimization.

4. The decrease for the average complexity of operational blocks used for implementing the operations of transitions.

VI. Conclusion

Application of the proposed approach of operational addressing allows implementing logic circuits of control units using only standard library elements of cAD libraries. This

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approach targets mostly FPGA- and ASIC-implementations of control units. This approach can decrease the hardware amount and increase performance of resulting control unit in comparison with known design methods. Of course, it is possible if some conditions discussed in our article take place.

Our investigations show that this approach should be applied for rather complex finite state machines having more than 80-100 states. But the growth of gain (hardware reduction) is possible only if each operational block executes more than one transition. It requires developing new state assignment algorithms targeting the proposed organization of control units.

Now, the authors develop design methods targeting usage more than one logical condition for executing the interstate transitions of Moore FSM. It permits the one-cycle execution of multidirectional transitions by the Moore FSM with operational addressing. Also, we develop methods for finding the set of operations leading to further saving the number of LUT elements in the logic circuits of Moore FSMs with operational addressing.

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[14] Barkalov A., Titarenko L.: Logic Synthesis for Compositional Microprogram Control Units. Springer, Berlin, 2008.

[15] Scholl C. Functional decomposition with application to FPGA synthesis. Kluwer Academic Publishers, Norwell, 2001.

[16] Kim T., Villa T., Brayton R., Sangiovanni - Vincentelli A. Synthesis of finite state machines: functional optimization. Kluwer Academic Publishers, Boston, 1997.

[17] Kania D., Milek A. Logic synthesis based on logic decomposition for CPLDs. Microprocessors and Microsystems, 2010, V. 34, Number 1. -pp. 25 - 38.

[18] Barkalov A., Titarenko L., Chmielewski S. Reduction in the number of PAL macrocells in the circuit of a Moore FSM. International Journal of Applied Mathematics and Computer Science, 2007, V. 17, Number 4. -pp. 565 - 575.

[19] Sutter G., Todorowic E., Lopez-Buedo S., Boemo E. Low-power FSMs in FPGA: Encoding Alternatives. Lecture Notes in Computer Science, 2451. Springer, Berlin,2002. - pp. 363 - 370.

[20] Slusarczyk A. Decomposition and encoding of finite state machines for FPGA implementation. PhD Thesis. Eindhoven, 2004.

Alexander A. Barkalov received Doctor of Technical Sciences degree in Computer Science from Institute of Cybernetics named after V.M. Glushkov (Kiev, Ukraine). From 2003 he is a Professor of Computer Engineering at the Department of Informatics and Electronics, University of Zielona Gora, Poland. His current research interests include theory of digital automata, especially the methods of synthesis and optimization of control units implemented with field-programmable logic devices.

Roman M. Babakov received the PhD degree in Computer Science from Donetsk National Technical University (Donetsk, Ukraine). From 2006 he is a Associate Professor at the Department of Informatics and Artificial Intelligence of Donetsk National Technical University. His current research interests include theory of digital automata, especially the methods of synthesis and optimization of control units implemented with field-programmable logic devices.

Larysa A. Titarenko received the M.Sc. (1993), PhD (1996) and Doctor of Technical Sciences (2005) degree in Telecommunications from Kharkov National University of Radioelectronics, Ukraine. From 2007 she is a Professor of Telecommunications at the Institute of Informatics and Electronics, University of Zielona Gora, Poland. Her current research interests include theory of telecommunication systems, theory of antennas and theory of digital automata and its applications.

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