Synthesis of Mealy FSM on verticalized flow-chart Текст научной статьи по специальности «Медицинские технологии»

КОМПЬЮТЕРНАЯ ИНЖЕНЕРИЯ И ТЕХНИЧЕСКАЯ ДИАГНОСТИКА

UDC 681.324

SYNTHESIS OF MEALY FSM ON VERTICALIZED FLOW-CHART

BARKALOVA., BUKOWIECA.

A method of improving of characteristics of Mealy FSM with encoding of the fields of compatible microoperations is proposed. Method is based on verticalization of initial flow-chart that permits to reach the full compatibility of all microoperations. In this case only one decoder is needed to implement the system of FSM microoperations. An example of proposed method application is given.

1. Introduction

Control unit of a digital system can be implemented as Mealy FSM [ 1]. The Field Programmable Gate Arrays (FPGAs) are used very often to design the logic circuits of FSMs [7]. The distinguished feature of FPGA is an existence of logic elements with limited amount of inputs, which are called as look-up-tables (LUTs) [5]. From another side, logic functions of FSMs have much more arguments (up to 200) than typical LUT (up to 6). This imbalance leads to decomposition of Boolean functions describing the behavior of automata [6]. The negative results of functional decomposition are increasing an amount of levels in the FSM circuit and decreasing of performance of a digital system in comparison with single-level implementation of control unit. The method of decreasing of amount of functions depending on logic conditions and internal variables of FSM is proposed in given article. It permits to decrease an amount of LUTs and levels of FSM circuit that leads to increasing of performance of control unit in comparison with well-known method of design [4]. The verticalization of initial flow-chart is the base of proposed method.

2. Analysis of Methods of FSM Design with Encoding of Fields of Compatible Microoperations

Let Mealy FSM is set up by a direct structural table (DST) with columns [2]: am , K(am), as, K(as), Xh , Yh , , h. Here am is an initial state of FSM,

am є A where A = {ai,...,aM} is a set of internal states ofFSM; K(am) is a code ofstate am є A having R =]log2M[ bits; as is a state of transition; K(as) is a code of state as є A ; Xh is a conjunction of some elements ofthe set oflogic conditions X = {x1,...,xl} that causes the transition < am,as >; Yh is the set of

microoperations formed under the transition < am,as >, РИ, 2005, № 2

Yh c Y , where Y = {y1,...,yN} is a set of microoperations; Ф h is a set of excitation functions that are equal to 1 to switch the FSM memory from K(am) to K(as), Фh сФ, where Ф = {ф1,...,is a set of excitation functions; h is a number of transition (h = 1,...,H). The internal variables Qr є Q , where Q = {Q1,..., Qr } is a set of internal variables are used to encode internal states of FSM. A DST is a base for formation of systems of Boolean functions describing the logic circuit of FSM:

o = o(Q,X), (1)

Y = Y(Q,X). (2)

These systems are used to design a single-level circuit of Mealy FSM (Fig. 1) that will be named as P FSM [2].

X-

Y

Fig. 1. A structural diagram of single-level circuit of Mealy FSM

Here circuit P implements the systems (1)-(2), register RG implements a memory of FSM using as a rule D flip-flops [8]. Such circuit has the highest possible performance in case of its implementation using PLA, PAL or CPLD. But in F PGA case it can be multi-level because of imbalance mentioned in introduction. The amount of functions with up to L + R arguments is equal to

t1 = R + N. (3)

One of the ways of optimization of hardware amount in a logic circuit ofFSM is decreasing of parameter h . It is possible due to application of encoding of fields of compatible microoperations [3]. The microoperations Уі, y j є Y are named the compatible ones if they never have met together in the operational nodes of initial flow-chart г . Let we have partition П = {B1,...,Bi} of set y by the classes of compatible microoperations. Let each microoperation yn є Bi is encoded by code K(yn) with Гі bits, where q =]log2(| B1 | +1)[

(i = 1,...,I). In this case Mealy FSM can be implemented as PD FSM (Fig. 2).

Y

Fig. 2. A structural diagram of Mealy PD FSM

49

Here circuit D is implemented using I decoders and each of them forms microoperations yn є B; (i = 1,..., I). Microoperations yn є Y are encoded using variables

I

from the set Z = {zi,...,zr } where Ri = £ri . Now

1 i=i

circuit P forms functions (1) and

Z = Z(Q,X). (4)

Therefore, it has only t2 < ti outputs, where

І2 = R + Ri • (5)

Thus, an amount of functions with amount of arguments up to l + R is decreased to t2 •

A disadvantage of such approach is relatively big amount of functions Z . The hardware amount can be decreased using maximal encoding of microinstructions together with encoding ofthe fields of compatible microoperations.

Let t is a total number of different sets of microoperations (microinstructions) that are written in operational nodes of flow-char г . Let’s encode each microinstruction Yt c Y by code K(yt) with R2 =]log2 T[ bits and let’s use the variables x r ет = {xp..x r2 } for such encoding. Let’s encode fields of compatible microoperations using method described above. In this case Mealy FSM can be implemented as triple-level Mealy PFD FSM (Fig. 3).

R3 =]log2 N +1[ bits using variables zr є Z . It leads to Mealy PD0 FSM (Fig. 4) where circuit D0 is implemented using only one decoder with R3 inputs and N outputs.

Here circuit P implements functions (1) and (4), circuit D0 forms microoperations yn є Y0 . Now circuit P has only t4 < t3 outputs, where

t4 = R + R3 . (8)

Let’s point out that PD0 FSM circuit has only two levels.

But the majority of real flow-charts are not vertical ones and they can not be interpreted using a model of Mealy PD0 FS M. In this article we propose to use an approach [3 ] that is named as verticalization of flow-chart. It leads to total compatibility of all microoperations of resulting flow-chart.

Y

Fig. 4. A structural diagram of Mealy PD0 FSM 3. The Main Idea of the Method

X

►Y

Fig. 3. A structural diagram of Mealy PFD FSM

Here circuit P forms systems (1) and

x = x(Q,X). (6)

It implements t3 < t2 functions with up to L + R arguments, where

t3 - R + r2 . (7)

Circuit F transforms inputs x into outputs z and can be implemented using ROMs. The embedded array blocks (EAB) of FPGA devices [5,7] can be used to implement circuit F.

Let flow-chart г contains k operational nodes forming a set O(T) = {Op...,Ok} . Let node Ok є O(r) contains Nk microoperations forming a set

Y(Ok) c Y , Y(Ok) = {yk | Уп є Y(Ok)} . Let’s

apply the procedure ofverticalization [3] to each node Ok є O(r). In this case each node Ok є O(r) is replaced

by sequence of nodes Pk =< OU-°N k > and each of new nodes contains only one unique microoperation уП є Y(Ok). Let’s name a resulting flow-chart v(r) as verticalized flow-chart (VFC). The subgraph of flowchart Ц before and after verticalization is shown on Fig.

5.

The method of this FSM design will be not discussed here but it should be pointed that this method has some disadvantages:

1. The amount of the internal states and lines of DST of PD0 FSM is greater than corresponding parameters of equivalent PD FSM on the value

The disadvantage of such approach is decreasing of performance in comparison with PD FSM because of existence of circuit F.

The best solution of the problem of decreasing of the outputs amount of circuit P without decreasing control unit performance is a case when each operational node includes only one microoperation. It corresponds to vertical flow-chart [3]. In this case each microoperation

yn є Y is encoded by code K(yn) with

k

A=l(Nk -1. (9)

k=1

It leads to the increasing of the amount of LUTs for implementation of system (1). But in the same time the amount of LUTs needed for implementation of the system z is decreasing.

2. The amount of cycles required for execution of microoperations yn є Y(Ok) in PD0 FSM is Nk

50

РИ, 2005, № 2

times greater than for equivalent PD FSM (k = 1, K) . It leads to significant decreasing of digital system performance. When microoperations yn є Y(Ok) have dependence on the data [4] such transformation is impossible. To eliminate second disadvantage the special signal y0 can be inserted in the last node of each sequence pk (k = 1,K) .

b

°3

°31

°з2

Fig. 5. The subgraph of flow-chart Tj before (a) and after (b) verticalization

synchronization can not pass to a data path. The microoperation yn = pqP k is written in the nth flip-flop of RY, using a local synchronization of microcell with particular LUT with output yn є Y . It is possible for each modern FPGA device [5].

When state aJNk is reached, yo = 0 and microoperations yn є Y(Ok) from the outputs YR of register RY can be executed in parallel by data path. After execution of current microinstruction register RY is reset and operation repeats till the reaching the final state ai є A.

The proposed approach permits to increase the performance of digital system and result depends on the relation of cycle times of control unit and data path. Let’s point that register RY is needed in any digital system with Mealy FSM to make this system a stable one [4].

4. The Method of the Synthesis of Mealy PDV FSM and Example of its Application

The method of Mealy PDV FSM design is proposed in this work and it is illustrated using subgraph of flowchart Ц (Fig. 5,a) corresponding to subtable of DST (Table 1).

Table J

am K(am) as K(as) Xh Yh Фь h

a2 001 a3 010 1 y1 y2 D2 1

a3 010 a4 011 X1 Уз D2 D3 2

as 100 ~X1 y4 У5 D1 3

Here R = 3 and K(a2) = 001,..., K(a5) = 100 .

The proposed method includes the following steps:

J. Verticalization of initial flow-chart Г and adding of signal y0 in the nodes ofverticalized flow-chart V(r).

2. Formation of the marked flow-chart v(r).

3. Maximal encoding of microoperations yn є Y by the binary codes K(yn ) with R3 bits and formation of the set Z .

Now a data path starts its operation only when all microoperations yn є Y(Ok) are formed and kept in some register RY. This situation is indicated by y0 = 0 . Such approach leads to PDV FSM (Fig. 6).

Fig. 6. A structural diagram of Mealy PDV FSM

A digital system with PDv FS M operates in the following manner. Let in the instant of time t (t=1,2,...) FSM is in the state a^ є A corresponding to the node ok (k = 1,...,K ). If Nk > 1 then y0 = 1 and pulse of

4. Encoding of the states of Mealy PDV FSM.

5. Formation of DST of Mealy PDv FSM.

6. Transformation of DST by replacement of the column Yh by columns K(yn), Zh , y0 . Here column Zh contains variables zr є Z, which are equal to J in the code K(yn) from the hth line of DST ofMealy PDV FSM (h = 1,...,H0 ; H0 = H + Д).

7. Formation ofsystems (J), (4) and y0 = f(Q,X) using the transformed DST.

8. Implementation of the FSM circuit using LUTs of FPGA.

After execution ofpp. 1-2 verticalized flow-chart V^) with signal y0 is formed (Fig. 7).

Let in our case N = 10, then R3 = 4 and Z = {z1,..., z 4 } . Let microoperations yn є Y have the

РИ, 2005, № 2

51

following codes: K(yj) = 0001, K(y2) = 0010 K(yio) = 1010 . Let m = 12 , then R = 3 and Q = {Q1,^5Q4>. Let K(a*) = 0010 ,

K(a 3) = 0011, K(a2) = 0100 , K(a4) = 0101 ,

K(a 5) = 0 1 1 0, K(a2) = 0 111.

The subtable of DST of Mealy PDV FSM in our case has H0 = 5 lines (Table 2).

The transformed DST of Mealy PDV FSM is formed in a trivial way (Table 3).

Fig. 7. Subgraph of verticalized flow-chart У(Гі)

Table 2

am K(am) as K(as) Xh Yh ®h h

a21 0010 a31 0011 1 y0 y1 D3 D4 1

a31 0011 a32 0100 1 y 2 D2 2

a32 0100 a51 0110 ~x1 y0 y4 D2 D3 3

a41 0101 x1 y3 D2 D4 4

a51 0110 a52 0111 1 у 5 D2D3D4 5

Table 3

am K(am) as K(as) Xh K(yn) Zh У0 ®h h

a21 0010 a31 0011 1 0001 z4 1 D3 D4 1

a31 0011 a32 0100 1 0010 z3 0 D2 2

a32 0100 a51 0110 ~x1 0100 z2 1 D2 D3 3

a41 0101 x1 0011 z3 z4 0 D2 D4 4

a51 0110 a52 0111 1 0101 z2 z4 0 D2D3D4 5

Functions (1), (4) and У0 can be represented as sum of products with terms

Fh = Aimxh = ( л Q1rmr)hXh (h = 1,H0), (10)

r=1

where Ajm is conjunction of internal variables Qr є Q corresponding to the code K(am) of the state from the hth line of transformed DST, lmr є {1,0}, q0 = Qr , Qr = Qr (r = 1,...,R ; h = f...,H0 ).

In our case, using Table 3, we can form, for example,

D2 = F2 V F3 V F4 V F5; z2 = F3 V F5; y0 = F1 v F3, where F1 = Q1Q2Q3Q4 , F2 = Q1Q2Q3Q4 ,

F3 = Q1Q2Q3Q4x1 , F4 = Q1Q2Q3Q4x1,

F5 = Q1Q2Q3Q4 •

The system of microoperations Y is implemented using one decoder with R3 outputs and N < 2R3 outputs.

The last step of our method is not discussed because methods of implementation of systems of Boolean functions for FPGAs can be found, for example, in the work [6]. Only main ideas of proposed methods are shown, so questions about organization of register RY are also under the scope of this article.

5. Conclusion

The proposed method of design of double-level circuit of Mealy FSM permits to decrease the amount of output functions depending on logic conditions and internal variables of FSM. The verticalization of initial flowchart permit to use only one decoder for implementation of the system of microoperations. The conducted researches have shown that proposed method permits to decrease the amount of LUTs in the FSM circuit up to 15-20% in comparison with method based on encoding of fields of compatible microoperations. The backside effect of verticalization of flow-chart is decreasing of the performance of digital system controlled by Mealy PDV FSM. But this effect can be diminished using proposed in this work method of data path synchronization.

References: 1. Baranov S. Logic Synthesis for Control Automata — Kluwer Academic Publishers, 1994 2. Barkalov A.A. Development of Formal Methods of Structural Synthesis of Compositional Automata — DonTSU, Donetsk 1994 3. Barkalov A.A. Synthesis of Control Units on PLDs — DonNTU, Donetsk 2002 4. Barkalov A.A. Synthesis of Operational Units — DonNTU, Donetsk 2003 5. Grushnitsky R.I., Mursaev A.H., Ugrjumov E.P. Design of the Systems Using Microcircuits of Programmable Logic — BHV, Petersburg 2002 6. „uba T. Synteza ukiadyw logicznych, WSISiZ, Warszawa 2001 7. Salcic Z. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization — Kluwer Academic Publishers, 1998. 8. Solovjev V. V. Design of Digital Systems Using the Programmable Logic Integrate Circuits — Hot Line - Telecom, Moscow 2001

Поступила в редколлегию 25.02.2005

Рецензент: д-р техн. наук, проф. Хаханов В.И.

Alexander Barkalov, Doctor of Technical Science, professor of The University of Zielona Gora, Faculty of Electrical Engineering, Computer Science and Telecommunication, Institute of Computer Engineering and Electronics. Address: ul. Podgorna 50, 65-246 Zielona Gora, Poland. Phone: (+48 68) 328 2693. E-mail: a.barkalov@iie.uz.zgora.pl.

Arkadiusz Bukowiec, Master of Science, assistant of The University of Zielona Gora, Faculty of Electrical Engineering, Computer Science and Telecommunication, Institute of Computer Engineering and Electronics. Address: ul. Podgorna 50, 65-246 Zielona Gora, Poland. Phone: (+48 68) 328 2526. E-mail: a.bukowiec@iie.uz.zgora.pl.

52

РИ, 2005, № 2