REAL NUMBER MODELING FLOW OF DIGITAL TO ANALOG CONVERTER Текст научной статьи по специальности «Компьютерные и информационные науки»

СХЕМОТЕХНИКА И ПРОЕКТИРОВАНИЕ CIRCUIT ENGINEERING AND DESIGN

УДК 621.3.087.92:001.891.573SystemVerilog DOI: 10.24151/1561-5405-2021-26-2-144-153

Real Number Modeling Flow of Digital to Analog Converter

* 1 * 2 3 * 13

V.Sh. Melikyan , V.D. Hovhannisyan ' , M.T. Grigoryan ' , A.A. Avetisyan1'3, H.T. Grigoryan1'3

1Synopsys Armenia CJSC, Yerevan, Armenia 2Aragats LTD, Yerevan, Armenia

National Polytechnic University of Armenia, Yerevan, Armenia vazgenm@synopsys.com

Abstract. This work introduces a flow of digital to analog (DAC) implementation in digital environment of SystemVerilog. Unlike the classical Verilog models, this digital to analog converter behavioral model is analog. Such type of model creation in general is called real number modeling. The DAC model is verified by the HSPICE and SystemVerilog Co-simulations which show its applicability in different register transfer level verification environments. The digital environment with real number modeled DAC runs around 8 times faster than the same environment with SPICE model. At the same time, the output signal's voltage difference between RNM and SPICE models is less than 2 mV.

Keywords. digital to analog converter; SystemVerilog; real number modeling; Co-simulation

For citation. Melikyan V.Sh., Hovhannisyan V.D., Grigoryan M.T., Avetisyan A.A., Grigoryan H.T. Real number modeling flow of digital to analog converter. Proc. Univ. Electronics, 2021, vol. 26, no. 2, pp. 144-153. DOI. 10.24151/1561-5405-2021-26-2144-153

© V.Sh. Melikyan, V.D. Hovhannisyan, M.T. Grigoryan, A.A. Avetisyan, H.T. Grigoryan, 2021

Маршрут моделирования цифроаналогового преобразователя

на действительных числах

1 2 3 13

В.Ш. Меликян , В.Д. Ованнисян ' , М.Т. Григорян ' , А.А. Аветисян1'3, А.Т. Григорян '3

1 Учебный департамент Синопсис Армения, г. Ереван, Армения 2ООО «Арагац», г. Ереван, Армения

Национальный политехнический университет Армении, г. Ереван, Армения

vazgenm@synopsys.com

Конструкции современных цифровых сложных систем в основном моделируются на нескольких языках описания аппаратных средств, например Verilog/VHDL, Spice, Verilog-A и др. Подобные языки предназначены для описания только цифрового поведения системы. Такой подход значительно ускоряет процесс проектирования и верификации. Однако аналоговые блоки, находящиеся в среде верификации, вызывают различные функциональные неточности, поскольку они не описываются должным образом. В работе предложено использовать моделирование цифроаналогового преобразователя (ЦАП) на действительных числах. Концепция заключается в описании требуемых аналоговых моделей на языке SystemVerilog и использовании их при верификации UVM вместо SPICE-моделей. Модель ЦАП проверена совместным моделированием HSPICE и SystemVerilog. Показана его применимость в средах проверки RTL. Установлено, что цифровая среда с ЦАП, смоделированная на действительных числах, работает примерно в 8 раз быстрее, чем такая же среда с моделью SPICE. В то же время разница в напряжении выходного сигнала между моделями на действительных числах и SPICE составляет менее 2 мВ.

Ключевые слова: цифроаналоговый преобразователь; SystemVerilog; моделирование на действительных числах; совместная симуляция

Для цитирования: Маршрут моделирования цифроаналогового преобразователя на действительных числах / В.Ш. Меликян, В.Д. Ованнисян, М.Т. Григорян и др. // Изв. вузов. Электроника. 2021. Т. 26. № 2. С. 144-153. Б01: 10.24151/1561-54052021-26-2-144-153

Introduction. The designs of modern digital complex systems are mostly modeled in several hardware description languages. The most common used hardware description languages are Verilog/VHDL, SPICE, Verilog-A, etc. Each language is unique in terms of simulation speed and signal description accuracy (abstract diagram is shown in Fig.1). Verilog/VHDL and similar languages are designed to describe only the digital behavior of the system. Signals have only 0,1, X and Z states and any analog signal levels are being ignored. Such approach significantly speeds up the design and verification process. However, the analog blocks which are considered to be in verification environments cause different functional inaccuracies as they are not being properly described.

Input languages of circuit level simulators are the opposite extreme. The models described by them are very accurate, they consider many physical aspects during the calcula-

tions and have small mistake probability. The main drawback is low design - verification speed. The accuracy of Verilog-A type languages is between those two languages. They use simple descriptions of digital logic and more complex analog cell descriptions. Modern IC Design companies perform system verification, however in some cases Verilog/VHDL description level is not enough. The problems are occurring in analog cells which are usually described as black boxes with pure behavioral descriptions. One of the modern solutions of this problem is the Co-simulation where the analog part of the design is instantiated as a SPICE cell and the digital part -as Verilog/VHDL cell [1]. The whole environment then is driven by a mixed-mode simulator which allows to combine two conceptually different models in one simulation.

However, the Co-simulation also has several problems. In practice digital environments are verified by universal verification methodology (UVM) regressions with thousands of simulations and each with randomized inputs and parameters. The Co-simulation cannot afford a big number of simulations, because the analog part of the environment is very resource consuming, hence the simulation time is a lot bigger compared to a fully digital environment.

To avoid mentioned problems, the real number modeling is used instead of Co-simulation. The concept is to describe required analog models in SystemVerilog language and use them during UVM verification instead of SPICE models. The SystemVerilog language is not intended for real number modeling, however due to its flexibility it fits all the requirements. The SystemVerilog is used as a base for RNM because the most widespread digital environment verification tool is the UVM. It is also written in SystemVerilog and is easily compatible with Verilog language. The user can replace digital models with RNM without additional tuning.

Real number model-based environment runs much faster than the one based on Co-simulation, hence allowing to keep the randomized regressions in place and greatly increasing the verification coverage. Also, the verification coverage is higher compared to the digital environment, because the suggested real number models also provide PVT randomization.

Digital to analog architecture. There are several common submodules which were implemented and used during the digital to analog (DAC) design: digital to analog converter; RC-filter; resistance ladder; analog multiplexer. The presented RNM DAC is based on the thermometer-coded DAC circuit [2] described in HSPICE [3]. The main advantage of such DAC is the high-precision voltage step. The main disadvantage is the number of components

Accuracy

Performance

Fig.1. Simulation accuracy to performance ratios

Resistance ladder Analog multiplexer

vdd

rhead ;

r[127]:

r[oi :

rfoot<

out

resulting more occupied area on silicon. Voltage buffer connected to the output can be accounted while it is not mandatory in terms of RNM vs HSPICE verification. In Fig.2, the block-diagram of 128 bit thermometer-coded DAC is presented. This architecture has been implemented for both SystemVerilog and SPICE formats for further research.

Problem description. The target is the creation of a functional RNM DAC model and its verification through comparison of RNM DAC signals versus the equivalent SPICE model. Several suggested RNM milestones should be met during model creation. The RNM and SPICE models should be simulated using the same SystemVerilog testbench.

Submodule descriptions. Digital to analog converter converts the input digital signals to the output analog voltage. Variables can be changed during the simulation via the cross-module reference assignments.

«Rise_time» and «fall_time» variables control on the positive and negative edges of output signal.

«High_volt» and «low_volt» variables control output voltage levels. «x_state» and «z_state» variables show output values when the input signal is at «X» or «Z» states. «Level» variable determines simulation output accuracy vs simulation time ratio. Higher «level» (from 1 to 6) provides lower number of datapoints, hence less simulation accuracy and faster simulations. Fig.3 and 4 show configuration variables' effects on the output signal.

И

Fig.2. Thermometer-coded DAC architecture

1 ... . 1 2 3n 4n 5n 6n 7n

logic in lb 1 1 1 1 1

realout 2" 1.5 1 SOOn 0 pr.......................

\

I 1 \

1 .....................\

high_volt 2 1 3 1.6 !«)........................;..........................;•••

low_volt 500a 400n lin)

200n lOOir

■ rise time[31:0] 32h

a fall time[31:0] 32h 1H_ I'KSCffit

Fig.3. DAC «rise_time», «fall_time», «high_volt», «low_volt» configuration variables and their effects

on the output signal in SystemVerilog simulator

2n in 6n 8n lOn 12n

logic in lb 1 1 1 i ii ii ii

realout 1 BOOn 6001 dm)

0 1

real_out 1" BOOn 60011 400n tlin) M м

M M ..........................M................M................\..................................... MM MM ..........................M.................M................i................. : H *

M M

I MM 3.........................;...................ы...............-.............................ы.....

level [Ii«...................

sec (fan) 2n n 6n 8n 1 n 12n 1

Fig.4. DAC «level» variable effect on the output

RC-filter model is used as a load model. It has 4 inputs and 1 output. «r» and «c» inputs show the RC-filter's resistance and capacitance values and the «vi» and «gd» inputs are the source. RC-filter's input and the ground node's potential. The «vo» output is the RC-filter's output. Fig.5 presents RC-filter module's block scheme with according parameters. Also, there is a «level» variable like the d2a converter's which control the simulation accuracy versus speed ratio. The core code of the RC-filter is the exponential dependency equations of voltage commutation. Fig.6 shows the commutation code written in the SystemVerilog model [4]. Fig.7 presents the effects of the 4 inputs and the «level» variable onto the RC-filter's output «vo».

vojrev^+ ((gd - vi) - vo prev) * (1 - Sexp(-t/(r»Cfilt)));

Fig. 6. RC-filter behavioral model

Fig. 7. RC-filter input effects onto the output

Resistance ladder outputs 128 analog signals based on the analog VDD supply voltage. The ladder has «rhead» and «rfoot» resistances which limit the maximum and minimum output voltages and 128 step resistors which provide 128 voltage steps. Resistance ladder block scheme is shown on Fig.2 connected with analog multiplexer.

Also, in real circuit there is a PVT factor. The PVT factor is represented as a «res_scale» variable. During the verification, the «res_scale» variable should be randomized in the range of (-1, 1), where 0 provides the nominal resistance values, -1 - (nominal - 10 %) and +1 - (nominal + 10 %). User can also exceed the range if there is a need. Fig.8 presents resistance ladder's analog functionality. It has 2 analog inputs - VDD, VSS and a 128 real bus outputs which later will go into the analog multiplexer.

Analog multiplexer receives 128 analog inputs from resistance ladder and 7 digital select bits. Based on the select bits it outputs one of the 128 analog inputs. Multiplexer's block scheme is shown in Fig.2, connected to the resistance ladder. Fig.9 presents the analog multiplexer's SystemVerilog model.

There were several milestones which this project was meant to achieve during model creation:

- keep as many inputs digital as possible;

- keep as much internal logic digital as possible;

- make the model PVT dependent;

- analog features (for example resistances) and internal structure of the model (number of interconnections) should be like the SPICE model;

- do not restrict the model with parameters so it can be changed during the simulation.

Listed milestones allow to create a universal model which can be used in many digital

environments. Of course, in practice it should be integrated and changed for every digital environment, however the efforts of integration should not be very high. On the other hand, by keeping the model close to SPICE and adding PVT randomization we are sure that the verification will bring out any crucial functionality mismatches.

The DAC model has 3 inputs - VDD, VSS, code, and 1 output - Q (VDD, VSS are the source nodes and are digital; «code» signal bus is the 7 bit select code of the DAC; «Q» is an analog output).

//......................................................

//......................................................

'timescale lps/lps

module resistanceladder ( input real VDD, input real VSS, output real n[127:0] );

real resscale » 0; real r_filt ;

real rstep ;

real rhead ;

real rfoot ;

assign rstep = (res scale > 0 ) ? 220 - res scale * 22 : 220 - res scale * 22 ;

assign rfoot = (res_scale > 0 ) ? 12600 - res_scale * 1260 : 126Q0 - res_scale * 1260 ;

assign rhead = (res_scale > 0 ) ? 2730 - res_scale * 273 : 2730 - res_scale * 273 ;

real vmax, vmin, vstep;

assign vmax = VSS + ( 128 * rstep + rfoot) * (VDD - VSS) / (rhead + 128 » rstep + rfoot); assign vmin = VSS + ( rfoot » (VDD - VSS) ) / (rhead + 128 * rstep + rfoot); assign vstep = ( vmax - vmin ) / 128 ;

genvar i;

generate for (i = 0 ; i

assign n[i] end

endgenerate endmodule

Fig.8. Resistance ladder module

//

//......................................

timescale lps/lps

module multiplexer ( input VDD,

input VSS,

input [6:9] select, input real in[ 127:0], output real 0

);

assign o = (-VDD & VSS) ? 8 : in [select] endmodule

Fig.9. Analog multiplexer module

There are 5 submodules instantiated in the DAC cell. Two d2a converters, a resistance ladder, an analog multiplexer and an RC-filter. According to the mentioned milestones the input source ports - VDD, VSS - are digital. However, the resistance ladder expects analog VDD and VSS inputs. To convert the signals, there are two d2a converters. The purpose of resistance ladder and the analog multiplexer is pretty straight forward - those 2 together are the DAC's core. The RC-filter acts as an analog load by filtering the «ideal» analog signal from the multiplexer (it can be seen from «vi» and «vo» signals from Fig.7 as an example). This is an important detail connected with the RC-filter's resistance. It should be calculated based on the resistance ladder's current select code. Fig.10 shows the detailed calculation of the RC-filter's resistance.

Also, there are several variables which should be configured from the top cells through a cross-module references. At the same time, the configuration variables are passed to the internal submodules. There are four configuration variables - «VDD_value», «VSS_value», «c_filt» and «level».

«initial» block passes configuration variable values to the internal submodules.

< 128 ; i = i + 1 ) begin = (i + 1) * vstep + vmin ;

assign rtop = resladd.rhead + (code + l)*resladd.rstep; assign rbottom = resladd.rfoot + (127 - code)»resladd.rstep;

assign r_fi.lt = (rtop * rbottom) / (rtop + rbottom);

Fig.10. RC-filter's resistance calculation

The «VDD_value» variable is passed to the VDD converters and affect the VDD signal's high level. In general, it is recommended to randomize this signal too as the voltage is also part of the PVT. Additionally, user can add noise to the VDD signal which in theory may lead to some interesting tests, like noise dependency or jitter measurements. The «VSS_value» variable is similar to the «VDD_value» except it is responsible for the VSS signal. «c_filt» variable is the output load which is passed as an input to the .C-filter module. «simula-tion_level» is passed to the d2a converters and the RC-filter. The effects of this variables are described in appropriate paragraphs.

Model verification. To have a reliable verification, the RNM model must be compared with SPICE model in exact same conditions. To execute such comparison a Co-simulation environment with SystemVerilog top testbench was created. The testbench is common between SPICE and RNM models and calls them in parallel. RTL testbench is also responsible for passing the RNM configuration variables to the RNM model. Fig.11 shows an abstract scheme of our Mixed-Signal verification environment.

RTL testbench

T T

Cross-module references

1 —1 ! ,

I- 'Iii' 1

Verilog to Spice interfacing

Spice model

Verilog to Spice interfacing

Configuration variables

RNM model

Ш

Fig.11. DAC RNM model verification environment

Fig.12 illustrates the SPICE model's schematic. It includes resistance ladder and a TG based multiplexer. All RNM resistors are matched with the SPICE resistors. The capacitive load is also matched. RNM model does not include TG resistances and internal transistor parasitic which however should not cause big differences.

Fig. 12. SPICE TG based DAC model

Simulation Results. Simulation checks all possible input code combinations. The resulting analog outputs are presented on Fig.13. There are glitches at the MSB code switching moments and they do not appear in the RNM simulation. The rest parts of the simulation are very close. The mean difference of the «ladder» part is 1.36 mV including the glitches which is a pretty good result.

Fig.13. SPICE vs Verilog wave to wave comparison

Table presents the results of several Co-simulations. First line shows the run time and the resulting wave file size of SPICE model. The rest of the lines show RNM model usage with different simulation level parameters.

Simulation results

Analog output's mean error against SPICE model, mV Resulting wave file (fsdb) size, MB

Model Simulation duration, s

SPICE model 0 8789.74 3784

RNM level 1 1.36 1096.89 4458

RNM level 2 1.54 232.33 999

RNM level 3 1.64 122.01 0.0537

RNM level 4 1.81 63.73 0.0281

RNM level 5 2.25 26.58 0.0119

RNM level 6 2.93 14.01 0.0063

Conclusion. An RNM DAC was implemented and verified against a similar SPICE model. Despite the introduced 2.93 mV across PVT mean error (which is acceptable in the most cases), the RNM DAC provides 8-628 times higher simulation speed compared to the SPICE. At the same time, the RNM model exists only in SystemVerilog domain which greatly simplifies its integration into already existing digital environments.

References

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2. Mixed-signal simulation user guide. Mountain View, CA. Synopsys Inc., 2014, pp. 1-134, 151-156, 213-259, 268-269.

3. Baker J.R. CMOS circuit design, layout, and simulation. 3rd ed. Hoboken, NJ, John Wiley and & Sons, 2010, pp. 965-970.

4. HSPICE reference manual. Mountain View, CA, Synopsys Inc., 2020, pp. 126-263, 374-401.

5. Kasatkin A.S., Nemcov M.V. Elektrotekhnica, Uchebnik dlya vuzov = College Textbook on Electrical Engineering. 9th ed. Moscow, Academia Publishing center, 2003, pp. 129-156. (In Russian).

6. Taraate V. System Verilog for hardware description - RTL design and verification. Gateway East, Springer Nature Singapore Pte Ltd., 2020, pp. 11-45.

7. Cavanagh J. Verilog HDL design examples. Boca Raton, FL, Taylor & Francis Group, LLC, 2018, pp. 1109, 146-176.

8. Verilog-A reference manual. Palo Alto, CA, Agilent Technologies, Sept. 2004, pp. 2-1-5-4.

Received 02.02.2021; Revised 02.02.2021; Accepted 08.02.2021. Information about the authors:

Vazgen Sh. Melikyan - Corresponding Member of RA NAS, Dr. Sci. (Eng.), Prof., Director of Educational Department of Synopsys Armenia CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), vazgenm@synopsys.com

Vardan D. Hovhannisyan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Engineer at Aragats LTD (Armenia, 375038, Yerevan, Abelyan st., 6-1), v.hovh99@gmail.com

Mushegh T. Grigoryan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. II Synopsys Armenia CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), hgrigo@synopsys.com

Ashot A. Avetisyan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. II Synopsys Armenia CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), aavet@synopsys.com

Hayk T. Grigoryan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. II Synopsys Armenia CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), hgrigo@synopsys.com

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