POWER SUPPLY RATIO IMPROVEMENT USING SELF-CALIBRATION IN VOLTAGE REGULATORS Текст научной статьи по специальности «Электротехника, электронная техника, информационные технологии»

yaK 621.382

DOI: 10.24151/1561-5405-2019-24-3-248-256

Power Supply Ratio Improvement Using Self-Calibration in Voltage Regulators

V.Sh. Melikyan1, A.K. Hayrapetyan1'2, H.T. Kostanyan1'3f

12 * 13 * 13

H.V. Margaryan ' , H.T. Grigoryan ' , A.A. Martirosyan '

1CJSC Synopsys Armenia, Yerevan, Armenia

2

Yerevan State University, Yerevan, Armenia 3National Polytechnic University of Armenia, Yerevan, Armenia

vazgenm@synopsys.com

Abstract. The effect of noises in the power supply networks increases due to reduction of the power supply voltage and an increase of switching speeds of the digital circuits. Therefore, the design of voltage regulators with high power supply rejection ratio (PSRR) is substantial. The voltage regulator to provide high PSRR while the load current is being changed, depending on many factors, such as the technological process, temperature, operating mode, operating frequency and operating frequency of the circuits connected to the voltage regulator, has been proposed. In existing voltage regulators, independently from the current load value the pass device should have a large size to provide the possible maximum current, hence, it has strong capacitive coupling with the output, which affects PSRR. It has been shown that the proposed regulator changes the conductance of the pass device by enabling or disabling the additional parallel units in addition to controlling the gate-source voltage. It has been stated that the calibration maintains better PSRR for different load currents whereas the disabled units almost do not affect PSRR. Simulation using the analytical programs HSpice has shown the better results as compared to existing voltage regulators. The minimum PSRR has been improved from 17.53 dB to 22.1 dB for voltage regulator with the NMOS pass device, when the load current has two times decreased. The area of LDO voltage regulator has been 24% increased due to the added control block.

Keywords. power supply rejection ratio; low drop-out voltage regulator

For citation. Melikyan V.Sh., Hayrapetyan A.K., Kostanyan H.T., Margaryan H.V., Grigoryan H.T., Martirosyan A.A. Power supply ratio improvement using self-calibration in voltage regulators. Proc. Univ. Electronics, 2019, vol. 24, no. 3, pp. 248-256. DOI. 10.24151/1561-5405-2019-24-3-248-256

© V.Sh. Melikyan, A.K. Hayrapetyan, H.T. Kostanyan, H.V. Margaryan, H.T. Grigoryan, A.A. Martirosyan, 2019

Улучшение коэффициентa подавления нестабильности питания с помощью самокалибровки в регуляторах напряжения

В.Ш. Меликян1, А.К. Айрапетян1'2, А.Т. Костанян1'31

12 13 13

А.В. Маргарян ' , А.Т. Григорян ' , А.А. Мартиросян '

1ЗАО «Синопсис Армения», г. Ереван, Армения 2Ереванский государственный университет, г. Ереван, Армения Национальный политехнический университет Армении, г. Ереван, Армения

vazgenm@synopsys.com

Воздействие шумов в сетях питания увеличивается из-за снижения напряжения питания и увеличения скоростей переключения цифровых схем. Поэтому разработка регуляторов напряжения с высоким коэффициентом подавления нестабильности питания (КПНП) очень важна. В работе предложен стабилизатор напряжения для обеспечения высокого КПНП при изменении тока нагрузки, зависящего от многих факторов, таких как технологический процесс, температура, режим работы и рабочая частота схем, подключенных к стабилизатору напряжения. В существующих стабилизаторах напряжения независимо от тока нагрузки для обеспечения максимального тока выходной каскад должен иметь большие размеры. При этом выходной каскад характеризуется сильными емкостными связями, что ухудшает значение КПНП. Показано, что предлагаемый регулятор помимо управления напряжением затвор-исток также управляет проводимостью выходного каскада путем включения или отключения дополнительных параллельных транзисторов. Схема управления сравнивает напряжение затвора транзистора выходного каскада с опорными напряжениями для определения необходимости изменения количества включенных транзисторов. Установлено, что калибровка обеспечивает высокий КПНП для различных токов нагрузки, так как отключенные транзисторы почти не влияют на его значение. Моделирование с помощью программы анализа HSpice показало улучшенные результаты по сравнению с существующими регуляторами напряжения. Минимальное значение КПНП возросло с 17,53 до 22,1 дБ для регулятора напряжения с p-МОП выходным каскадом и с 18,4 до 23,6 дБ для регулятора напряжения с n-МОП выходным каскадом. Площадь регулятора с низким падением напряжения увеличилась на 24 %.

Ключевые слова: коэффициент подавления нестабильности питания; регулятор с низким падением напряжения

Для цитирования: Улучшение коэффициента подавления нестабильности питания с помощью самокалибровки в регуляторах напряжения / В.Ш. Меликян, А.К. Айрапетян, А.Т. Костанян и др. // Изв. вузов. Электроника. - 2019. - Т. 24. -№ 3. - С. 248-256. DOI: 10.24151/1561-5405-2019-24-3-248-256

Introduction: Due to higher switching speeds and low supply voltages power supply noise has risen to a very high level of concern. Supply noise deteriorates the performance of

sensitive analog blocks [1-3]. Therefore, it is substantial to have voltage regulators (Fig. 1) [4, 5] with high power supply rejection ratio (PSRR) [6]:

PSRR = 20 log Ripplevdd .

RiPPleout

Fig. 1. Voltage regulator with NMOS pass device and charge pump (a); Voltage regulator with PMOS pass device (b)

The error amplifier gain should be increased, and high frequency filter or capacitor should be added for PSRR improvement. However, gain of amplifier is limited by various factors, such as area and power requirements, operating conditions, bandwidth, etc. On-chip capacitors have a large size and are constrained by on-chip area limitations. Those could occupy multiple times larger area than circuit itself. Besides, output current is controlled only by gate-source voltage of pass device [4, 5]. In such conditions regardless of load current, it should have a large size to provide possible maximum current, hence it has strong capacitive coupling with the output, which affects PSRR. The proposed regulator besides controlling gate-source voltage, changes the size of pass device, hence decreasing capacitive couplings with the output and improving PSRR for lower load currents.

Proposed voltage regulator. Voltage regulator could be used to supply various blocks at the same time. That means the current drawn from the voltage regulator could be changed dependent on operation mode, such as data transfer, idle, power saving, etc. and operating conditions, such as operation frequency of the supplied circuits. In conventional voltage regulators [4, 5] the pass device is the same for all loads. In the proposed design the size of pass device is being changed depending on load. When the size of pass device is smaller it has smaller capacitive couplings with the output. That's why controllable pass device provides higher PSRR. It can be represented as a simple capacitive divider, i.e. when the value of upper capacitance is smaller the voltage variation is lower in the output. The proposed voltage regulator consists of three building blocks: the low drop-out (LDO) voltage regulator, control block, and parallel connected controllable NMOS devices (Fig.2). The LDO voltage regulator consists of an operational amplifier with negative feedback, charge pump [7-9], pass device and resistive divider (Fig.1,a). The parameters of devices for proposed voltage regulator are presented in Table 1.

Fig.2. Proposed voltage regulator

Table 1

Parameters of voltage regulator devices

Device Nf L, u Vh, mV R, П

Pass device 40 20 0.15 470 -

Controllable pass elements 2 20 0.15 470 -

Switches 2 8 0.15 495 -

R1, R2, Rload - - - - 6000

Charge pump multiplies supply voltage by 1.45 ratio to maintain higher supply for operational amplifier (Fig.3) [9]. It is implemented by summing the high and low voltage supplies. The invertors, driving O and O signals are supplied from low voltage, which nominal value is 0.9 [V]. The Mn1 and Mn2 transistors are supplied from higher supply, which nominal value is 2.0 [V], hence the voltage on Cst capacitor will be 2.9 [V], for Vdd 10% case it would be 2.6 [V]. The maintained voltage is used to supply the output stage of operational amplifier; hence the gate voltage of pass-device could reach up to 2.5 [V], considering the saturation margin of operational amplifier output stage PMOS transistor. The parameters of charge pump devices are presented in Table 2.

Vck!h

0 O

Fig.3. Charge pump circuit

Table 2

Parameters of charge pump devices

Device Nf Nfin L, u Vth, mV C, fF

Mn 1, Mn2 4 8 0.15 470 -

Mp1, Mp2 6 8 0.15 495 -

С С Cch-! Cst - - - - 93.28

The reference voltage of LDO is multiplied by the ratio of resistive divider and applied to a pass device, which could be an N-FET or P-FET. The pass device operates in the saturation region to maintain the desired output voltage. The operational amplifier senses the output voltage of the regulator, which drives the pass device's gate to the appropriate voltage to ensure the correct output. The operational amplifier changes the gate-source voltage of the pass device, in case of variations of load current or reference voltage [10, 11]. The all reference voltages are provided by band-gap reference, which ensures maximum 10 [mV] variation.

The parallel connected controllable NMOS devices used to adjust pass device drive strength. Each NMOS device has serial connected PMOS transistor which acts like a switch. Control block regulates the switches. In Fig.4 the architecture of control block is presented. It consists of two comparators, digital logic part and bidirectional shift register.

Fig.4. Control block

There are three possible operation modes for bidirectional shift register that are determined by the digital logic. NAND, AND, XNOR gates are used in digital logic part. In Table 3 possible operation modes of control block are presented. Vg serves as an input for both comparators. Control block monitors gate voltage of pass-device to maintain appropriate operating region for it, as in case of changes in load current the gate voltage will be changed as well by negative feedback loop. For extensively large load currents Vg could reach to supply voltage and current supplied by voltage regulator will be limited (Fig.5). To eliminate this scenario control block enables additional parallel devices, hence lowering Vg voltage.

Table 3

Possible input configurations for digital logic part

O1 O2 Mode en Operation

0 0 1 1 Add 0 from in1

0 1 1 0 -

1 0 1 0 No changes

1 1 0 1 Add 1 from in2

Fig.5. Gate voltage dependence of pass device from load current

Comparators are used to determine range of Vg gate voltage of pass device. Outputs of comparators are inputs for digital logic part. When O1 = 0 and O2 = 0, shift register is enabled and mode = 1, which means shift register shifts right. In this case logical «0» is inserted from in1, hence additional unit of pass device is added, and Vg value is decreased. When O1 = 1 and O2 = 1, shift register is enabled and mode = 0, which means shift register shifts left. In this case logical «1» is inserted from in 2, hence one of the units of pass device is disabled and Vg value is increased. When O1 = 1

and O2 = 0 the bidirectional register is in static state. The O1 = 0 and O2 = 1 case could never be met, as vref1 is always greater than vref2.

Simulation results: Simulations have been performed using circuit level simulator HSpice [12]. The existed [4,5] and proposed voltage regulators have been implemented in 14 nm SAED FinFet technology [13] for proper comparison to eliminate process dependent differences. Nominal value for supply voltage is 2 V and for worst case it is 10 % less and equals to 1.8 V. The worst results are observed in SF process, high temperature and low supply voltage. Simulation results for worst case of PSRR for the proposed and existed voltage regulators with maximum and half load currents are presented in Fig.6 and Fig.7. With the maximum load current all parallel units of proposed voltage regulator are enabled and PSRR is almost the same compared with existed versions, while for lower currents pass element size is decreased and PSRR is improved from 17.53 dB to 22.1 dB for voltage regulator with PMOS pass device and from 18.4 dB to 23.6 dB for voltage regulator with NMOS pass device.

The performance comparison of proposed method for worst case with previously reported LDO regulators, while the load current is decreased by two times is presented in Table 4.

The highest value of PSRR is noticed in SF process, low temperature and high supply voltage. Simulation results considering process, voltage, temperature (PVT) variations are presented in Table 5 and Table 6.

1.0k 10.0k 100.0k 1meg 10meg

f Hz

Fig.6. Comparison of PSRR results for 15 mA load current

1.0k 10.0k 100.0k 1meg 10meg 100meg 1g 10g

f Hz

Fig. 7. Comparison of PSRR results for 7,5 mA load current

Table 4

Comparison with available method s Vdd = 2.0 [V]

Parameter Proposed voltage regulator with PMOS pass device Existed voltage regulator with PMOS pass device [5] Proposed voltage regulator with NMOS pass device Existed voltage regulator with NMOS pass device [4]

Technology [nm] 14 14 14 14

Supply voltage, 0.9Vdd, V 1.8 1.8 1.8 1.8

Output voltage, V 1.55 1.55 1.7 1.7

Max load current, mA 15 15 15 15

Max rejection, dB 88.14 87.7 84.1 82.7

Min rejection, dB 22.1 17.53 23.6 18.4

Area, um2 2470 1840 3222 2592

Table 5

PVT simulation results for NMOS pass device

Parameter TT, 25°C, Vnominal SS,-40°C, Vlow FF, 125°C, Vhigh SF,125°C, Vlow FS, -40°C, Vhigh

Max PSRR, dB 90.6 86.3 94.7 84.1 98.3

Min PSRR, dB 26.2 24.9 27.1 23.6 29.2

Table 6

PVT simulation results for PMOS pass device

Parameter TT, 25°C, Vnominal SS, -40°C, Vlow FF, 125°C, Vhigh FS, 125°C, Vlow SF,-40°C, Vhigh

Max PSRR, dB 95.3 89.9 97.6 88.14 98.1

Min PSRR, dB 25.7 24.1 25.8 22.1 26.3

Conclusion. Voltage regulator is presented, which controls the pass device size to enhance PSRR. For that purpose, the control block is added which consists of comparators, bidirectional shift register and logic gates. The control block monitors the gate voltage of pass device and enables or disables additional units if gate voltage exits from its operational region. The minimum PSRR is improved from 17,53 dB to 22,1 dB for voltage regulator with PMOS pass device and from 18,4 dB to 23,6 dB for voltage regulator with NMOS pass device when load current is decreased two times. The area of LDO voltage regulator is increased by 24 % due to added control block.

References

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11. Horowitz P., Hill W. The Art of Electronics. Second Edition. Cambridge University Press, 1989. 700 p.

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Received 10.01.2019; Revised 18.02.2019; Accepted 19.03.2019.

Information about the authors:

Vazgen Sh. Melikyan - Corresponding Member of NAS RA, Dr. Sci. (Eng.), Prof., Director of Educational Department of «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), vazgenm@synopsys.com

Andranik K. Hayrapetyan - PhD student of Yerevan State University (Armenia, 0025, Yerevan, Alex Manoogian, 1), Analog and Mixed Signal Circuit Design Engineer, Sr. I OOO «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), and@synopsys.com

Hakob T. Kostanyan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. I OOO «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), hakobk@synopsys.com

Hayk V. Margaryan - student of Yerevan State University (Armenia, 0025, Yerevan, Alex Manoogian, 1), Analog and Mixed Signal Circuit Design Engineer, Engr. I OOO «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), hmargar@synopsys.com

Hayk T. Grigoryan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. I OOO «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), hgrigo@synopsys.com

Armen A. Martirosyan - PhD student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Sr. I OOO «Synposys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), armenma@synopsys.com

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