ASIC implementation of high-speed vector magnitude & arctangent approximator Текст научной статьи по специальности «Компьютерные и информационные науки»

Circuits and Systems for Receiving, Transmitting and Signal Processing

Устройства и системы передачи, приёма и обработки сигналов

Research article

DOI: https://doi.org/10.18721/JCSTCS.14401 UDC 621.3.049.774

ASIC IMPLEMENTATION OF HIGH-SPEED VECTOR MAGNITUDE & ARCTANGENT APPROXIMATOR

Ara Abdulsatar Assim12 e

1 Salahaddin University, Erbil, Iraq; 2 Peter the Great St. Petersburg Polytechnic University, St. Petersburg, Russian Federation

H araabdulsattar@gmail.com

Abstract. The quadrature processing techniques used in spectral analysis, computer graphics, and digital communications constantly demand high-speed calculation of the magnitude of a complex number (vector V) given its real and imaginary parts. The aim of this work is designing a digital signal processor (DSP processor) for approximating magnitude and arctangent (phase) of vectors (and/or complex numbers). This work can be divided into three main stages. Firstly, a mathematical model is designed in Simulink, then using that model. Secondly, Verilog description code is generated. The code is used to perform logic synthesis (converting the description code into logic gates) using XT018 technology (180 nm BCD-on-SOI) from X-FAB. Lastly, an ASIC (Application Specific Integrated Circuit) is created from the logic gates. The inputs and outputs of the device are fixed-point numbers, their length is equal to 16 bits and the fraction length is 8 bits. The proposed system can calculate magnitude and phase with an error of less than 1 and 0.35 % respectively.

Keywords: alpha max plus beta min algorithm, arctangent approximation, fast magnitude approximation, digital signal processing, DSP processor

Citation: Assim A.A. ASIC implementation of high-speed vector magnitude & arctangent approximator. Computing, Telecommunications and Control, 2021, Vol. 14, No. 4, Pp. 7—14. DOI: 10.18721/JCSTCS.14401

This is an open access article under the CC BY-NC 4.0 license (https://creativecommons.org/ licenses/by-nc/4.0/).

© Assim A.A., 2021. Published by Peter the Great St. Petersburg Polytechnic University

Научная статья

DOI: https://doi.org/10.18721/JCSTCS.14401 УДК 621.3.049.774

РЕАЛИЗАЦИЯ ИНТЕГРАЛЬНОЙ СХЕМЫ СПЕЦИАЛЬНОГО НАЗНАЧЕНИЯ ВЫСОКОСКОРОСТНОГО АППРОКСИМАТОРА ДЛЯ ВЕЛИЧИНЫ И АРКТАНГЕНСА ВЕКТОРОВ

А.А. Ассим12 и

1 Университет им. Салахаддина, Эрбиль, Ирак; 2 Санкт-Петербургский политехнический университет Петра Великого,

Санкт-Петербург, Российская Федерация

и araabdulsattar@gmail.com

Аннотация. Методы квадратурной обработки, используемые в спектральном анализе, компьютерной графике и цифровой связи, постоянно требуют высокоскоростного вычисления величины комплексного числа (вектора V) с учетом его действительной и мнимой частей. Рассмотрен цифровой сигнальный процессор (DSP) для аппроксимации величины и арктангенса (фазы) векторов (и / или комплексных чисел). Работу можно разделить на три основных этапа. Сначала в Simulink создаётся математическая модель, затем с её помощью формируется код описания Verilog, используемый для выполнения логического синтеза (преобразования кода описания в логические элементы) с применением полупроводниковой технологии XT018 (180 нм BCD-on-SOI) от X-FAB. Наконец, из логических вентилей создаётся ASIC (специализированная интегральная схема). Входы и выходы устройства представляют собой числа с фиксированной точкой, их длина равна 16 битам, а дробная длина — 8 бит. Предлагаемая система может рассчитывать амплитуду и фазу с погрешностью менее 1 и 0,35 % соответственно.

Ключевые слова: алгоритм альфа макс плюс бета мин, приближение арктангенса, быстрое приближение величины, цифровая обработка сигналов, цифровой сигнальный процессор, ЦСП

Для цитирования: Assim A.A. ASIC implementation of high-speed vector magnitude & arctangent approximator // Computing, Telecommunications and Control. 2021. Т. 14, № 4. С. 7-14. DOI: 10.18721/JCSTCS.14401

&атья открытого доступа, распространяемая по лицензии CC BY-NC 4.0 (https://creative-commons.org/licenses/by-nc/4.0/).

Introduction

Calculating magnitude and phase of vectors or complex numbers is useful in many areas, including, but not limited to, AM demodulation, signal processing and image processing systems [1—9]. There is more than one method for that purpose, but choosing the optimal method depends on the required precision, hardware and software capabilities. For instance, calculating magnitude of a vector requires taking square root of the squared sum of the real and imaginary components [14], as in equation:

Magnitude = yj x2 + y2, (1)

while determining the phase requires solving arctan function [1, 4, 7], as given in

9 = tan-1 y. (2)

x

© Ассим А.А., 2021. Издатель: Санкт-Петербургский политехнический университет Петра Великого

Fig. 1. Block diagram of the high speed magnitude approximator

Both operations require a lot of arithmetic computations with floating-point numbers. That is why approximation algorithms are introduced: they finish the same task much faster, and require less hardware and software resources [1, 5, 13—15]. In this paper, Alpha max plus beta min algorithm is used for fast magnitude approximation [10—15]. This algorithm can be defined by this formula [1, 3, 4]:

Apprx. magnitude ~ a.max + p.min, (3)

where max, min are the unsigned maximum and minimum values of the vector components respectively, a and P are constant values. The block diagram of this system is provided in Fig. 1.

The choice of a and P values depends on the desired precision as provided in Table 1. In this work, the last values are used, because they produce the most accurate results (maximum error is 1.0 %). The implemented arctan approximation equations used in this work are provided in Table 2. The proposed method mentioned here is quite efficient and convenient: it uses neither look-up tables nor very high-order polynomials. The only issue is that all the equations in Table 2 require division. Due to the fact that division is not a synthesizable operation in Verilog, it is not allowed to use a divider block in the mathematical model; instead, the division function (1/x) is approximated using Taylor series expansion with center 1, as provided in the following equation:

1 2 3

Taylor series of — with center 1«1 -(x -1) + ( x -1) -(x -1) +.... (4)

x

Table 1

Choice of alpha and beta values and corresponding error rates

a в Maximum error, %

1 0.5 11.8

1 0.25 11.6

1 0.375 6.8

0.9375 0.46875 6.3

0.9486 0.39293 5.1

1 0.4 7.7

a = 1 if min < 0.375 max a = 0.84375 if min > 0.375 max P = 0.125 if min < 0.375 max в = 1.1875 if min > 0.375 max 1.8

a = 0.99 if min < 0.4142135 max a = 0.84 if min > 4142135 max в = 0.197 if min < 0.4142135 max в = 0.561 if min > 4142135 max 1.0

Table 2

Used equations for approximating arctangent function

Octant Arctan approximation formula

1st or 8th 0- IQ 12 + 0.28125Q 2

2nd or 3rd 0 = n- 2 IQ 2 2 Q2 + 0.2812512

4th or 5th 0 - sign ( Q ) .n + --^-- 12 + 0.28125Q2

6th or 7th 0 = -n- IIQ 2 12 + 0.28125Q2

Implementation of the fast magnitude approximator

The fast magnitude approximator system is given in Fig. 2, it is based on a max plus P min algorithm [4]. An ideal (reference) model is needed to justify the validity of the proposed model. There is a special block in Simulink for that application, namely (Complex to Magnitude-Angle), but it is not synthesizable in practice.

An input signal is applied to the designed system in Fig. 2 for checking the performance of the mathematical model. The signal consists of the summation of three sinusoidal signals with different magnitudes and frequencies, as depicted in Fig. 3a. This input generates an output that is provided in Fig. 3b. We can see the difference between the ideal magnitude and the approximated magnitude is very little. Thus, we can conclude that the system's performance is valid.

Fig. 2. Block diagram of the fast magnitude approximator (in Simulink)

Fig. 3. The applied input signal (a) and output signal (b)

Implementation of the arctangent (phase) approximator

The structure of the arctangent function approximator system is provided in Fig. 4. The last block is a 4-to-1 multiplexer, because there are four different formulas for approximating arctangent function based on the octants (provided in Table 2). Based on the control signal's value, the multiplexer connects the output to one of its four inputs.

A comparison between the ideal arctangent signal and the output signal of the arctangent approximator system is shown in Fig. 5a, and the difference between the ideal and approximated arctangent function is shown in Fig. 5b, the maximum error is 0.0035.

Fig. 4. Block diagram of the arctangent (phase) approximator (in Simulink)

a)

b)

Ideal phase Arctangent Approximation

10 15 20

Time, sec

25 30

Difference of Bueliie from Lower Tolerance

---Difference of Baseline from Upper Tolerance

-Difference

K10-'

1D 15 20

Time, sec

Fig. 5. Ideal vs. approximated arctangent function (a) and tolerance (error) signal (b)

Realization of the Application Specific Integrated Circuit (ASIC)

Before the realization of the ASIC, the entire blocks in the system must be converted into fixed-point numbers, so that later, the system can be defined in Verilog. The process is done by using the built-in tool in Simulink, known as fixed-point tool. Once all the blocks' date types are converted to a fixed-point, it can be used to generate the Verilog code by means of HDL coder, a MATLAB tool generating a Verilog description of the mathematical model. In addition to that, this tool transforms the input and output signal to an array of hexadecimal numbers. This later can be used as a reference to verify that the netlist functions correctly. The Verilog description code is used to create a netlist of the device (synthesis). In this work, Cadence Encounter RTL Compiler was used to synthesize the code. The netlist is shown in Fig. 6a. The same tool (Cadence Encounter) was used to create the layout from the netlist in Fig. 6b. (list of logical gates and interconnects obtained after logical synthesis) with reference to the technological library: the position of the input and output pins and the constraint file. The process of layout generation is automated, but there are many specifications that need to be carefully specified in the tools. The chosen clock frequency

is 10 MHz with an uncertainty of 0.05. The layout of the device is provided in Fig. 6b. Its dimensions are (701.565 ^m x 693.335 ^m), it requires an area of 486419.56 ^m2.

Conclusion

In conclusion, this research paper covers the entire process of the development of a digital device, from writing a Verilog code (system level) to creating a layout of the device (physical level). A system for approximating vector magnitude and arctangent using the FPGA was developed. All the main stages of development were passed: description of a digital device in Verilog HDL language, logical synthesis of a device in Cadence RTL Compiler, layout generation in Cadence Encounter. In addition to that, functional verification was carried out in Cadence Incisive at all the three stages: behavioral level, synthesis and layout generation. The timing diagram results confirm the correct operation of the device, and during the stage of layout generation, different verifications were carried out (time analyses for post-Route and SignOff stages for both cases of setup and hold). Verifications for DRC, connectivity and geometry were performed as well, all of them showing no violations. After its generation, the layout was imported to Cadence Virtuoso undergoing two checks, namely DRC and LVS, which it passed successfully. Therefore, we may conclude that the layout was generated correctly. The source codes are uploaded to GitHub, the link is provided in Appendix, in case someone is interested in repeating the same work.

Appendix

The Verilog codes can be found in this repository: https://github.com/AraAssim/AraAssim-Vec-tor-magnitude-and-arctangent-approximation

Acknowledgment

I would like to express my deep gratitude to my parents for their boundless encouragement and love. I also thank my dearest friend (Nikolai Kirichenko) for helping me during my stay in Russia. Finally, I want to extend my thanks to the editors of this journal for taking time to review my work.

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THE AUTHOR / СВЕДЕНИЯ ОБ АВТОРЕ

Assim Ara Abdulsatar Ассим Ара Абдулсатар

E-mail: araabdulsattar@gmail.com

The article was submitted 01.09.2021; approved after reviewing 02.12.2021; accepted for publication 22.12.2021.

Статья поступила в редакцию 01.09.2021; одобрена после рецензирования 02.12.2021; принята к публикации 22.12.2021.