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10СХЕМОТЕХНИКА И ПРОЕКТИРОВАНИЕ CIRCUIT ENGINEERING AND DESIGN
УДК 621.382.049.771:621.394.6:53.089.62 DOI: 10.24151/1561-5405-2019-24-5-503-510
Crystal Area Reduction Method for Impedance Matching Systems in High-Speed Data Links
* 1 * 12 12 V.Sh. Melikyan , K.T. Khachikyan ' , H.V. Gumroyan ' , 12 12 2 A.V. Babayan ' , S.A.Avushyan , K.T. Hakobyan
1«Synopsys Armenia» CJSC, Yerevan, Armenia National Polytechnic University of Armenia, Yerevan, Armenia
Abstract. The well known solution of the signal reflection is the transmission line matching method usage, where the resistance calibration problem comes forward. The transmission line matching occurs in I/O circuits, the number of which per IC can be more than 40, therefore, the area reduction of those is critical. In existing transmission line matching systems the multiple functional nodes, such as the current source, multiplexer, comparator, etc., have been used. Replacing those by other functional nodes can result in a significant area reduction, but can affect the resistance calibration accuracy. In the work the method for calibration of resistances, where the input signal feeds through a voltage follower, which output is connected to the «decision-making system», determining whether the controlled resistance value should be increased or decreased, has been proposed. Usage of the given method 1.6 times reduces the occupied area, with the resistance calibration accuracy reduction of 1%.
Keywords: integrated circuit; transmitter; receiver; transmission line; reflections; impedance matching
For citation: Melikyan V.Sh., Khachikyan K.T., Gumroyan H.V., Babayan A.V., Avushyan S.A., Hakobyan K.T. Crystal area reduction method for impedance matching systems in high-speed data links. Proc. Univ. Electronics, 2019, vol. 24, no. 5, pp. 503-510. DOI: 10.24151/1561-5405-2019-24-5-503-510
© V.Sh. Melikyan, K.T. Khachikyan, H.V. Gumroyan, A.V. Babayan, S.A. Avushyan, K.T. Hakobyan, 2019
Метод уменьшения площади кристалла для систем согласования импедансов в высокоскоростных каналах передач
1 12 12 В.Ш. Меликян , К.Т. Хачикян ' , Р.В. Гумроян ' ,
А.В. Бабаян1'2, С.А. Авушян1'2, К.Т. Акопян2
1ЗАО «Синопсис Армения», г. Ереван, Армения
2Национальный политехнический университет Армении, г. Ереван, Армения vazgenm@synopsys.com
В узлах ввода-вывода данные передаются из передатчика к приемнику через каналы (линии) передач, в которых происходит отражение передаваемого сигнала. В свою очередь, быстрое уменьшение размеров транзисторов современных ИС делает системы, основанные на КМОП-технологии, более чувствительными к отклонениям напряжения, температуры и технологического процесса. Все перечисленное увеличивает чувствительность систем ввода-вывода к отражениям сигнала. Известное решение проблем отражения - метод согласования линии передач, при использовании которого возникает проблема калибровки сопротивлений. Согласование линий передач происходит в системах ввода-вывода, количество которых в одной ИС может быть более 40. Таким образом, уменьшение занимаемой площади в подобных схемах является критическим. В существующих системах согласования линий передач используется множество функциональных узлов, таких как источник тока, мультиплексор, компаратор и т.д., замена которых может привести к уменьшению занимаемой площади, а также к потере точности калибровки. В работе предлагается метод калибровки сопротивлений, когда входной сигнал проходит через повторитель напряжения, подключенный к «системе принятия решений», которая «решает», должно ли «контролируемое сопротивление» увеличиться или уменьшиться. Данный метод предоставляет возможность сократить занимаемую системой калибровки площадь в 1,6 раза, при этом точность калибровки уменьшается на 1%.
Ключевые слова: интегральная микросхема; передатчик; приемник; линия передач; отражения; согласование импедансов
Для цитирования: Метод уменьшения площади кристалла для систем согласования импедансов в высокоскоростных каналах передач / В.Ш. Меликян, К.Т. Хачикян, Р.В. Гумроян и др. // Изв. вузов. Электроника. - 2019. - Т. 24. -№ 5. - С. 503-510. DOI: 10.24151/1561-5405-2019-24-5-503-510
Introduction: CMOS technology continuous shrinking has immense influence on modern integrated circuits (IC). It makes ICs more sensitive to devices mismatches and postlayout effects, which makes the system more unstable and less accurate [1]. On the other hand, fabrication process of ICs becomes more arduous and has enormous impact on IC components quality. PVT variations have significant impact on system accuracy, as well. Due to PVT variations devices' parameters can deviate from their nominal values. Moreover, transmission lines are very important in high speed systems and interfaces as they significantly affect signal timing and shape [2]. Channels are one of the main factors limiting the operating
frequency of high-speed devices since they can act as low-pass filters and induce signal reflections (fig. 1) [3].
Proper Signal termination at the end of line is required to reduce voltage reflections. The latter can lead to a loss of a data information and impair timing margins. As a result, the system can fail to function under some operating conditions such as over-voltages or high temperature. The reflected voltage value at the end of the channel depends on termination resistance and transmission line impedances matching. Each end of transmission line has its own reflection coefficient p. However, even a correctly terminated line is limiting the signal bandwidth damping its high-speed harmonics, which manifests itself in reduced slew rates and decreased eye opening as a result [4].
The amount of reflected signal (Vreflected), which is a portion of the transmitted signal (Vtransmitted), will be determined with the proportion of transmission line impedance (Z0) and
source's impedance (Zt) (fig.2).
--------------
/ \
^ transmitted -
Transmission line )-
Zr
^Transmitter /
Fig.2. Transmission line model
The equation below represents the method of determining the amount of reflections of the transmitted signal [5], where p is reflection coefficient, Vt is transmitted and Vr is reflected voltages, Zt is transmitter output impedance and Zr is the transmission line impedance
V Z + z.
The equation proves, that reflections can be avoided if transmitter output and line impedances are matched, otherwise transmitted signal can be reflected and therefore be distorted.
For high-speed signals analysis data-eye methodology is common [6]. The eye-diagram shows all the data collected and concentrated in one period of signal. The vertical axis stands for data amplitude and the horizontal for data period.
Aforementioned phenomena reduce eye-diagram opening of the received signal in both directions (fig.3), which makes data loss unavoidable.
Transn lisson ine
Inpi it signa
Trati (1 srmsso i line ,nal
Л
iignal iistortii ins due
; i to lm 5 rcflcc ions
i
i I i
r i 1 1 1
I 1 1 1 / « 1 \
\ \! v /
V V
2 4 6
Time
Fig.1. Signal distortion due to transmission line negative effects
Time, ns
Fig.3. Signal's eye-diagram distortion due to transmission lines reflections
Current source
Multiplexer
Logic cell
Controllec resistor
, External -resistor
О о
3
■с
й а
О
Impedance matching existing methodology architecture is based on comparison with an external resistance. An external resistance has high precision and its value is independent from process variations, temperature, and supply voltage changes. In modern ICs, the external resistnace value precision is close to 2 %. This implementation makes possible transmitter and receiver nodes impedance matching. Impedance matching system consists of the following blocks: current source, multiplexer, controlled resistor, comparator and a logic cell (fig.4) [7].
Current source allows to provide high output current. Output current flows through the multiplexer to the external and then to the controlled resistances. The current drops on the external and controlled resistor and forms comparator input voltages. Afterwards, the result of comparison is being provided to the logic cell, which generates the control signals of the parallel resistors. Described sequence repeats until the voltages formed on the resistors are equal, which means that the resistances are equal too, since the current is the same for both.
Mentioned architecture provides high accuracy but occupies large area.
Proposed impedance matching system architecture: Proposed impedance matching method is based on the exteranal and high accurate resistance although it uses mixed-signal nodes (voltage follower, ADC, etc.) therefore it occupies small area (fig. 5). The proposed architecture's main blocks are an amplifiers operating as input voltage follower, analog to digital converter (ADC), RTL logic block and controlled resitor array. To gain linearity and minimize PVT sensitivity in each leg additional resistors were inserted [8]. ADC and RTL logic blocks are responsible for deciding whether to increase or decrease the number of controlled resistors in the array. The controlled resistor reaches its target value when the mid-point voltage (Vref) of the resistors becomes equal to a voltage on a VP_half pin.
Fig.4. Impedance matching system block diagram
Fig.5. Proposed Impedance matching system
ADC code
start
Control
J
Current ADC code
T
sel <n:0>
Ref code
Digital comparator
Input voltage follower contains two stages, the first one is an operational amplifier, and the second one is common source amplifier. A negative feedback loop brings voltage difference on the voltage follower inputs to a zero. ADC converts the analog output of the voltage follower to a digital code.
Digital code proceeds to the «RTL Logic» block, which calculates the difference between VP_half and Vref voltage values. RTL block diagram is presented (fig.6). In RTL block digital comparator compares «current ADC code» with the «Ref code». RTL block changes «sel» value, until the «Ref code» value and «Current ADC code» are not equal. Since the comparator is digital after the synthesis it will occupy small area.
During operation the voltage follower's output will be simultaneously changed, until the input voltages become equal. The RTL block generates binary code, which is further
being applied to the controlled resistor. The calibration process finishes, when the input voltages of the voltage follower are equal, and since the half of the source voltage is being applied to the voltage follower positive input, then the same voltage is being formed on external and controlled resistors as well. This is possible only when external and controlled resistors are equal.
Simulation results: Simulations have been performed using Synopsys circuit level simulator HSPICE [9] for 27 PVT corners, including SS (slow-slow), TT (typical-typical), FF (fast-fast), SF (slow-fast), FS (fast-slow) with supply voltage ±10 % and temperature from -40 oC to 125 oC variations using 28 nm CMOS technology node. During the simulations 50 Ohm external resistor was selected. For occupied area evaluation physical design for both methods was done [10].
Fig. 6. RTL block diagram
Simulation results are presented in table.
Resistors values comparison
Parameter Existing Method Proposed Method
min typ max min typ max
Resistance (Ohm) 48.53 50.03 51.43 48.62 49.95 52.04
Area (um2) 1540 960
Table shows that the resistance value deviates from 48,62 to 52,04. That means, matching accuracy has dropped approximately for 1 % compared to the existing method, on the other hand proposed impedance matching method optimizes occupied area to 1.6 times.
Physical designs of current source, multiplexers and comparator of the existing method are presented below (fig. 7).
Current Source Multiplexers
Fig. 7. Layout view of additional blocks used in existing method
In the proposed architecture «Decision» making area (ADC and RTL logic) is comparative to the existing method Logic Cell area and occupies 7 % - 9 % of the entire system, therefore during system area calculation it can be ignored.
Compared to the existing method architecture, in the proposed method there is no current source, multiplexer, and comparator, but there is an additional input voltage follower. The area of the excluded nodes is approximately 1400 |im , while the area of the included nodes is approximately 860 |im2 (fig. 8).
The proposed system architecture occupied area is 1.6 times less than the existing methods causing 1% accuracy degradation.
Voltage follower
Fig.8. Layout view of added Voltage Follower
Conclusion: An impedance matching method implemented in 28nm CMOS technology node, is presented. The impedance matching proposed method improves occupied area for 1.6 times compared to the existing common calibration method. Proposed method occupies 860 |im . 1 % calibration accuracy loss keeps the methodology applicable for different highspeed data transfer protocols.
The most challenging part of proposed method implementation is the physical design, since it contains both, digital (RTL Logic) and analog (Voltage Follower, Current source, etc.) blocks. In physical design perspective, all analog blocks should be properly designed to keep the system accuracy at the desired level.
This method can be used for sensitive systems to compensate transmission line adverse influence on system performance.
References
1. Monica Zolog, Dan Pitic. Analysis of the effect of nonlinear input/output characteristics of digital integrated circuits on signal integrity. IEEE 31stInternational Spring Seminar on Electronics Technology. Budapest, 2008, pp. 604-609.
2. Samuel P. High-speed serial I/O design for channel-limited and power-constrained systems. Texas A&M University, 2010, pp. 57.
3. Nitsch J., Rambousky R., Tkachenko S. Introduction of reflection and transmission coefficients for nonuniform radiating transmission. IEEE Transactions on Electromagnetic Compatibility, 2015, pp. 1703-1713.
4. Haibo He, Shijie Cheng, Youbing Zhang, Nguimbis J. Analysis of reflection of signal transmitted in low-voltage powerline with complex wavelet. IEEE Transactions on Power Delivery, 2004, pp. 86-91.
5. Johnson H., Graham M. High-speed digital design: A handbook of black magic. Prentice Hall. Second Edition, 2003, pp. 31-48.
6. Jeonghyeon Ch., Eakhwan S., Jongjoo Sh. A precise analytical eye-diagram estimation method for nonideal high-speed channels. IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS), 2009, pp. 159-162.
7. Melikyan V., Balabanyan A., Hayrapetyan A., Melikyan N. Receiver/transmitter input/output termination resistance calibration method. IEEE XXXIII International Scientific Conference Electronics and Nanotech-nology (ELNANO). Kiev, 2013, pp. 126-130.
8. Esch G., Chen T. Design of CMOS IO drivers with less sensitivity to process, voltage, and temperature variations. IEEE International Workshop on Electronic Design, Test and Applications. Perth, 2004, pp. 312-317.
9. Hspice Reference Manual. Synopsys Inc., 2017, pp. 375-381.
10. Baker R.J. CMOS circuit design, layout, and simulation. Second Edition, 2008, 1045 p.
Received 05.04.2019; Revised 05.04.2019; Accepted 18.06.2019. Information about the authors:
Vazgen Sh. Melikyan - Corresponding Member of NAS RA, Dr. Sci. (Eng.), Prof., Director of the Educational Department of «Synopsys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), vazgenm@synopsys.com
Karen T. Khachikyan - PhD Student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Engr. II OOO «Synopsys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), karenkh@synopsys.com
Hrachya V. Gumroyan - Masters Student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Applications Engineer, Engr. I OOO «Synopsys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), gumroyan@synopsys.com
Armen V. Babayan - Student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), ASIC Digital Design Engineer, Engr. I OOO «Synopsys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), ababaya@synopsys.com
Suren A. Avushyan - Masters Student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Layout Design Engineer, Engr. I OOO «Synopsys Armenia» CJSC (Armenia, 0026, Yerevan, Arshkunyats st., 41), avushyan@synopsys.com
Kimik T. Hakobyan - Masters Student of National Polytechnic University of Armenia (Armenia, 0026, Yerevan, Arshkunyats st., 41), kim.hakobyan@polytechnic.am
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