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Circuits and Systems for Receiving, Transmitting, and Signal Processing
DOI: 10.18721/JCSTCS.13305 УДК 621.3.049.77
MODELING THE IMPACT OF TECHNOLOGICAL PROCESS VARIATIONS ON R-2R DAC STATIC CHARACTERISTICS
E.A. Salonina', Ya.V. Belyaev2, I.M. Piatak'
1 Peter the Great St. Petersburg Polytechnic University, St. Petersburg, Russian Federation;
2 Concern CSRI Elektropribor, JSC, St. Petersburg, Russian Federation
Digital-to-analog converter (DAC) is widely used in modern integrated electronics, converting digital signals into analog ones. This paper considers an R-2R structure DAC, its operation principle and static characteristics: integral non-linearity (INL) and differential non-linearity (DNL). For the accuracy of this DAC conversion, it is important that the element resistance ratio is maintained for the entire circuit. The authors considered the influence of random and systematic errors of DAC elements resistances on the transfer function and static characteristics of DAC, as well as the use of special DAC element placements to compensate for systematic errors. Systematic errors are presented as three types of gradients: linear, quadratic and central quadratic. These gradients were modeled in MATLAB. Using the MATLAB script, the authors calculated the static characteristics of the R-2R DAC for two resistor placements: regular and common centroid, taking into account the impact of three different gradients. These placements were compared based on the modeling and calculation results.
Keywords: digital-analog conversion, R-2R, linear gradient, quadratic gradient, resistor mismatch, MATLAB, common centroid.
Citation: Salonina E.A., Belyaev Ya.V., Piatak I.M. Modeling the impact of technological process variations on R-2R DAC static characteristics. Computing, Telecommunications and Control, 2020, Vol. 13, No. 3, Pp. 55-62. DOI: 10.18721/JCSTCS.13305
This is an open access article under the CC BY-NC 4.0 license (https://creativecommons.org/ licenses/by-nc/4.0/).
МОДЕЛИРОВАНИЕ ВОЗДЕЙСТВИЯ ТЕХНОЛОГИЧЕСКОГО РАЗБРОСА НОМИНАЛОВ ЭЛЕМЕНТОВ НА СТАТИЧЕСКИЕ ХАРАКТЕРИСТИКИ ЦАП ТИПА R-2R
Е.А. Салонина', Я.В. Беляев2, И.М. Пятак'
1 Санкт-Петербургский политехнический университет Петра Великого,
Санкт-Петербург, Российская Федерация;
2 ЦНИИ «ЭЛЕКТРОПРИБОР», Санкт-Петербург, Российская Федерация
ЦАП широко используются в современной интегральной электронике, осуществляя преобразование цифрового сигнала в аналоговый. В статье рассматривается ЦАП структуры R-2R, его принцип работы и статические характеристики: интегральная нелинейность (INL) и дифференциальная нелинейность (DNL). Для точности преобразования данного ЦАП важно, чтобы соотношение сопротивлений элементов сохранялось для всей схемы. Изучено влияние случайных и систематических погрешностей
номиналов резисторов на выходную и статические характеристики ЦАП, а также использование специальных расстановок элементов ЦАП для компенсации систематических погрешностей. Систематические ошибки представлены в виде трех типов градиентов: линейного, квадратичного и центрального квадратичного. Выполнено моделирование данных градиентов в MATLAB. С помощью скрипта MATLAB сделан расчет статических характеристик ЦАП R-2R с учетом воздействия трех различных градиентов при двух расстановках резисторов: «обычная» и «с общим центром». По результатам моделирования и расчета выполнено сравнение данных расстановок.
Ключевые слова: цифро-аналоговый преобразователь, R-2R, линейный градиент, квадратичный градиент, MATLAB, расстановка с общим центром.
Ссылка при цитировании: Салонина Е.А., Беляев Я.В., Пятак И.М. Моделирование воздействия технологического разброса номиналов элементов на статические характеристики ЦАП типа R-2R // Computing, Telecommunications and Control. 2020. Vol. 13. No. 3. Pp. 55-62. DOI: 10.18721/JCSTCS.13305
Статья открытого доступа, распространяемая по лицензии CC BY-NC 4.0 (https://creative-commons.org/licenses/by-nc/4.0/).
Introduction
Digital-to-analog converters (DAC) are widely used in modern complex mixed-signal integrated circuits, performing a conversion of a digital signal into an analog one. There are various types of DACs, which convert input signals with different resolutions into the output analog voltage or current. All digital-to-analog converters can be divided into the two main groups: serial and parallel DACs [1].
A DAC based on resistive matrix R-2R belongs to the parallel DACs of the binary architecture, since the output signal is formed by summing the voltages from the switched weighting elements [2]. In general, the weighting elements are resistances and, according to the weighting method, they are formed as a resistive ladder [1]. The schematic of an ideal 8-bit R-2R DAC is shown in Fig. 1.
As a rule, DAC converts an input signal from the digital binary code to the output continuous voltage. The output analog signal formed as a sum of the voltages at the DAC inputs is multiplied by the appropriate weighting coefficients. In the ideal case, when manufacturing DACs, there is no weight element ratio error, so the resistor ratios from the R-2R ladder are precisely matched and the DAC weights can be 2(—(N — i + :)), where "N" is the DAC resolution, "i" is the bit number [3]. In reality, there are always random and systematic errors due to imperfectly matched resistors from the R-2R ladder [4]. To minimize DAC conversion error, it is necessary to maintain a certain ratio between R and 2R resistances [5-6].
Random errors are the component (e.g. weighting components — resistors) errors that occur during chip production. They can be calculated within the normal distribution with the manufacturer's specified variation. Systematic errors are the errors caused by external factors affecting all weighting elements simultaneously and depending on the placement of each element on the chip [7].
Vont
Fig. 1. Schematic of an ideal R-2R DAC based on a resistive ladder
E.A. Salonina, Ya.V. Belyaev, I.M. Piatak, DOI: 10.18721/JCSTCS.13305
The problem of systematic errors
In this paper, we will consider systematic errors affecting R-2R resistances. To reduce random errors, geometric dimensions of the weighting components can be increased [8—10]. Therefore, random errors become insignificant and the impact of systematic errors increases. Thus, the impact of a systematic error typically prevails over that of a random error.
Under certain assumptions, systematic errors can be represented with some accuracy in the form of a linear or quadratic gradient [11—13] describing the deviation of the weight elements (resistances) placed on a chip. In order to solve the problem of the negative impact of these gradients, which leads to increased DAC integral and differential non-linearities, designers widely use gradient-compensated placement for the weighting elements where gradient is compensated and the matched resistance ratio for all elements is preserved [14].
On the one hand, the optimal placement of DAC array elements in terms of minimizing the area occupied on the chip and the absence of parasitic capacitances implies simplification of the connection and reduction of parasitic capacitances [1]. However, this placement can be susceptible to various systematic errors which have a negative impact on DAC characteristics [15].
Simulation by MATLAB script
In order to find a compromise between gradient compensation and connection simplification, it is necessary to evaluate DAC characteristics (in particular, integral and differential non-linearity) for the given placement of the weighting elements (resistors). The MATLAB script used in this paper can simulate horizontal and vertical gradients on the weighting elements placed on the chip. The script allows to model three types of the gradient: linear, quadratic and central quadratic (Fig. 2).
The script also calculates the actual weighting coefficients and the DAC transfer characteristic taking into account the non-idealities of the resistance values. The R-2R array element placement is formed as a number matrix with the element numeration strictly ordered as shown in Fig. 3. The proposed script is
a) b)
o a
Fig. 2. The gradient map simulation: a — linear; b — quadratic; c — central quadratic
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Computing, Telecommunications and Control
Vol. 13, No. 3, 2020
Fig. 3. R-2R weighting elements
suitable for any number of the weighting elements on a chip, as well as for any DAC resolution; the calculation of integral nonlinearity (INL) and differential nonlinearity (DNL) is also included in the MATLAB script.
Comparison of the various ways of placing R-2R array elements on a chip is studied and static DAC characteristics are evaluated (in particular, INL and DNL) for a given type of gradient and the placement of DAC weighting elements on the chip. The script produces the following graphs:
1. Transfer characteristic — relationship between the value of the output voltage Vout and the given DAC input code.
2. DNL — deviation of an output step from the ideal analog LSB value scaled to the value of conversion step (LSB).
3. INL — deviation of the actual transfer characteristic from the ideal transfer curve for each output level scaled to the value of conversion step (LSB) [16].
Comparison of two placements
In this paper, we consider two choices for the placement of the 8-bit DAC weighting elements: with a common center ("common-centroid") and without compensation for distortion ("regular"). The first one was designed to achieve full compensation of the linear gradient and the second one was chosen as the simplest in terms of connections and the area on the chip.
The "common centroid" placement is an example of a linear gradient compensation layout, but it occupies a large area on a chip and it is difficult to connect the elements with each other due to the significant distance between them and possible connection crossings [17]. The "regular" layout without gradient compensation was chosen as the smallest placement area with the simplest connection of elements. Script examples with these placements are shown in Fig. 4. Numbers from 0 to 16 in the matrix denote R-2R
a) Rmatrix -
[16 4 6 8 10 12 16 i b)
14 5 7 9 11 13 14 ;
15 4 6 8 10 12 -1 ; Rmatrix -
-12 3 2 16-1; [0 1 3 S 7 9 11 13 15 ;
-1 -1 -1 -1 -1 -1 -1 i -12 4 6 8 10 12 14 16
-10 1232-1; -1 2 4 6 S 10 12 14 16
-1 12 10 8 6 4 15 J 14 13 11 9 7 5 14 ;
16 12 10 8 6 4 16 :
Fig. 4. Code example of the weighting elements matrix: a — "common centroid" placement; b — "regular" placement
Fig. 5. INL plots for the central quadratic gradient simulation: a — "common centroid" placement; b — "regular" placement
matrix elements according to the numeration in Fig. 3, which includes the resistance of the given weighting element. The number "—1" denotes an empty cell.
Three types of gradients were simulated separately: linear, quadratic and central quadratic. The maximum gradients value was limited to 20 %. Each gradient was set on both axes. Taking the gradients into account, DAC output characteristics were calculated for two placements ("common centroid" and "regular"), as well as DNL and INL, scaled to the value of the minimum step of the transfer characteristic, which is LSB (least significant bit). The results of the modeling are given in Table 1.
Table 1
Simulation results
Gradient type Maximum value of DNL, LSB Maximum value of INL, LSB
"regular" layout "common centroid" layout "regular" layout "common centroid" layout
Linear -6.894 10-14 13.590 ~10-14
Quadratic -3.027 —0.901 6.234 2.174
Central quadratic 0.742 —3.553 0.910 8.191
For the linear gradient, the best placement was of the "common centroid" type. According to the modeling result, it allows INL of the order of 10-14 LSB, which is comparable to the accuracy of MATLAB calculations.
For the quadratic gradient, the "common centroid" placement is less suitable than for a linear gradient, as INL in this case reaches 2.174 LSB. This value is higher than acceptable (INL can be considered acceptable if not higher than ±1 LSB, acceptable DNL does not exceed ±0.5 LSB). However, compared to the "regular" placement, the "common centroid" placement result was better.
For the central quadratic gradient, the best placement was the "regular" one. It gives the maximum DNL = 0.742 LSB and INL = 0.910 LSB, while in the "common centroid" arrangement these values are —3.553 LSB and 8.191 LSB, respectively. INL plots for this gradient are shown in Fig. 5.
Conclusion
This paper considered the non-linearities in the R-2R DAC static characteristics caused by systematic errors of the weighting elements (resistances). A MATLAB script was developed to simulate these errors
in the form of matrix gradients and to calculate the static DAC characteristics taking into account these gradients for different weighting elements placement. INL and DNL were estimated for three types of gradients (linear, quadratic, central quadratic) and for two types of placements ("regular" and "common centroid"). The result shows that the "common centroid" placement is better for both linear and quadratic gradients. On the other hand, the "regular" placement is better for the central quadratic gradient. In addition, the MATLAB script written in the process of the research can be further used to model gradient impact on various R-2R DAC weighting element placements and DAC static characteristics.
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E.A. Salonina, Ya.V. Belyaev, I.M. Piatak, DOI: 10.18721/JCSTCS.13305
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16. Parmar S.S., Gharge A.P. R-2R ladder circuit design for 32-bit digital-to-analog converter (DAC) with noise analysis and performance parameters. Proceedings of the 2016 International Conference on Communication and Signal Processing, 2016, Pp. 467-468. DOI: 10.1109/ICCSP.2016.7754180
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Received 05.07.2020.
СПИСОК ЛИТЕРАТУРЫ
1. Кузнецов К.П. Исследование методик размещения взвешивающих элементов ЦАП с бинарной структурой // URL: https://elib.spbstu.ru/dl/3/2020/vr/vr20-4137.pdf. (Дата обращения: октябрь 2020). (rus)
2. Rabal A., Otin A., Urriza I., Gines A.J., Leger G., Rueda A. A compact R-2R DAC for BIST applications // Proc. of the 2016 IEEE 21st Internat. Mixed-Signal Testing Workshop (IMSTW 2016). 2016. DOI: 10.1109/IMS3TW.2016.7524224
3. Hirai M., Yamamoto S., Arai H., Kuwana A., Tanimoto H., Gendai Y., Kobayashi H. Systematic construction of resistor ladder network for N-ary DACs // Proc. of the 2019 IEEE 13th Internat. Conf. on ASIC. 2019. Pp. 1-4. DOI: 10.1109/ASICON47005.2019.8983583
4. Chen C., Lu N. Nonlinearity analysis of R-2R ladder-based current-steering digital to analog converter // Proc. of the 2013 IEEE Internat. Symp. on Circuits and Systems. 2013. Pp. 833-836. DOI: 10.1109/IS-CAS.2013.6571976
5. Xu W., Zhang R., Shi C. Research of segmented 8bit voltage-mode R-2R ladder DAC // Proc. of the 2015 IEEE 11th Internat. Conf. on ASIC. 2016. DOI: 10.1109/ASICON.2015.7517105
6. Lin Y., Geiger R. Resistors layout for enhancing yield of R-2R DACs // Proc. of the 2002 IEEE Internat. Symp. on Circuits and Systems. 2002. Pp. 97-100. DOI: 10.1109/ISCAS.2002.1010649
7. Yu T., Fang S., Chen C., Sun Y., Chen P. Device array layout synthesis with nonlinear gradient compensation for a high-accuracy current-steering DAC // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2018. Vol. 37. No. 4. Pp. 717-728. DOI: 10.1109/TCAD.2017.2729402
8. Khorami A., Sharifkhani M. Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique // Microelectronics J. 2015. Vol. 46. No. 12. Pp. 1275-1282.
9. Zhang W., Qu R., Zhu M. Non-ideality analysis of current steering DAC // Proc. of the 2020 IEEE Internat. Conf. on Artificial Intelligence and Information Systems. 2020. Pp. 278-282. DOI: 10.1109/ICAI-IS49377.2020.9194898
10. van der Wagt J.P.A., Chu G.G., Conrad C.L. A layout structure for matching many integrated resistors // IEEE Transactions on Circuits and Systems I: Regular Papers. 2004. Vol. 51. No. 1. Pp. 186-190. DOI: 10.1109/TCSI.2003.821303
11. Yao D., Sun Y., Higashino M., Mohyar S.N., Yanagida T., Arafune T., Tsukiji N., Kobayashi H. DAC linearity improvement with layout technique using magic and latin squares // Proc. of the 2017 Internat. Symp. on Intelligent Signal Processing and Communication Systems. 2017. Pp. 616-621. DOI: 10.1109/IS-PACS.2017.8266552
12. Srivastava R.K., Vellathu A., Kaipu S.V.R., Jattana H.S., Rampal A. A systematic method to find an optimized quad-quadrant random walk sequence for reducing the mismatch effect in current steering DAC // Proc. of the 2017 Internat. Conf. on Microelectronic Devices, Circuits and Systems. 2017. Pp. 1-6. DOI: 10.1109/TCAD.2017.2729402
13. Yenuchenko M.S., Korotkov A.S., Morozov D.V., Pilipko M.M. A switching sequence for unary digital-to-analog converters based on a knight's tour // IEEE Transactions on Circuits and Systems I: Regular Papers. 2019. Vol. 66. No. 6. Pp. 2230-2239. DOI: 10.1109/TCSI.2018.2890412
14. Константинов А.И., Енученко М.С., Коротков А.С. Анализ эффективности методик расстановки взвешивающих элементов на кристалле унарного цифро-аналогового преобразователя // Известия вузов. Радиоэлектроника, 2017. Т. 60. № 5. С. 225-232. DOI: 10.20535/S0021347017050041
15. Tong X., Wang C., Wang F. Linearity optimization of current steering DAC based on improved layout topology // Proc. of the 2019 IEEE Internat. Conf. on Electron Devices and Solid-State Circuits. 2019. Pp. 1-3. DOI: 10.1109/EDSSC.2019.8754219
16. Parmar S.S., Gharge A.P. R-2R ladder circuit design for 32-bit digital-to-analog converter (DAC) with noise analysis and performance parameters // Proc. of the 2016 Internat. Conf. on Communication and Signal Processing. 2016. Pp. 467-468. DOI: 10.1109/ICCSP.2016.7754180
17. Lin M.P., Chang Y., Hung C. Recent research development and new challenges in analog layout synthesis // Proc. of the 2016 21st Asia and South Pacific Design Automation Conf. (ASP-DAC). 2016. Pp. 617-622. DOI: 10.1109/ASPDAC.2016.7428080
Статья поступила в редакцию 05.07.2020.
THE AUTHORS / СВЕДЕНИЯ ОБ АВТОРАХ
Salonina Ekaterina A.
Салонина Екатерина Александровна
E-mail: salonina.ea@gmail.com
Belyaev Yakov V.
Беляев Яков Валерьевич
E-mail: designcenter.spb@mail.ru
Piatak Ivan M.
Пятак Иван Михайлович
E-mail: i.m.piatak@gmail.com
© Санкт-Петербургский политехнический университет Петра Великого, 2020
