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VERIFICATION OF MANUFACTURABILITY OF IC DESIGNS
WIESLA W KUZMICZ, ZBIGNIEW JA WORSKI
Institute of Microelectronics and Optoelectronics Warsaw University of Technology, Warsaw, Poland (wbk,zj)@imio.pw.edu.pl
Abstract. This paper introduces the concept of design for macufacturability and discusses relations between IC chip size, manufacturing yield and chip cost. Origins of parametric and catastrophic faults in VLSI chips are presented. Random and deterministic variations inherent in semiconductor manufacturing processes are discussed and several approaches to yield estimation are compared. Simple worst case corner analysis is not suitable for this purpose and only statistical simulation of circuit behavior allows for yield estimation. Moreover, only methodology based on statistical simulation of the manufacturing process accounts for spatial correlation of devices parameters which phenomenon is vital for proper operation of analog designs.
1. Introduction
The technical goal of design of an IC chip is to develop a product which meets its specifications when manufactured in a particular manufacturing process. Various verification procedures such as logic simulation, circuit simulation, DRC and LVS are used to prove that the design is formally and functionally correct. Unfortunately, an IC design which passes all standard verification procedures may still turn out to be not manufacturable. We say that a VLSI chip is manufacturable if the percentage of manufactured chips which meet all technical specifications (known as manufacturing yield) is high. This yield is always less than 100%. What level of yield is acceptable depends on economic constraints because low yield means high chip cost. The goal of this paper is to discuss various reasons for yield losses, in order to help IC designers to optimize their designs from the viewpoint of yield as well as manufacturing cost. This idea is known as design for manufacturability. The manufacturing cost of an IC chip is roughly proportional to the ratio Ac/Y, where Ac is the chip area and Y is the manufacturing yield. Minimization of the manufacturing cost is nontrivial because the area and yield are not independent, and relationships between them are complex. As a result, in engineering practice the design goal is usually formulated as follows: to develop a design which is logically and electrically correct and contains no DRC violations (otherwise the yield would be very low or even zero), and occupies the minimum area. More subtle aspects of the design that address the problems of manufacturability are either neglected or in the best case treated superficially. In this paper we will try to show how to account for these problems in the IC design process.
2. Manufacturing imperfections
A manufactured chip canbe faulty in two ways: either the chip works but its performance is out of specifications (parametric fault), or the chip does not perform its function at all (catastrophic fault). To avoid both types of faults, the designer must first of all make sure that the design is correct. This verification is usually performed in two phases:
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Phase 1: checking whether the design passes standard formal verification procedures: DRC, LVS, logic simulations and electrical simulations with nominal values of device parameters.
Phase 2: checking of the robustness and insensitivity of the design with respect to secondary parasitic effects such as substrate coupling noise, high frequency parasitic coupling, transmission line effects etc.
Let us assume that the design passes all verification procedures in both phases1. If so, failures will result from imperfections that occur in manufacturing processes. For the purpose of our discussion it is convenient to divide these imperfections into three groups: process disturbances, layout disturbances and structural defects.
- Process disturbances are variations of processing parameters such as temperatures, processing times etc. as well as variations of quality ofthe semicondutor material such as doping concentration, carrier lifetime or density of crystallographic defects in the substrate wafers.
- Layout disturbances are deviations of the device and interconnection sizes, shapes and dimensions. These disturbances may result from such imperfections as mask misalignment and under/overetching of the exposed photoresist. In deep submicron CMOS technologies additional effcts are observed. To obtain minimum dimensions which are comparable to or smaller than deep UV exposure light wavelength, special corrections of mask shapes and/or phase shitfing masks are used (see two recent papers [4,5] for an overview). As a result, shapes and dimensions of geometrical patterns printed on IC wafers depend on other adj acent patterns - a phenomenon known as proximity effect. This seriously complicates layout design rules and increases sensitivity of device dimensions to random disturbances.
- Structural defects are imperfections in devices and interconnections such as shorts and breaks due to spot defects, pinholes in gate oxide, missing contacts and shorts due to residual metal.
All imperfections regardless of their nature and origin can be classified as either global or local. Global imperfections affect all nominally identical components in the same way (i. e. electrical characteristics of identical components remain identical). Local imperfections affect every component individually. Due to local imperfections electrical characteristics of nominally identical components become different. Many kinds of imperfections may have both global and local components. A good example is temperature in a thermal process. If the temperature in a furnace differs from its nominal value, this difference affects all wafers processed simultaneously. This is an example of a global variation. At the same time the temperature may exhibit nonuniform distribution within the wafers, for example it may be slightly higher at the periphery of the wafers than in their centres. This is an example of a local variation.
1 We assume here that all simulations in both phases reflect the real behaviour of the circuit with sufficient accuracy (good device models, accurate modeling of parasitic effects etc.).
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Both local and global variations may have deterministic and random components. Here a good example is the concentration of dopant atoms. Doping profiles resulting from either diffusion or ion implantation depend on the thermal history of the wafer. Higher temperatures in thermal processes result in deeper penetration of dopant atoms. If the temperature in a thermal process such as post-implant annealing is lower in the middle of the wafer than on the periphery, the depth of doped region will be lower in the middle and higher on the periphery of the wafer. This is a local deterministic variation. However, doping profiles are also affected by random variations. One of the reasons is fundamental - it is the stochastic nature of doping processes. Even if there are no other reasons, the doping concentrations will exhibit short range variations around the average value. This phenomenon becomes more and more important in deep submicron techologies. Another reason for local random variations of doping profiles is in dependence of the diffusivity on the density of crystallographic defects in the substrate.
In more precise terms the local value p(x,y) on the wafer of a quantity p which is affected by local and global, deterministic and random variations is given by
p = pnom +Apg +Apld(x,y) + Ap1t . (1)
where pnom is the nominal value, Apg is the global disturbance, Apld is the local deterministic disturbance which is a function of the position (x,y) on the wafer and Aplr is the local random disturbance. It is often observed that random variables Apg and Apld have normal distributions, and the deterministic component Apld(x, y) exhibits radial dependence.
This is qualitatively illustrated in Fig. 1.
Fig.1. Global, local deterministic and local random disturbances. The origin of the coordinate system is in the center of the wafer, R is the radius of the wafer
The concepts of global, local deterministic and local random disturbances are not appropriate for structural defects. These occur more or less randomly on the wafers. They can be characterised by average density D (number of defects per unit area) and defect size distribution function. Details are beyond the scope of this paper.
3. Imperfections and faylts
Manufacturing imperfections may or may not affect the circuit functionality and performance. The art of good IC design is to make a design which is not only correct but also insensitive to imperfections. This is why a designer should understand the origins of the imperfections and know how they can affect his/her design.
In a well designed integrated circuit global disturbances usually affect chip performance but not its functionality. Digital CMOS circuits are good examples. It is well knownthat correct operation of static CMOS logic gates depend on the relationships between W/L ratios of nMOS and pMOS transistors. If a global underetching of the polysilicon layer occurs, channel lenghts L of all the transistors will be larger than nominal, but the relationships between the W/L ratios will not be affected. The chip will work normally but its speed will be lower than expected.
Local disturbances affect the chip performance in more subtle ways. In general, they introduce mismatch where matching is expected. Mismatch effects are typical for analog circuits. One of the basic assumptions in analog IC design is that local components of process and layout disturbances are much smaller than global components. Common design practice is to minimize the effects of global disturbances by making the design sensitive to the ratios of the parameters of the components rather than to their absolute values. Unfortunately, as the VLSI technology develops toward deep submicron sizes of the components, the magnitude of local disturbances increases resulting in increased mismatch.
Contrary to common belief mismatch effects are not limited to analog circuits. In large digital chips one of the most difficult design problems is to minimize clock skew, i.e. to design the clock distribution circuitry in such a way that clock pulses reach all clocked gates at the same moment. Large local disturbances may introduce mismatch of the clock pulse delay times on various paths. This results in degradation of the chip performance: the maximum clock frequency must be reduced. Mismatch effects are also of high importance in circuits which perform digital functions but are internally analog, such as dynamic RAM chips.
Averaging effect may help to reduce the influence of local disturbances: large components exhibit lower sensitivity than small ones. This is reflected in “Pelgrom’s law” [6]: the magnitude of mismatch of a certain electrical parameter P between two supposedly identical devices on the same chip is inversely proportional to the square root of their area A: AP<x>1/ VA . A good example is threshold voltage mismatch in MOS devices which is inversely proportional to (WL)1/2. This is illustrated in Fig. 2.
Fig. 2. Example of threshold voltage mismatch in a pair of nMOS transistors as a function of channel area.
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Another property of device mismatch is its dependence on the distance between the devices. Experience often shows that matching is better for a pair of devices close to each other than for a pair of the same devices separated by a large distance. However, it is worth mentioning that if local disturbances were purely random and uncorrelated, mismatch would not depend on the distance between the devices. Matching is a function of distance only if there is a deterministic component of local disturbances2.
In practice the random and deterministic local disturbances are often not distinguished from each other: deterministic disturbances appear to be random. This results from randomness of orientation of a randomly selected chip with respect to the gradient of the quantity that exhibits local deterministic variation. This is illustrated in Fig. 3.
Fig. 3. Radial deterministic local disturbance results in mismatch of a pair of devices in location B but not in location A
A pair of devices in location A is not affected by radial deterministic disturbances because both are located at the same radius R. On the contrary, a similar pair of devices in location B will exhibit mismatchbecause they are not equally distant from the center of the wafer. When a sample of randomly selected chips is tested, mismatch due to deterministic disturbances appears to be random because positions of the chips on wafer are random and unknown. In general, excessive global and/or local disturbances lead to parametric faults. However, in extreme cases these disturbances may affect the circuit operation so severely that it stops working completely (e.g. if operating points of some active devices become shifted from active region to subthreshold or cutoff region). Therefore global and local process and layout disturbances may result in catastrophic faults as well.
Spot defects and other structural defects may or may not affect chip operation depending on their size and position. Defects of the size comparable to or larger than the typical dimensions of geometrical objects on the masks may result in catastrophic faults, e.g. shorts or breaks in the metal interconnections. It is usually assumed that structural defects result in catastrophic faults. However, defects of smaller sizes may affect the circuit performance parametrically, e.g. by increasing or reducing resistances, capacitances or transistor channel dimensions and result in performance degradation and parametric faults. In the next sections of this paper we will neglect structural defects and focus our attention on process and layout disturbances.
2 Yet another reason may be nonuniform temperature distribution in the working chip. Difference in temperatures in two otherwise identical devices leads to difference in their electrical characteristics. This effect is, however, not discussed here.
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4. Design for manufacturability Overview of the methodologies
As mentioned above, cost of making a VLSI chip is roughly proportional to the ratio Ac/Y. This makes cost optimization difficult, because in general there is a tradeoff between chip area and yield. For example, lower mismatch and lower probability of parametric faults in an analog IC may be achieved by increasing dimensions of matched devices (see Fig. 3), but this leads to increase of chip area3. Therefore minimization of the Ac/Y ratio is not a standard engineering practice. Minimization of chip area and maximization ofyield are considered separately. An example is the practical rule often used in digital design: “pack the components in the chip as densely as possible but do not violate design rules”. For moderately complex designs this rule usually leads to acceptable digital chip designs with chip area close to minimum and acceptable yield.
As it can be seen from our discussion, the process of manufacturability oriented IC design should be performed in three major phases. The first two of them have already been mentioned in Section2.
Phase 1: Making a formally correct design. This involves the following steps which include some rudimentary precautions addressing manufacturability:
- Selection and design of a circuit which is inherently insensitive to global variations of device parameters. Static CMOS logic gates have this property as far as logic levels and noise margins are considered but global variations affect such parameters as threshold voltages, parasitic capacitances and carrier mobilities leading to sensitivity of switching times to these variations. Analog circuits are insensitive if their performance depends on ratios of device parameters rather than on absolute values. This is usually achieved by means of symmetry (as in differential amplifiers) and/or compensation effects which are based on device matching paradigm.
- Design of a layout which does not violate design rules and (if necessary) uses simple intuitive rules to obtain good device matching: large device dimensions reduce relative sensitivity to under/overetching, close proximity of devices which are supposed to be identical reduces the effect of deterministic and random correlated disturbances (as well as effects of thermal gradients, if they are present), identical device orientation reduces sensitivity to mask misalignment and under/overetching effects, “common centroid” layout helps to compensate all kinds of deterministic and random correlated disturbances.
- Verification of formal and functional correctness of the design (DRC, circuit extraction, LVS and post-layout circuit simulation with nominal values of device parameters). This step may easily include extraction and electrical simulation with lumped parasitic components such as interlayer capacitances, giving more realistic prediction of performance of the circuit, but more complex parasitic effects are not taken into account.
3 When yield is limited by structural defects, the opposite tendency is observed. Smaller chips have better yields because lower chip area means lower probability of occurrence of a structural defect.
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Phase 2: Verification and optimization of the design with respect to secondary parasitic effects. Since these affects are sensitive to physical structure of the chip, this phase cannot start before layout design is completed, and may lead to layout redesign (in extreme cases it may become necessary to go back to circuit design and make changes in it). This phase may include e.g.:
- Thermal analysis of the design: finding the temperature distribution, thermal gradients and estimating their influence on circuit’s preformance.
- Analysis of parasitic coupling via substrate and in mixed mode (analog-digital) chips influence of switching noise generated by the digital part of the chip on performance of the analog part.
- Analysis of transmission effects in long interconnections such as delays, clock skew, capacitive and inductive coupling etc.
- Analysis of performance of RF circuits (e.g. bandwidth, amplitude and phase characteristics, noise, stability) with actual physical design (active and passive parasitics, coupling etc.) taken into account.
Phase 3: Verification of sensitivity to manufacturing imperfections and minimization of this sensitivity. The main goal of this phase is to predict statistical spread of the characteristics of the circuit and estimate probability of parametric and catastrophic faults resulting from all kinds of variations of device parameters. In principle this verification might include:
- Worst case analysis (also known as corner analysis), i.e. electrical simulation of the circuit for “process corners”: sets of minimum and maximumvalues of device parameters that are considered acceptable in the manufacturing process and lead to extreme circuit performance, e.g. the highest and the lowest speed.
- Simple statistical circuit simulation where in a Monte Carlo loop device parameters are varied by means of random number generators according to statistical distributions observed in the process Simple simulation means here that all the parameters of all the devices are varied independently of one another, and correlations are neglected.
- Advanced statistical circuit simulation which is similar to the simple one but additional mechanisms in variation of device parameters are used to account for the most important correlations between device parameters and to simulate mismatch.
- Netlist driven statistical manufacturing process, device and circuit simulation where manufacturing of the IC devices is simulated in a Monte Carlo loop, with all kinds of process disturbances accounted for, and is followed by circuit simulation. Such a simulation accounts for all kinds ofprocess disturbances in the most realistic way [7-10].
- Estimation of design sensitivity to spot defects by means of evaluation of the critical areas - parts of the mask where spot defects of a given size result in a catastrophic failure [11,12]. If the critical areas are known, an attempt canbe made to redesign the layout in order to reduce their total area. This is not discussed in this paper.
To perform all these analyses and verifications, two conditions must be met: appropriate CAD tools must be available, and designers must be aware of them and know how to use them. The state of the art is as follows:
- All tools necessary in phase 1 exist, are mature and easily available (although commercial versions are expensive), and routinely used by IC designers.
- Tools necessary in phase 2 exist and some of them are available in commercial CAD systems. However, they are often difficult to use, not always reliable, and the results produced are not always realistic. The quality of the results often depends on good understanding by the designer of the nature of the problem investigated, because the designer must make decisions what is to be simulated and how.
- Tools necessary in phase 3 also exist, some of them are included in commercial CAD toolsets but many are still subject of research, far from being fully mature despite long history of their development [ 1 -3 ]. Another problem is in lack or inaccessibility of statistical data related to manufacturing imperfections. Such data are difficult to collect and even if they exist, they are usually treated as strictly confidential by the manufacturers. In this situation the resuls obtained by available tools are often unrealistic. As a result, verifications in phase 3 are very often omitted.
In the next subsections we will discuss in more detail methods and tools that can be used in phase 3. In this discussion we will use as a simple example the circuit shown in Fig. 4.
Fig. 4. The example circuit: a differential pair biased by a current source, with external load resistors
Two layouts - the simple one (Fig. 5a) and the “common centroid” one (Fig. 5b) - will be considered.
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a
b
Fig. 5. Two layouts for the circuit shown in Fig. 4: simple (a) and common centroid (b)
The nominal DC transfer curve for this circuit is shown in Fig. 6.
Corner analysis This kind of analysis becomes very often the first choice of a designer since it is easy to understand and many CAD tools can perform it automatically. The process corners are defined by the process vendor. In the case of MOS devices there are usually five corners: typical mean (TM), worst case power (WP), worst case speed (W S), worst case zero (WZ), worst case one (WO).
Corners analysis has two advantages:
- it uses limited number of corners from the device parameter space (instead of process parameter space), • it is easy to understand by an average engineer who is not familiar with details of IC manufacturing.
However, this method has also severe limitations:
- mismatch effects are not visible since all the devices of the particular type, e.g. nMOS transistors, receive the same model (comer),
- the analysis accounts for global variations only,
- parametric yield cannot be estimated,
- for some circuits the worst case performance may be obtained for a different combination of device parameters than corner parameters.
The results of corner analysis performed for TM, WP, WS, WZ, WO corners for the nMOS transistors (with IMOhm resistors treated as external elements) are shown in the Fig.7.
The shifts of the curve illustrate sensitivity to global process disturbances. Rough estimation of the design sensitivity to these disturbances is the only result that can be obtained. Mismatch related offset - which is a crucial performance measure in differential amplifiers - cannot be observed.
Fig.6. Resuls of DC sweep simulation (Voutn = f(Vinn)) for circuit shown in Fig. 5 for nominal values of transistors parameters
Statistical circuit simulation
Many circuit simulators used in IC design provide statistical (Monte Carlo) simulation option which allows to estimate statistical spread of circuit parameters, not only the worst case values. This simulation allows also to estimate mismatch
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Fig. 7. Results of corner analysis for the example circuit
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related effects usch as offset in a differential amplifier. To estimate such effects, every device in the design must be represented by an individual model. To account for statistical spread of device parameters values of such parameters as MOS transistor threshold voltage or carrier mobility are replaced with random number generators. The generators should be setup to reflect process-related disturbances. The choices of random number generator type (uniform or normal) and generator parameters are crucial in this methodology. The designer should understand very well what disturbances are accounted for and how, otherwise the results may be easily misinterpreted.
T o illustrate this, statistical Monte Carlo circuit simulation was applied to the example design. The difference in the output voltages observed at the terminals outn and outp was chosen as the measure of the offset. This voltage was observed as the function of the common mode voltage applied to both inputs (i.e. differential input voltage was equal to 0). The two netlists were obtained via extraction from both layouts. Every nMOS transistor received its own BSIM3v3 model and the vth0 and u0 parameters were replaced with random number generators of normal distribution. The generators setup was typical for modeling the nature of local process disturbances: the mean value was equal to nominal parametervalue while the standard deviation was set to obtain value spread equal to ±1% of the mean value on the 3 s level4. The example of a family of DC sweeps is shown in Fig. 8.
The histograms presented in Fig. 9 show the offset observed for the common mode input voltage equal to 0.86V - the point where offset reaches maximum. It can be clearly seen that the offset is smaller in the case of the common centroid layout. This seems realistic but in fact has nothing to do with layout quality and is strictly related to the simulation mechanism -summing of two randomly disturbed drain currents in two transistors connected in parallel, where random disturbances
may more or less compensate each other. We will see later that in fact this result is unrealistic and misleading.
Mean-1.94 Std.dev.=224.22
■1000 -500 0 500 1000
Offset [mV]
b
Fig.8. Simple MC simulations: offset voltage at the output for basic layout version (Fig. 5a) for local transistor parameters disturbances (500 DC sweeps)
4 Note that if the random number generators reflected global disturbances, the results of simulation of mismatch effects would be totally unrealistic - greatly exaggerated
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Fig.9. Offset distributions obtained from simple MC simulation for: a - basic version; b - common centroid version
Further improvements to yield estimation methodology can be made by including device parameters correlation and some of the layout related phenomena such as Pelgrom law. These improvements can be introduced to simple statistical simulation methodology by appropriate extensions of the device models. The Pelgrom law can be implemented by building the (WL)-1/2 dependency into transistor model formula for random generation of the threshold voltage and other relevant parameters. Another possible improvement can be in so called nested random generation of device parameters. The idea is that the first level generator is responsible for creating global parameter distribution. Next, the parameter value obtained from the first level generator is used as the mean value for the second level generator which creates local parameter distribution. These ideas are very useful for making Monte Carlo circuit simulations more realistic but require in-depth knowledge of the process statistics. Some process vendors provide such statistical simulation oriented device models.
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In order to check how the advanced statistical simulation methodology changes the offset estimation of our example designs the same experiment has been carried out again with device models and random number generators extended as described above. The models and parameters were provided by the process vendor. The resulting offset histograms are presented in Fig.10. The estimated offset is about 50% of the value obtained from simple statistical simulation, and there is no significant difference between simple layout and common centroid layout.
Mean=11.51 Std.de«.=ll?.75
40 ”1---------:---------:--------J---------
30
20
10
Offset [mV]
a
b
Fig.10. Offset distributions obtained from advanced MC simulation for: a - basic version; b - common centroid version.
The examples above demonstrate that for the same design and the same process statistical circuit simulation may yield very different results depending on the way in which statistical data is used in the simulation process. Although results of the advanced statistical simulation are closer to reality, this approach has still some weaknesses:
- no spatial correlations between different devices (it is impossible to estimate quality of different layout versions),
- implementation of the Pelgrom law does not account for all the nuances of design sensitivity to layout (e.g. shape, position and orientation of transistors are disregarded),
- no intra-device correlations (parameters of a particular transistor are not correlated) • layout disturbances are not accounted for.
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As a result, layout quality still cannot be properly evaluated. Statistical circuit simulation cannot be used to compare two different layouts to choose the one with optimal area to yield ratio.
Layout driven methods
It has been demonstrated [7,8] that methodology based on coupled statistical process/device simulation, circuit extraction andcircuit simulationcanprovide realistic predictionofmismatch-related IC performances and thus parametric yield. This methodology has been applied to both versions of the example circuit. Each design was simulated in the following way:
- 500 chip samples were randomly distributed over 1 wafer,
- for each sample circuit extraction followed by process/ device simulation were performed,
- the resulting 500 netlists were simulated with a circuit simulator.
The resulting offset histograms are presented in Fig. 11. The estimated offset is about 75% of the value obtained in advanced statistical simulations. This simulation confirms that difference between simple and common centroid layouts is insignificant in our case5.
Mean=6.14 Std.dev.=95.5Z
nmifUifjf IBIMllh nrfl H
400 -200 0 200 400
Offset [mV]
a
b
Fig. 11. Offset distributions obtained from statistical process/ device simulation for a - basic version, b - common centroid version
5 This may seem strange but is correct - it can be proven that common centroid layout is better than simple one only if there are significant deterministic local disturbances.
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The netlist driven statistical simulation gives the most realistic results because all kinds of disturbances are accounted for at the process simulation level in the most natural way. Unfortunately, this methodology has also some disadvantages:
- process simulation requires use of several nonstandard tools and is considered an exotic approach, closer to process engineering than IC design,
- IC designers are not familiar with manufacturing process details and process simulation,
- statistical process/device simulation requires process-related data that are considered confidential by IC manufactures.
These disadvantages prevent widespread use of this methodology. To make it available for IC designers, the concept of „virtual prototyping” Web-based service has been proposed recently [9,10]. The Web server provides the user with interface to submit his/her design and define testbench, performs the simulation processes and returns the results. The user does not need to run any simulations himself and has no access to confidential process data. Such a service is currently being developed by the authors of this paper. Examples of application of it to real designs can be found elsewhere [10].
5. Conclusions
Design for manufacturability is a topic discussed for many years [1-3] but existing engineering practice either ignores its methods or in the best case uses only the simplest of them. As feature sizes in CMOS technology decrease below 100 nm, sensitivity of IC designs to manufacturing imperfections and also to subtle details of physical design will tend to increase. This means that design for manufacturability should become routine part of IC engineering, otherwise progress in manufacturing technology will not be fully exploited. This requires both new approaches and tools and good understanding of the methodology by IC designers.
Acknowledgements
Special thanks are due to Prof. W. Maly, Carnegie Mellon University, who initiated research in this field while he was with WUT. Cooperation and contributions ofProf. A. Strojwas (Carnegie Mellon University), Dr. M. Niewczas (PDF Solutions., Inc.), and members of the WUT team: Dr. E. Piwowarska, Prof. A. Pfitzner, Dr. W. Pleskacz, Dr. A. W oj tasik and many students of WUT are gratefully acknowledged.
This paper has been prepared with financial support from REASON (IST-2000-30193), a FP5 project funded by the European Union. Financial support provided by Polish State Committee for Research for investigations in the field of design for manufacturability (KBN grant no. 4 T11B 028 22) is also gratefully acknowledged.
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