Научная статья на тему 'HIGH-SPEED DECISION FEEDBACK EQUALIZER WITH LOW INPUT CAPACITANCE DYNAMIC LATCH COMPARATORS'

HIGH-SPEED DECISION FEEDBACK EQUALIZER WITH LOW INPUT CAPACITANCE DYNAMIC LATCH COMPARATORS Текст научной статьи по специальности «Медицинские технологии»

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Ключевые слова
CONTINUOUS TIME LINEAR EQUALIZER / DECISION FEEDBACK EQUALIZER / DOUBLE-TAIL COMPARATOR / IC

Аннотация научной статьи по медицинским технологиям, автор научной работы — Grigoryan Manvel T.

The recovery of degraded signal due to channel loss assumes importance in high-speed integrated circuits (ICs) design. Scaling of the CMOS transistor over time gives opportunity to increase data rate in high-speed SerDes protocols. Hence there is a need to design special input-output blocks that will be responsible for providing necessary performance and throughput. Continuous time linear equalizer has controllable boost for Nyquist frequency, but its gain is not enough to compensate channel loss. In this work, another solution is proposed: decision feedback equalizer, which is simple n-tap digital filter and can recover signal after continuous time linear equalizer. The double-tail comparator having low input capacitance and providing faster switching is considered. Simulation results show up to 36.6 % time saving during operation mode. It gives opportunity to increase frequency of data transmission. Eye diagram results have been received for whole system consisting of two-stage continuous time linear equalizer and 1-tap decision feedback equalizer. Eye diagrams show that proposed decision feedback equalizer architecture increases eye height by about 13.9 % and eye width by 13.5 %. The area of decision feedback equalizer circuit has been increased by ~19 % due to added comparators.

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Текст научной работы на тему «HIGH-SPEED DECISION FEEDBACK EQUALIZER WITH LOW INPUT CAPACITANCE DYNAMIC LATCH COMPARATORS»

Original article yaK 621.3.049.77

doi:10.24151/1561-5405-2022-27-3-367-373

High-speed decision feedback equalizer with low input capacitance dynamic latch comparators

M. T. Grigoryan

National Polytechnic University of Armenia, Yerevan, Armenia "SynopsysArmenia" CJSC, Yerevan, Armenia

manvelg@synopsys.com

Abstract. The recovery of degraded signal due to channel loss assumes importance in high-speed integrated circuits (ICs) design. Scaling of the CMOS transistor over time gives opportunity to increase data rate in high-speed SerDes protocols. Hence there is a need to design special input-output blocks that will be responsible for providing necessary performance and throughput. Continuous time linear equalizer has controllable boost for Nyquist frequency, but its gain is not enough to compensate channel loss. In this work, another solution is proposed: decision feedback equalizer, which is simple n-tap digital filter and can recover signal after continuous time linear equalizer. The double-tail comparator having low input capacitance and providing faster switching is considered. Simulation results show up to 36.6 % time saving during operation mode. It gives opportunity to increase frequency of data transmission. Eye diagram results have been received for whole system consisting of two-stage continuous time linear equalizer and 1 -tap decision feedback equalizer. Eye diagrams show that proposed decision feedback equalizer architecture increases eye height by about 13.9 % and eye width by 13.5 %. The area of decision feedback equalizer circuit has been increased by ~19 % due to added comparators.

Keywords: continuous time linear equalizer, decision feedback equalizer, double-tail comparator, IC

For citation: Grigoryan M. T. High-speed decision feedback equalizer with low input capacitance dynamic latch comparators. Proc. Univ. Electronics, 2022, vol. 27, no. 3, pp. 367-373. doi: https://doi.org/10.24151/1561-5405-2022-27-3-367-373

© M. T. Grigoryan, 2022

Научная статья

Высокоскоростной эквалайзер обратной связи с динамическими компараторами, имеющий низкую входную емкость

М. Т. Григорян

Национальный политехнический университет Армении, г. Ереван, Армения

ЗАО «Синопсис Армения», г. Ереван, Армения manvelg@synopsys. com

Аннотация. При разработке высокоскоростных ИС важно учитывать возможность восстановления качества сигнала, ухудшенного из-за потерь в канале передачи данных. Масштабирование КМОП-транзистора дает возможность существенно увеличивать скорость передачи данных в системах. Следовательно, возникает потребность в разработке специальных блоков ввода-вывода, которые обеспечат необходимую производительность и пропускную способность. Асинхронный линейный эквалайзер имеет управляемое усиление частоты Найквиста, но его усиления недостаточно для компенсации потерь в канале. В работе представлен эквалайзер с решающей обратной связью, который представляет собой простой цифровой фильтр с n-отводами и может восстановить сигнал после асинхронного линейного эквалайзера. Рассмотрен динамический компаратор, имеющий малую входную емкость и обеспечивающий более быстрое переключение. Результаты моделирования отражают снижение задержки переключения до 36,6 % в рабочем режиме. Это дает возможность увеличить частоту передачи данных. Получены результаты глазковых диаграмм для всей системы, состоящей из двухкаскадного асинхронного линейного эквалайзера и одноотводного эквалайзера с решающей обратной связью. Глазковые диаграммы показывают, что предлагаемая архитектура эквалайзера с решающей обратной связью увеличивает высоту глаза примерно на 13,9 % и ширину глаза на 13,5 %. Площадь эквалайзера с решающей обратной связью увеличена на ~19 % за счет добавления компараторов.

Ключевые слова: асинхронный линейный эквалайзер, эквалайзер с решающей обратной связью, динамический компаратор, ИС

Для цитирования: Григорян М. Т. Высокоскоростной эквалайзер обратной связи с динамическими компараторами, имеющий низкую входную емкость // Изв. вузов. Электроника. 2022. Т. 27. № 3. С. 367-373. doi: https://doi.org/10.24151/1561-5405-2022-27-3-367-373

Introduction. It is difficult to imagine the operation of modern electronic devices without integrated circuits (ICs) that are installed independently of each other and perform different functions [1]. Nevertheless, integrated circuits are in constant communication with each other and exchanging processed information [2]. For the whole system to work properly, it is necessary to ensure the correct transmission of information in the system between different ICs. Continuous scaling of the CMOS transistor over time has led to an increase in data trans-

Fig. 3. Decision feedback equalizer

fer speeds. It is known that the channel has low-pass filter AC characteristics, hence degraded signal recovery in high frequencies becomes more significant [3].

In modern SerDes architectures continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE) are widely used to compensate channel loss [4]. Conventionally, CTLE is a differential amplifier with embedded degeneration resistance and capacitance (fig. 1). To increase gain of CTLE inductive load is used instead of resistance in differential amplifier [5]. But it can't be controlled over process, voltage and temperature (PVT) variation and occupies large area in IC. To control CTLE's AC performance negative capacitance (Neg-C) circuit can be connected to the output of CTLE [6] (fig. 2). It makes possible to have wide operating frequency range and increase gain. However, in long channels signal loss is higher than -20 dB and CTLE can't compensate it. To recover data DFE circuit is used (fig. 3). It eliminates residual post-cursor of inter symbol interference (ISI).

Each path (odd and even) has two cases, and the selection of right path depends on previous bit. The selection is happening through a multiplexer with respect to the feedback tap coefficient (H1). After choosing right path the comparator makes decision. The conventional double-tail comparator is used in DFE [7] (fig. 4). At the reset mode (when CLK = 0) Out_p and Out_n are resetting to ground. At the operation mode (when CLK = 1) M3 and M4 transistors are open. Mr1 and Mr2 transistors' gate voltage is starting to discharge. Depending on input data one of them will close sooner and the output data will be achieved.

Fig. 4. Conventional double-tail comparator

Proposed DFE circuit. To speed up DFE operation mode it has been proposed to use improved version of double-tail dynamic latch comparator (fig. 5).

In this architecture M9 and M10 transistors are used instead of Mtail2. At the reset stage the voltages of np and nn nodes are connected to VDD via Mr1 and Mr2 transistors. So, the voltages of np and nn are equal to VDD, which closes M9 and M10 transistors. At the same time M11 and M12 transistors set fp and fn to 0, hence the outputs become equal to VDD. This function gives opportunity to disconnect regenerative latch from supply voltage. At the comparison stage M1 and M2 transistors start to discharge np and nn nodes. Due to input data, they have different currents. With the help of M5 - M8 transistors the output data is achieved. After operation mode they have different voltages. The voltage at the node having high voltage value decreases more quickly due to charge injection which produce offset. To reduce offset between fp and fn the Mr3 transistor is used. M3 and M4 transistors decrease load for previous stage and the speed of comparator increases.

Fig. 5. Proposed double-tail comparator

Simulation results. The proposed scheme was designed with "SAED 14nm" FINFET technology [8] and "Custom compiler" software tool [9]. All results were received with HSPICE circuit simulation tool [10]. To check performance of proposed double-tail dynamic latch comparator transient simulation was done. Results and comparison with conventional solution for worst corner are presented in fig. 6.

Trartsien (Comparison

£ ° =

x. 112.1 Op / / -

Level: 0.45359 Y (Г

/ / x: 95 141p 05p V

x: 65 \

loop

«0)

(V):«s)

1 - proposed

2 - conventional J - clock

Fig. 6. Delay of conventional and proposed double-tail comparators

Simulation has demonstrated that for conventional and proposed double-tail dynamic latch comparators (in worst corner) the delay is 46.51 and 29.491 ps, respectively, and the difference is 17.019 ps (-36.6 %). Hence, the proposed double-tail comparator's delay time for operation mode is by about 36.6 % less than the conventional comparator's delay time.

To check performance of whole system consisting of two-stage CTLE and 1-tap DFE eye diagram results were measured via transient analysis (fig. 7). The results received from eye diagram and comparison of conventional and proposed solutions are summarized in table.

б

Fig. 7. Eye diagrams with conventional DFE (a) and proposed DFE (b)

Eye diagram results with conventional and proposed DFE

Parameter With conventional DFE With proposed DFE Difference

Eye height, mV 51 64.9 13.9 (+27.25 %)

Eye width, ps 62.7 71.2 8.5 (+13.5 %)

The values given in the table indicate that proposed DFE configuration gives opportunity to increase eye height by about 13.9 % and eye width by 13.5 %.

Conclusion. Proposed double-tail comparator has improved delay time compared with conventional solution. Additional architecture is responsible for reducing input capacitance and provides faster switching for outputs. Simulation results showed that operation mode takes about 36.6 % less time which improves performance of whole system and gives opportunity to increase data rate. It has been suggested to use proposed double-tail comparator in DFE block. Eye diagrams showed that proposed DFE architecture increases eye height by about 13.9 % and eye width by 13.5%. The area of DFE circuit has been increased by ~19 % due to added comparators.

References

1. Stojanovic V. High-speed serial links: design trends and challenges. Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05). Banff, IEEE, 2005, p. 514. doi: https://doi.org/ 10.1109/IWSOC.2005.72

2. Rashdan M., El-Sayed F., Salman M. Performance comparison between SerDes and time-based serial links. 2020 7th International Conference on Electrical and Electronics Engineering (ICEEE). Antalya, IEEE, 2020, pp. 37-41. doi: https://doi.org/10.1109/ICEEE49618.2020.9102626

3. Zhou N., Huang K., Lve F., Wang Z., Zheng X., Zhang Ch., Li F., Wang Zh. A 76 mW 40-Gb/s SerDes transmitter with 64: 1 MUX in 65-nm CMOS technology. 2016 6th International Conference on Electronics Information and Emergency Communication (ICEIEC). Beijing, IEEE, 2016, pp. 155-158. doi: https://doi.org/ 10.1109/ICEIEC.2016.7589709

4. Choi Y., Kim Y.-B. A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer. 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). Fort Collins, CO, IEEE, 2015, pp. 1-4. doi: https://doi.org/10.1109/MWSCAS.2015.7282072

5. Zheng K., Frans Y., Chang K., Murmann B. A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS. 2018 IEEE Custom Integrated Circuits Conference (CICC). San Diego, CA, IEEE, 2018, pp. 1-4. doi: https://doi.org/10.1109/CICC.2018.8357076

6. Grigoryan M. T., Atanesyan A. A., Hakobyan G. H., Harutyunyan S. S. Two stage CTLE for high speed data receiving. 2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO). Kyiv, IEEE, 2020, pp. 374-377. doi: https://doi.org/10.1109/ELNANO50318.2020.9088865

7. Razavi B. Design of Analog CMOS Integrated Circuits. 2nd ed. New York, McGraw-Hill, 2015. 782 p.

8. Melikyan V., Martirosyan M., Melikyan A., Piliposyan G. 14nm Educational Design Kit: capabilities, deployment and future. Proceedings of the 7th Small Systems Simulation Symposium, 2018, February 12-14, Nis, Serbia. Nis, Faculty of Electronic Engineering, 2018, pp. 37-41.

9. Galaxy Custom Designer Schematic Editor User Guide. Synopsys Inc., 2014. 236 p.

10. HSPICEReference Manual. Synopsys Inc., 2017. 846 p.

The article was submitted 15.03.2022; approved after reviewing 29.03.2022;

accepted for publication 04.05.2022.

Information about the author

Manvel T. Grigoryan - PhD student of the Electronics, Micro and Nanoelectronics Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Analog and Mixed Signal Circuit Design Engineer, Eng. II, "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), manvelg@synopsys.com

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