A VOLTAGE CONTROL SYSTEM FOR A LOW-POWER DEVICES TO ADDRESS TRANSISTOR OVERSTRESS IN I2C SYSTEMS Текст научной статьи по специальности «Электротехника, электронная техника, информационные технологии»

Original article

yflK 621.3.049.77:621.382.3:621.3.015 doi:10.24151/1561-5405-2022-27-3-374-381

A voltage control system for a low-power devices to address transistor overstress in I2C systems

• 1 2 * 12 3

V. Sh Melikyan , H. V. Gumroyan , D. S. Shaljyan ' , D. V. Manucharyan

1 "Synopsys Armenia" CJSC, Yerevan, Armenia 2National Polytechnic University of Armenia, Yerevan, Armenia Armenian National Agrarian University, Yerevan, Armenia

vazgenm@synopsys.com

Abstract. Modern standard cell libraries most commonly contain low-power devices designed without high voltage drivers. Once these devices are connected to high voltage data buses, this can lead to data loss issues and rapid depreciation of connected devices. An example of communication protocol using high voltage level (3.3 or 5 V) for data transmission lines is Inter-Integrated Circuit (I2C). By adding a voltage control system it is possible to avoid transistors degradation in such systems. In this work, a novel approach in I2C and low voltage transistors communication is considered: a voltage control system is proposed that allows connecting low-power devices to I2C bus without additional voltage calibration outside the integrated circuit. It has been demonstrated that proposed voltage control system reduces the voltages on data communication lines and uses it as a bias voltage for the receiver or transmitter input buffers. The developed system ensures the input buffers protection from overstress while supplying the bias voltage on the output of voltage controller system.

Keywords: integrated circuit, inter-integrated circuit, I2C system, voltage calibration, bias voltage, transmitter, receiver

For citation: Melikyan V. Sh., Gumroyan H. V., Shaljyan D. S., Manucharyan D. V. A voltage control system for a low-power devices to address transistors overstress in I2C systems. Proc. Univ. Electronics, 2022, vol. 27, no. 3, pp. 374-381. doi: https://doi.org/10.24151/1561-5405-2022-27-3-374-381

© V. Sh. Melikyan, H. V. Gumroyan, D. S. Shaljyan, D. V. Manucharyan, 2022

Научная статья

Система управления напряжением для уменьшения перенапряжения транзисторов в маломощных устройствах, подключенных к системе I2C

1 2 12 3

В. Ш. Меликян , Р. В. Гумроян , Д. С. Шалджян ' , Д. В. Манучарян

1ЗАО «Синопсис Армения», г. Ереван, Армения

2

Национальный политехнический университет Армении, г. Ереван, Армения

Национальный аграрный университет Армении, г. Ереван, Армения vazgenm@synopsys.com

Аннотация. Современные библиотеки стандартных ячеек, как правило, содержат устройства, спроектированные только с помощью маломощных транзисторов. Подсоединение таких устройств к высоковольтным шинам передачи данных может привести к потере данных, а также скорому износу подключенных устройств. Примером протокола, в котором для управления линиями данных используется высокое напряжение (3,3 или 5 В), является Inter-Integrated Circuit (I2C). Используя системы управления напряжением, можно уменьшить износ транзисторов в подобных системах. В работе предложена система управления напряжением, которая дает возможность подключать маломощные устройства к шине I2C без дополнительной калибровки напряжения вне интегральной схемы. Показано, что рассматриваемая система снижает напряжения на линиях передачи данных и использует их в качестве напряжений смещения для входных буферов приемника или передатчика. Применение разработанной системы управления напряжением обеспечивает защиту входных буферов от преждевременного износа при подаче напряжения смещения на выход регулятора напряжения.

Ключевые слова: интегральная микросхема, система I2C, калибровка напряжения, передатчик, приемник, напряжение смещения

Для цитирования: Меликян В. Ш., Гумроян Р. В., Шалджян Д. С., Манучарян Д. В. Система управления напряжением для уменьшения перенапряжения транзисторов в маломощных устройствах, подключенных к системе I2C // Изв. вузов. Электроника. 2022. Т. 27. № 3. С. 374-381. doi: https://doi.org/10.24151/1561-5405-2022-27-3-374-381

Introduction. The rapid progress of semiconductor industry [1] resulted in the development and advancement of data transfer methods between electronic components. The whole variety of standards for these data communications [2, 3] can be split into two major categories:

- parallel - data exchange occurs simultaneously along several buses;

- serial - data transfer occurs on a bus by using serializer and deserializer systems [4]. The most common applications of the serial data transfer protocol are the Universal Serial

Bus (USB), 1-Wire and the Inter-Integrated Circuit (I2C). The I2C interface uses two wires for data transfer: serial data line (SDA) used to send/receive data for master and slave devices,

and serial clock line (SCL) for transmitting the clock signal. Therefore, the connected devices do not require an additional data line [5].

The I2C interface is synchronous, which means that only one device can be a master at a time and data transfer between connected devices is synchronized with clock controlled by the master. The start and stop signals initiate and finish data communication [6, 7]. Data sharing in I2C system occurs in such a way (see e. g. [8, p. 161]) that during the data transfer process the SDA and SCL lines are constantly switching, which leads to a continuous operational mode change in the transistors of the input buffer. The most common application of I2C protocol is the connection to liquid crystal display (LCD). In such modules the voltage values used in I2C are 5 and 3.3 V. The I2C protocols are also used during a final test of a packaged IC. If the voltage control is not correctly handled at this stage the wafer tests can damage the chip and lead to a final test failure and yield loss. With technological node continuous shrinking the transistor overstress in IC design using FinFET technology becomes more challenging. Modern ICs are designed with the low-power techniques and that requires a certain design to be performed for I/O systems maintenance [9, 10]. The supply voltages have dropped up to 0.8 V inside the IC systems. Since the voltages on the rest of the board are higher it became a necessity to design I/O blocks that can maintain these differences in the voltage values [11, p. 375-381]. Improper voltage handling in the transmitter/receiver (Rx/Tx) block can lead to additional stress on the input buffers and cause a functional failure.

In most cases the input buffer can be represented as a single NMOS transistor directly connected to a data transfer bus. Once the system is ready to launch, the SDA and SCL lines are pulled up. When the device participates in data transfer process, i.e. is turned on, the input transistor is not considered to be under the stress. Conversely, when the device is turned off there are no internal supply voltages, although the 3.3 V line is still active. Since the devices are constantly connected to high voltage the drain-source voltage on the input transistor is equal to 3.3 V as well. This will lead to transistor parameters degradation and the I/O block operational failure, i.e. transistor overstress. To avoid these issues a drain voltage on the input transistor should constantly be biased. The known approach to handle this scenario is to insert additional control systems into the line to be able to pull off the connected devices when those are not a part of data communication process. For a turned off device, the data input is equal to logic 0 and the input transistor (m1) is in the cut-off mode. Once the voltage is applied to the bias transistor (mb), the voltage value on mb's source starts to rise. Since the m1 drain is connected to the mb's source and the value of that point is never going to reach the voltage value on SDA/SCL lines, the m1 is not going to be under stress. When the device is turned off there is no actual supply for generating the Vbias voltage. To generate the bias voltage SDA and SCL lines can be used.

Proposed voltage controller system architecture. To reduce usage of the external systems it has been proposed to embed a voltage control system (VCS) into the input transistor buffer. Proposed system implements a bias voltage generation for turned-off device connected to the data lines as part of a voltage control circuit which will drop the voltage value from the SDA/SCL lines to a required nominal value. The target bias voltage value was assumed equal to 1.8 V and the voltage on the data lines to 3.3 V.

As shown in fig. 1, two parallel diodes are connected to the SCL and SDA lines. At first stage the voltage is dropped by a threshold value of the first diode. Then two parallel diodes are connected to third one that drops the voltage value by another threshold. Connecting diodes in such manner helps to avoid shorts creation between SDA and SCL lines. The input buffer transistors are considered not to be under overstress when the bias voltage is around devices' VDD value on the data lines.

Output voltage on the bias net is formed based on the enable signal value, which determines whether the power supply for the system is turned on or off. When the system is connected to the supply line, the voltage on vdd1v8 net is set to 1.8 V. This means that the system works in operational mode, i.e. the enable value is also set to 1.8 V. Therefore the mp1 transistor operates in triode mode, and the mp2 transistor in cut-off, which means that the voltage value on bias is equal to the value on vdd1v8.

When the system is turned off the enable value is 0 V, which changes the state of the mp2 transistor to triode mode and mp1 to cut-off. Once the mp2 transistor is opened the voltage formed by the control system is going to be applied to bias net.

With the implemented system the voltage on the bias is not dependent on whether the system is turned on or off and is always equal to 1.8 V. The bias net is connected to the bias transistor in the transmitter. This means that the voltage value on the gate of this transistor is 1.8 V as well and is independent from the system operation. This implementation makes it possible to overcome stress related issues in the transmitters' input buffer.

Simulation results. During the IC modeling process additional simulations are required to estimate the potential IC failures. These simulations are using specific aging models helping to determine potential flaws in chip operation during time. Once the IC is fabricated, the same models are used again as a part of a chip final test. Synopsys HSPICE circuit level simulator was used for the results simulations performed for 27 PVT corners, including FF (fast-fast), SS (slow-slow), TT (typical-typical), with supply voltage ±10 % and temperature ranging from -40 to 125 °C variations using 14nm FinFET technology node. Proposed system was connected to the transmitters input buffer, and the data transfer simulations for typical PVT corners were performed to make sure that the data does not corrupt.

The operational simulation results of the input (SDA) and output (TX_OUT) signal, when the power supply is turned on (vdd1v8 = 1.8 V) are presented in fig. 2. When the data transmission through SDA line begins and the TX_OUT starts to switch its values, the circuitry part of the proposed system is being cut from the bias net, and the supply vdd1v8 voltage is fed to the transmitter input buffer. Since the I2C bus is connected to the high voltage source, the data transfer process is going to be inversed, i.e. when the transmitted data is equal to logic 0 transmitter's input NMOS transistor is closed and the data on the line is equal to logic 1, and vice versa: when the transmitting data is equal to logic 1 the input NMOS transistor is open and the data on the voltage on the line equals to logic 0. The parasitic capacitance in the connected voltage control system is small and the I2C bus itself carries a high voltage, so the signal distortions created by the voltage control system are not significant.

SDA SCL

vddlv8

Fig. 1. Voltage controller circuit

Fig. 2. Operational simulation results of data transmission with power supply on

Fig. 3 shows the bias voltage value when the supply power is turned off (vdd1v8 = 0 V). When there is no data transfer through SDA and SCL, no voltage is applied to input buffer transistors drains, therefore the transistors are not under the stress and the bias voltage is 0 V. Once other devices start the data transfer process on I2C lines the bias voltage starts to form. For TT corner the voltage on the output of the proposed system varies from 1.76 to 1.8 V, depending on the number of pulled up data transmission lines.

SCL

M Ils)

SDA

M US)

vbias

X / 1,76V 1.8V

0 0 5u I Ou I5u 20 и 25u 30u 35U 40u 45u SOu 55u

Fig. 3. Bias voltage generation with power supply off

Simulation results for the typical cases for different voltages on the data lines are presented in table 1. According to PVT variations the lowest measured voltage was equal to 1.55 V and the highest measured value is 1.92 V, which is sufficient to keep the low voltage transistors out of overstress.

Table 1

Bias voltage values resulting from simulation

PVT corners Voltage on the data line, V

2.97 3.3 3.63

TT, 25 °C 1.62 1.76 1.92

FF, 125 °C 1.55 1.65 1.75

SS, -40 °C 1.59 1.74 1.90

Fig. 4 shows the transient processes on the Vbias net voltage value, when the power supply is turned off and then back on, i.e. vdd1v8 and enable switch from logic 0 (0 V) to 1.8 V. When the supply power is disabled (enable = 0), mp2 and mp3 transistors are opened, therefore the voltage divider section of the proposed system (R1-R2 resistors) generates a bias voltage equal to 1.76 V, which is sufficient to keep the transistor out of stress. After the supply voltage is turned on, during the transition time the voltage on the bias net rises to 2.8 V due to transient processes in the mp2 and mp3 transistors. Those processes last for ~1.7 ns which is not sufficient for the input buffer transistors to undertake stress.

To evaluate the transistors overstress, the aging simulations were performed using two models simultaneously: Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI). The results are shown in table 2.

о,-» (V) Ц»)

00. vdd1V8

/ (V) t(s) enable

£ 10 00.

/ (V) t(S) vbias

£ 20.

496n 498n SOOn 502n 504n

Fig. 4. Bias voltage during power up

Table 2

Transistor aging simulation results

Stress Drain-source AVth degrada- Drain-source current AVth degradation

conditions current tion, mV degradation using using VCS, mV

(10 years) degradation, % VCS, %

TT, 3.63 V, 8.46 65 0.64 4.9

-40 °C

SS, 3.63 V, 7.32 56.28 0.67 5.14

-40 °C

FF, 3.63 V, 7.18 55.23 0.63 4.8

-40 °C

TT, 3.63 V, 50 385 6.37 48

+125 °C

SS, 3.63 V, 49.05 377 7.10 54

+125 °C

FF, 3.63 V, 46.4 357 6.25 48

+125 °C

The comparison was performed between a system including the proposed circuit and a system not including it. Simulation results showed that for the worst case the drain-source current degradation and AVth degradation values are improved by ~87 %.

Conclusion. The voltage control method implemented in 14nm FinFET technology node is presented. The proposed system reduces transistor stress for the device's input buffer connected to the I2C bus, and allows using the system without any additional circuitry outside of the IC. The output of the proposed system was connected to input buffer bias transistor and the target voltage selected equal to the power supply voltage.

The most challenging part of the proposed system was to provide bias voltage for the IC input buffer when the power supply is turned off. For that purpose, the SDA/SCL lines have been selected as the voltage sources. When voltage on data lines changes by ±10 %, in typical case bias voltage fluctuations are equal to 16 %.

Proposed system reduces the drain-source current degradation and AVth degradation values by ~87 % and can be used in the modern data links to avoid transistors overstress in I2C systems, which makes it possible to improve final test performance and to lower yield loss.

References

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The article was submitted 16.03.2022; approved after reviewing 22.04.2022;

accepted for publication 04.05.2022.

Information about the author

Vazgen Sh. Melikyan - Corresponding Member of the National Academy of Sciences of the Republic of Armenia, Dr. Sci. (Eng.), Prof., Director of the Educational Department, "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), vazgenm@synopsys.com

Hrachya V. Gumroyan - PhD student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), gumroyan96@gmail.com

Davit S. Shaljyan - PhD student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Design Engineer of Analog and Mixed Signal Circuit, Sr. I, "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), shaljyan.davit@gmail.com

Donara V. Manucharyan - Lecturer, National Agrarian University of Armenia (Armenia, 0009, Yerevan, Teryan st., 74), mdon@yandex.ru

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