SKEW IMPROVEMENT METHOD FOR DIGITAL DELAY LINES Текст научной статьи по специальности «Электротехника, электронная техника, информационные технологии»

Original article yaK 621.382.049.77

doi:10.24151/1561-5405-2022-27-2-233-239

Skew improvement method for digital delay lines

H. T. Kostanyan

National Polytechnic University of Armenia, Yerevan, Armenia "Synopsys Armenia" CJSC, Yerevan, Armenia

hakobk@synopsys. com

Abstract. Nowadays, the clock skew problem became critical in integrated circuits operating in nonstandard conditions which means external conditions (voltage, temperature drifts) could be changed after calibration process. Data transfer speed reaches dozens of gigahertz, and even a minor skew of clock signal could bring to data loss. Therefore, design of delay lines with high robustness against process, temperature and voltage changes is important. In this work, the digital delay line (DDL) has been proposed that controls the current flowing through delay cells by changing gate-source voltages of transistors. Sensor cell was added to sense the delay variation of single inverter. XOR device detects the delay change of circuit by comparing input and output signal differences. Low pass filter and amplifier pair controls the current used for biasing voltage generation for delay cells. The simulation results of proposed DDL circuit have shown up to 56.04 % delay range improvement during temperature and voltage drifts, with 4.5 sigma Monte Carlo process variation coverage. The area of DDL circuit is increased by around 23.1 % due to added feedback loop.

Keywords, clock skew, digital delay line, temperature drift, voltage drift, IC performance

For citation. Kostanyan H. T. Skew improvement method for digital delay lines. Proc. Univ. Electronics, 2022, vol. 27, no. 2, pp. 233-239. doi. https://doi.org/10.24151/1561-5405-2022-27-2-233-239

© H. T. Kostanyan, 2022

Научная статья

Метод выравнивания отклонения сигнала для цифровых линий задержки

А. Т. Костанян

Национальный политехнический университет Армении, г. Ереван, Армения

ЗАО «Синопсис Армения», г. Ереван, Армения hakobk@synopsys. com

Аннотация. В настоящее время проблема отклонения тактового сигнала критична в ИС, работающих в нестандартных условиях. Это означает, что внешние условия (дрейф напряжения, температуры) могут быть изменены после калибровки. Скорость передачи данных достигает десятков гигагерц, и даже незначительное отклонение тактового сигнала может привести к потере данных. Поэтому конструкция линий задержки должна обеспечивать высокую устойчивость к изменениям процесса, температуры и напряжения. В работе предложена цифровая линия задержки, которая управляет током, протекающим через ячейки задержки, в результате изменения напряжения затвор-исток транзисторов. Для определения изменения задержки одиночного инвертора добавлена ячейка датчика. Показано, что устройство Исключающее ИЛИ обнаруживает изменение задержки схемы, сравнивая разности входного и выходного сигналов. Пара фильтр нижних частот - усилитель управляет током, который используется для генерации напряжения для ячеек задержки. Моделирование предложенной цифровой линии задержки схемы показало улучшение диапазона отклонения до 56,04 % при дрейфах температуры и напряжения с охватом вариаций процесса Монте-Карло 4,5 сигма. Площадь схемы цифровой линии задержки увеличена примерно на 23,1 % за счет добавления петли обратной связи.

Ключевые слова: отклонение тактового сигнала, цифровая линия задержки, температурный дрейф, дрейф напряжения, производительность ИС

Для цитирования: Костанян А. Т. Метод выравнивания отклонения сигнала для цифровых линий задержки // Изв. вузов. Электроника. 2022. Т. 27. № 2. С. 233239. doi: https://doi.org/10.24151/1561-5405-2022-27-2-233-239

Introduction. In recent years, IC performance reached up to dozens of gigahertz [1]. High performance is required to transmit, receive, and process big data during minimum possible timeframes with SerDes applications where a single line is used for parallel data transfers (transmission and reception) [2]. In parallel configuration, voltage for processor units and IC cores is reduced up to 0.75 V. In this situation every factor like a temperature shift, intrinsic noise, voltage spikes on the supply or others becomes a source of IC behavior changes [3] such as functionality, linearity, sensitivity or open loop gain of analog sensitive sections, delay or transition times of digital sections resulting in data transfer or recovery errors etc. [4]. Due to the risk of such changes clock skew problem has risen to a very high level of concern. Even a minor skew of clock signal could lead to data loss. This brings a challenge to design

data sampling, deskew and calibration methods which are less dependent on above mentioned impact factors.

In modern serial links, delay locked loops (DLL) and phase locked loops (PLL) are widely used to overcome the skew problem and synchronize the phase of a system [5]. The principle of operation of those systems is to match output clock with the reference clock signal by means of feedback loop [6]. Output clock signal could also be multiplied or shifted by corresponding phase regarding reference one. Such circuits in general are occupying big die area and consuming high power.

Another deskew method is simpler and contains only digital delay line (DDL). Serially connected delay cells are controlled by digital code [7, 8], as shown on fig. 1. Depending on clock skew and external conditions, after calibration process clock signal is centered regarding the data.

Fig. 1. Controllable delay cells [7, 8]

Considering that circuits could operate in nonstandard conditions, which means external conditions (voltage, temperature drifts) could be changed after calibration, this method loses its effectiveness. During temperature change from low to high transistor's threshold value decreases, which in turn brings higher current value in saturation mode. Delay of cells will decrease as the current becomes higher. Same results will be reached during supply value shift from low to high.

To test how the circuit functionality depends on external conditions a DLL circuit was designed by Synopsys Armenia Education Department (SAED) using 14nm FinFET technology [9]. HSPICE [10] simulations results after calibration of the circuit with account for process, voltage, temperature (PVT) variations are presented in table 1.

Table 1

PVT simulation results

Parameter Min Typical Max

Max delay step, UI 0.09 0.12 0.13

Min delay step, UI 0.029 0.03 0.06

Delay_range, UI 2.06 2.27 2.5

The IC's operating conditions' changes after circuit calibration have been tested: voltage and temperature drifts were applied to the circuit for the fixed code. ± 25, ± 50 and ± 100 °C temperature drifts were applied to typical operating temperature (25 °C). Supply voltage value was drifted by 0.8 V ± 30 mV. Results are presented in table 2.

Table 2

PVT simulation results with temperature and voltage drifts

Condition change Parameter Min Max

Temperature drift ± 25 °C Max delay step, UI 0.089 0.132

Min delay step, UI 0.029 0.061

Delay range, UI 2.05 2.52

± 50 °C Max delay step, UI 0.087 0.133

Min delay step, UI 0.028 0.063

Delay range, UI 2.0 2.55

± 100 °C Max delay step, UI 0.085 0.136

Min delay step, UI 0.026 0.067

Delay range, UI 1.91 2.59

Positive voltage drift Max delay step, UI 0.088 0.128

Min delay step, UI 0.027 0.058

Delay range, UI 1.68 2.67

Negative voltage drift Max delay step, UI 0.093 0.135

Min delay step, UI 0.033 0.065

Delay_range, UI 1.66 2.74

As shown in the table above, delay_step parameter values changed only a little. Since the delay cells have similar architecture, maximum and minimum values of delay changed similarly for all devices and the step remained the same. As the sum of all delay cells changed de-lay_range parameter was most affected with 0.61 UI change after negative voltage drift. Difference between maximum and minimum values of delay_range changed from 0.44 to 1.08 UI. Hence, circuit's functionality was affected during temperature and voltage changes.

Proposed DDL circuit. To solve the skew problem several modifications have been done in existing deskew calibration mechanisms. To sense the delay change, additional delay cell was added to the chain as a replica. This cell works as sensor helping to detect delay changes during conditions changes. To overcome delay variation an updated DDL circuit has been designed (fig. 2).

Fig. 2. Proposed circuit

Input and output of delay cell are connected to XOR cell which acts as phase detector between input and output signals. Low pass filter (LPF) works as integrator to detect delay changes during voltage / temperature drifts (fig. 3). The output of LPF is connected to operational transconductance amplifier (OTA) (fig. 4) that compensates delay change with decreasing / increasing current coming from current mirrors; LPF - OTA pair generates voltages for delay cells (fig. 5).

Fig. 3. XOR-LPF pair

Fig. 4. OTA schematic

Fig. 5. Control voltage generator circuit

The circuit responsible for control voltages for delay cells contains parallel connected current stages which are biased from compensated current. During startup of the circuit calibration mechanism is enabled and control bits are set to have appropriate control voltages for delay cells. During voltage / temperature drift transistor's Vth and Ids parameters may change causing current change and control voltages degradation from initial value. A negative feedback loop was used to overcome this issue.

Simulation results. To check stability and noise immunity for OTA, power supply rejection ratio (PSRR) and AC simulations were done. PVT simulation results for OTA are presented below:

Gain..........................................................61 dB

PSRR................................................ < - 32 dB

Phase margin......................................57 degree

Gain margin..........................................14.4 dB

Monte Carlo (MC) simulation results for worst corner are presented an fig. 6. Comparison with existing solution is presented in table 3.

Table 3

Delay range values obtained by various methods

Delay range

Condition change [6] [7] Proposed solution

Min Max Min Max Min Max

Nominal 2.06 2.5 2.01 2.8 2.28 2.58

Max thermal drift, UI 1.91 2.59 1.83 2.61 2.2 2.69

Positive voltage drift, UI 1.68 2.67 1.70 2.66 2.17 2.63

Negative voltage drift, UI 1.66 2.74 1.68 2.73 2.11 2.58

Conclusion. The proposed DDL circuit controls the current flowing through delay cells by changing gate-source voltages of transistors. Sensor cell was added to sense the delay variation of single inverter. XOR device detects the delay change of circuit by comparing input and output signal differences. LPF and amplifier pair controls the current which is used for biasing voltage generation for delay cells. The simulation of proposed DDL circuit has shown up to 56.04 % delay range improvement during temperature and voltage drifts (worst case: from 1.08 to 0.47 UI), with 4.5 sigma Monte Carlo process variation coverage. The area of DDL circuit had to be increased by around 23.1 % due to added feedback loop.

References

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2. Li L. IC challenges in 5G. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC). Xiamen, IEEE, 2015, pp. 1-4. doi: https://doi.org/10.1109/ASSCC.2015.7387430

Q-Q Plot [y=0.03047x+2.363]

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Fig. 6. MC simulation results: 1 - Gaussian fit; 2 - confidence interval; 3 - target sigma; ♦ - data

3. Abouda K., Besse P., Clairet M., El Sherif A., Hemon E., Lopez D., Moore D., Turpin P. How System Basis Chips rise to the power and reliability challenges for future-proof electrification and autonomous vehicle electronic control unit designs. 2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD). Nagoya, IEEE, 2021, pp. 17-22. doi: https://doi.org/10.23919/ISPSD50666.2021.9452239

4. Keow A. C., Negara M. A. Methodology to investigate the root cause of threshold voltage drift of transistor devices using capacitance voltage measurements. 2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA). Hangzhou, IEEE, 2019, pp. 1-4. doi: https://doi.org/ 10.1109/IPFA47161.2019.8984913

5. Razavi B. Design of Analog CMOS Integrated Circuits. 2nd ed. New York, McGraw-Hill, 2015. 782 p.

6. Yang C.-Y., Li M.-S., Chuang A.-J. A wide-range folded-tuned dual-DLL-based clock-deskewing circuit for core-to-core links. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 2021, vol. 29, iss. 5, pp. 883-894. doi: https://doi.org/10.1109/TVLSI.2021.3056506

7. Sourikopoulos I., Frappé A., Cathelin A., Clavier L., Kaiser A. A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI. ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference. Lausanne, IEEE, 2016, pp. 145-148. doi: https://doi.org/10.1109/ESSCIRC.2016.7598263

8. Antonov Y., Stadius K., Kosunen M., Ryynanen J. Open-loop all-digital delay line with on-chip calibration via self-equalizing delays. 2017 European Conference on Circuit Theory and Design (ECCTD). Catania, IEEE, 2017, pp. 1-4. doi: https://doi.org/10.1109/ECCTD.2017.8093344

9. Melikyan V., Martirosyan M., Melikyan A., Piliposyan G. 14nm Educational Design Kit: capabilities, deployment and future. Proceedings of the 7th Small Systems Simulation Symposium, 2018, February 12-14, Nis, Serbia. Nis, Faculty of Electronic Engineering, 2018, pp. 37-41.

10. HSPICEReference Manual. Synopsys Inc., 2017. 846 p.

The article was submitted 27.12.2021; approved after reviewing 27.12.2021;

accepted for publication 22.02.2022.

Information about the author

Hakob T. Kostanyan - student of National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan 105), Analog and Mixed Signal Circuit Design Engineer, Engr. II "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, A. Aharonyan st., 26), hakobk@synopsys.com

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