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13СХЕМОТЕХНИКА И ПРОЕКТИРОВАНИЕ CIRCUIT ENGINEERING AND DESIGN
Original article УДК 621.3.049.77:621.382.3 doi:10.24151/1561-5405-2023-28-3-351-359 EDN: UDMQWS
A method for minimizing aging influence on rail-to-rail operational amplifier with thin oxide transistors
V. Sh. Melikyan, S. A. Ghukasyan, S. S. Harutyunyan, G. A. Voskanyan, N. A. Asatryan
National Polytechnic University of Armenia, Yerevan, Armenia "Synopsys Armenia" CJSC, Yerevan, Armenia
ghukasya@synopsys. com
Abstract. In technological processes below 5 nm the semiconductor manufacturing companies face difficulties during fabrication of transistors with thick gate oxide. As supply voltages are not scaled respectively, it causes stress between transistor terminals, which leads to transistor aging degradation. In this work, a method is proposed for designing rail-to-rail operational amplifier with usage of only thin oxide transistors. Amplifier scheme was designed with "SAED 14nm" FinFET technology. As a result of using the proposed method the aging degradation has been reduced by protecting transistors from stress conditions. Based on the proposed design Ids variation is reduced from 22.4 to 3.9 % and threshold voltage Vth variation from 252 to 28 mV.
Keywords. CMOS, aging, stress, rail-to-rail, thin oxide transistor
Funding: the work has been supported by the Science Committee of the Republic of Armenia (project No. 21T-2B002).
For citation: Melikyan V. Sh., Ghukasyan S. A., Harutyunyan S. S., Voskanyan G. A., Asatryan N. A. A method for minimizing aging influence on rail-to-rail operational amplifier with thin oxide transistors. Proc. Univ. Electronics, 2023, vol. 28, no. 3, pp. 351-359. https://doi.org/ 10.24151/1561-5405-2023-28-3-351-359. - EDN: UDMQWS.
© V. Sh. Melikyan, S. A. Ghukasyan, S. S. Harutyunyan, G. A. Voskanyan, N. A. Asatryan, 2023
Научная статья
Метод минимизации влияния старения на rail-to-rail операционный усилитель с тонкими оксидными транзисторами
В. Ш. Меликян, С. А. Гукасян, С. С. Арутюнян, Г. А. Восканян, Н. А. Асатрян
Национальный политехнический университет Армении, г. Ереван, Армения
ЗАО «Синопсис Армения», г. Ереван, Армения ghukasya@synopsys. com
Аннотация. В технологических процессах менее 5 нм компании-производители полупроводников сталкиваются с трудностями при изготовлении транзисторов с толстым оксидом подзатвора. Поскольку напряжения питания не масштабируются соответствующим образом, это вызывает стресс между клеммами транзистора, что приводит к старению транзистора. В работе предложен метод проектирования rail-to-rail операционного усилителя с использованием только тонких оксидных транзисторов. Схема усилителя разработана с использованием 14 нм FinFET технологии SAED. В результате применения метода деградация из-за старения снижена за счет защиты транзисторов от стрессовых условий. На основе предложенной конструкции уменьшены разброс тока Ids с 22,4 до 3,9 % и разброс порогового напряжения Vth с 252 до 28 мВ.
Ключевые слова: КМОП, старение, стресс, rail-to-rail, тонкий оксидный транзистор
Финансирование работы: работа выполнена при финансовой поддержке Комитета по науке Республики Армения (проект № 21T-2B002).
Для цитирования: Метод минимизации влияния старения на rail-to-rail операционный усилитель с тонкими оксидными транзисторами / В. Ш. Меликян, С. А. Гукасян, С. С. Арутюнян и др. // Изв. вузов. Электроника. 2023. Т. 28. № 3. С. 351-359. https://doi.org/10.24151/1561-5405-2023-28-3-351-359. - EDN: UDMQWS.
Introduction. As the transistor's sizes grow smaller during technological progress, many undesirable phenomena have arisen, damaging the reliability of integrated circuits (ICs), thus additional accuracy during design process is needed [1]. One of phenomena leading to the shortening of the blocks life span is aging [2]. Three major aging effects are:
- Hot Carrier Injection (HCI), when particles with kinetic energy under high electric field are injected into gate oxide region and trapped, which leads to a shift in threshold voltage Vth (fig. 1) [3];
- Bias Temperature Instability (BTI), when Vth and Ids shift after a negative bias for PMOS (NBTI) and positive bias for NMOS (PBTI) is applied at elevated temperatures; some portion of degradation recovers after the stress is removed (fig. 2) [4];
Fig. 2. Stress and recovery phases during circuit's lifetime
- Time-Dependent Dielectric Breakdown (TDDB), a process unfolding gradually: at first, soft breakdown (BD) occurs, then, during dielectric wearout, gate leakage increases and signal swing and cell timing are reduced, and finally, hard BD takes place, when trap induced conduction channel is formed and widened, which leads to exponential increase of leakage (fig. 3) [5].
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о M) га
сз о -J
о
НягН Rn
® ® 4 m
Time to soft BD Wearout time /Catastrophic failure
jTFLrxFiir-
Time Soft BD
Gate: Polysilicon Gate: Polysilicon Gate: Polysilicon
0 0
0
0
0 <f>0 0 Шр
0 \ 0 n
Substrate
Substrate b
Substrate
Fig. 3. Illustration of TDDB effect: a - process stages; b - trap induced conduction channel formation
The power supply units of PCs and other devices incorporate multiple DC power supplies. A power supply line provided by a power supply unit is referred to as a power rail. The entire range from the maximum voltage of a power line (VDDH) to its minimum voltage (GND) is referred to as rail-to-rail. Operational amplifiers having a common-mode input voltage range that almost covers the GND-to-VDDH range at input and output are called rail-to-rail operational amplifiers (or full-swing). Rail-to-rail operational amplifiers make it possible to operate at lower supply voltages, swing closer to the rails, and provide wider dynamic range [6]. Below are presented the schematic view (fig. 4) and HSPICE simulation results (fig. 5, 6) of the rail-to-rail operational amplifier designed by "SAED 14nm" FinFET technology [7, 8] using "Custom compiler" tool [9].
Fig. 4. Schematic view of rail-to-rail operational amplifier
50db 40db 30db 20db 10db
Odb
(db20)
100
1k
10k 100k 1M
ЮМ 100M
Fig. 5. AC characteristic of designed rail-to-rail operational amplifier
Such structures are in routine use in the input receiver inside auxiliary ports (AUX). AUX is a type of standard communications port on a device that accommodates audio signals for: MP3 players, headphones and headsets, microphones, speakers, and other audio devices. They are also used inside digital delay lines (DDL) in charge pumps and in voltage and/or temperature drift compensation circuits.
340m 320m 0.3 280m 260m (lln)
340m 320m 0.3 280m 260m (lin)
1 0.8 0.6 0.4 0.2
(Km)
0 lu 2u 3u 4u 5u
Fig. 6. Transient simulation results of designed rail-to-rail operational amplifier
Problem description. Nowadays semiconductor manufacturing companies are facing difficulties when fabricating transistors with thick gate oxide in some technological processes below 5 nm, hence the necessity to replace all thick oxide devices with thin oxide devices, thereby causing difficulties at the design stages [10]. So far operational amplifiers are designed with thick oxide devices, and their replacement with thin oxide can cause stress, because of high supply voltages. Stress conditions between two terminals of thin oxide transistor are lower than for thick oxide transistor. All thin oxide transistors are designed and fabricated to have maximum voltage difference between terminals (gate-drain VGD, gate-source VGS, drain-source VDS) equal to low supply voltage, and using them in high supply voltage analog blocks can cause stress on those devices [11], which will lead to enhanced aging degradation. One of the ways to solve this problem is to make the devices work under non-stress conditions [12].
Generally, to explore the deterioration of the rail-to-rail operational amplifier parameters due to aging degradation, aging simulation is used. This simulation captures the effect of degradation of transistors over time. Semiconductor manufacturing companies are providing their own aging models accurately describing the degradation of devices during lifetime.
For exploration of aging degradation of the designed rail-to-rail operational amplifier the SPICE simulations for 10 years have been performed for two operating modes: normal operation and power down. In normal operation mode some aging degradation was detected on the main devices, but without dramatic change of main parameters. To enter circuit to the power down mode the following modifications have been performed (fig. 7): added P1, P2, P3, P4, P5 and P6 transistors (indicated by dashed line). The P1, P2, P3, P4, P5 and P6 transistors cut all the paths for the current flow. In power down mode aging degradations were observed for more main devices and all power down devices, which leads to the reduction of DC gain approximately by 12 dB. Simulation results for devices that demonstrated significant Vth and Ids shifts in normal operation and power down modes after 10 years aging are presented in table 1. In normal operation mode the degradation of M1 and M2 input devices is due their drains reaching to VDDH, and gates near 300 mV, which causes stress. The drain of M10 that is the output of the amplifier can reach to VDDH and gate can be closed to 200 mV, which leads to stress. In power down mode M5 and M6 devices are under the same conditions
Fig. 7. Schematic view of rail-to-rail operational amplifier after adding power down devices (Table 1
Vth and Ids variation for most degraded devices for rail-to-rail operational amplifier
- -)
Transistor name Normal operation mode Power down mode
Д Vth, mV Mds, % ДVth, mV Mdls, %
M1, M2 119 15.2 26 4.1
M5, M6 25 3.8 178 18.5
M10 109 14.6 0.1 0.1
M13, M14 31 4.5 182 19.3
P1, P2, P3 0.1 0.1 252 22.4
P4, P5, P6 0.1 0.1 252 22.4
and are operating in off mode because P6 drives gates of M5 and M6 to 0, and P1 drives M5 drain and P3 drives M6 drain to VDDH, so VGD for both is VDDH. M13 device is in off mode, P3 drives M13 gate to VDDH, P4 drives M13 source to 0, drain is floating and can reach to VDDH. Same for M14. The P1, P2 and P3 power down devices should be open, and their control signal is 0, so VGS and VGD is VDDH. The gates of P4, P5 and P6 devices are connected to VDDH level signal, thus VGS and VGD is VDDH.
Obtained results demonstrated the problems' manifestation in both normal and power down modes.
Proposed solution. To solve the stress-induced problems that have arisen, the following changes (indicated by dash-dot line) have been implemented in the amplifier (fig. 8.):
- the power down enable signal separated for NMOS and PMOS devices; additionally, their logic 0 and logic 1 domains changed using multi output level converter (from 0 to vnbias for NMOS and from vpbias to VDDH for PMOS) [12];
VDDH
Fig. 8. Schematic view of rail-to-rail operational amplifier after modifications (-----)
- cascading method used by adding D1, D2, D3, D4, D5 and D6 devices [11];
- T1 transmission gate added to cut the pbias1 and pbias2 nets when amplifier is in power down mode;
- P3 PMOS device replaced with NMOS device and source changed from VDDH to vpbias;
- P7 and P8 devices added to drive x1 and x2 nets to vpbias in power down mode.
Generally, cascode transistors gate receives bias voltage that limits source voltage of
NMOS below bias voltage and source voltage of PMOS above bias voltage, otherwise transistors will be closed. Correctly chosen bias voltage value for cascode devices will bring desirable effect: no stress in the circuit. The vnbias and vpbias values could be generated using voltage dividers or bandgap reference, with proper matching techniques in layout the voltage should not vary by more than 5 %. The *_nb and *_pb signals are also for protecting devices from stress, they can be applied from multi output level converters. For *_pb signal low level is vpbias and high level is VDDH, and for *_nb signal it is 0 and vnbias, respectively. With these methods the devices will be under working conditions defined by factories (no stress) and will have much longer lifetime.
The D1 transistor will prevent M5 device from stress, D2 and D3 will protect M1 and M2 correspondingly. D4 and D5 will protect M3 and M4, when input common mode is high, although in simulation under study there was no such scenario. D6 will protect M10. P3 device will drive gates of M13 and M14 devices to vpbias, meanwhile P7 will drive M13 source and P8 will drive M14 source to vpbias. Thus, they will be closed and not liable to stress. M6 drain will reach to vpbias, therefore no stress conditions. Using T1 transmission gate to cut pbias1 from terminal of R1 is necessary to prevent an undesirable effect. Otherwise, one terminal of R1 device is connected to vpbias and another terminal is connected to VDDH, which leads to constant current through R1 resistor. This in turn will bring unnecessary power con-
sumption. Aging simulations performed after those modifications have demonstrated that problems are solved: there are no changes in main parameters, no significant degradation neither in normal mode nor in power down mode (table 2). The changes in parameters of the designed rail-to-rail operational amplifier before and after proposed design updates, with 10 years aging simulation, are summarized in table 3.
Table 2
Vth and Ifc variation for rail-to-rail operational amplifier after modifications
Transistor name Normal operation mode Power down mode
Д Vth, mV Д/s, % Д Vth, mV Д/s, %
M1, M2 21 3.5 8 1.4
M5, M6 22 3.6 0.1 0.1
M10 18 2.7 0.1 0.1
M13, M14 28 3.9 0.1 0.1
P1, P2, P3 0.1 0.1 15 2.1
P4, P5, P6 0.1 0.1 15 2.1
Table 3
Simulation results for unmodified and proposed designs of rail-to-rail operational amplifier
Parameter Before modifications After modifications
DC gain, dB 40.1 52.3
Д Vth, mV 252 28
Д/ds, % 22.4 3.9
Conclusion. New schematic solutions have been implemented to prevent stress conditions influence on devices. It has been demonstrated that proposed design updates improve the variation of Ids and Vth parameters caused by aging degradation in 10 years lifetime, thus neutralizing the reduction in amplification factor.
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The article was submitted 12.01.2023; approved after reviewing 26.01.2023;
accepted for publication 30.03.2023.
Information about the authors
Vazgen Sh. Melikyan - Corresponding Member of the National Academy of Sciences of the Republic of Armenia, Dr. Sci. (Eng.), Prof., Head of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Director of the University Programs "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), vazgenm@synopsys.com
Sevak A. Ghukasyan - PhD student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Design Engineer of Analog and Mixed Signal Circuit, Senior Eng., "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), ghukasya@synopsys.com
Sergo S. Harutyunyan - PhD student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Design Engineer of Analog and Mixed Signal Circuit, Eng. II, "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), sergo@synopsys.com
Garnik A. Voskanyan - PhD student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Design Engineer of Analog and Mixed Signal Circuit, Senior Eng., "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), garnikv@synopsys.com
Narek A. Asatryan - Master's degree student of the Microelectronic Circuits and Systems Department, National Polytechnic University of Armenia (Armenia, 0009, Yerevan, Teryan st., 105), Design Engineer of Analog and Mixed Signal Circuit, Eng. I, "Synopsys Armenia" CJSC (Armenia, 0026, Yerevan, Arshakunyats ave., 41), anarek@synopsys.com
