CC BY
49
https ://doi.org/10.29013/AJT-19-9.10-40-43
Timoshkin Andrey Ivanovich, candidate of physical and mathematical sciences, assistant professor
National Metallurgical Academy of Ukraine
Ukraine, Dnepr E-mail: timoshkin1964@gmail.com
TESTABLE LOGICAL CIRCUIT OF A BINARY NONRESTORING ARRAY DIVIDER
Abstract. In the information processing systems LSI with regular structure (adders, substractors, array multipliers, array dividers and so on) perform increasable part. A testable functional-logical circuit of a binary nonrestoring array divider has been elaborated. The circuit being represented possesses a fault detection test of the length of three and a small hardware complexity.
Keywords: logical circuits with regular structure, stuck-at fault, fault detection test.
It is easier to design testable digital integrated where a and b are the values of the original 1-bit
circuits with a regular structure, including adders, multipliers, substractors, dividers, and various memory circuits, than integrated circuits with an irregular structure. The article [1] presents a testable functional-logical circuit of a binary nonrestoring array divider with a fault detection test with a sequence length 4 or 5 for single stuck-at faults. However, its implementation requires a significant amount of hardware resources, which is a major flaw. This article proposes a testable functional-logical circuit of a binary nonrestoring array divider with a fault detection test with a sequence length 3 of the same fault class and with less hardware complexity.
Layers of 1-bit adders combined within each layer into parallel adder with sequential carry are the basis of this circuit. At the same time, the construction of a testable 1-bit adder circuit that underlies the multi-bit adder ofeach layer is based on the representation ofthe sum S and carry P functions ofa full 1-bit adder as polynomials dual to the Zhegalkin polynomials [2, P. 24] (since the sum S and carry P functions are self-dual) and also on the fact that these polynomials for sum S and carry P functions of a 1-bit adder are simple: P-{avb) ©(a v p)Q(bv p),
S = aObOp, (1)
operands; p and P are the values of the input and output carry signals, respectively, S is the value of the sum signal, v is the symbol of the disjunction operation, G is the symbol of the biconditional operation (equivalence).
The formula for the carry function P from (1) can easily be converted to convenient form: P = (a v b) [p v(a b)] = (a v b) [p v (a b)]. (2)
Then the testable logical circuit of the 1-bit adder can be implemented in a logical basis consisting of NOR and EQUIVALENCE two-input gates. This diagram is shown in (Fig. 1). At the same time, a rather simple schematic diagram of EQUIVALENCE gate on MOS transistors, containing only 3 transistors [3, P. 196], is known. This scheme is shown in (Fig. 2). The fault detection test for the 1-bit adder circuits in the selected basis for all single stuck-at faults contains 3 vectors and is described in table shown in (Fig. 1).
The testable n-bit (n is a positive integer) circuit of the binary adder of each layer of the nonrestoring array divider is composed of n testable circuits of a full 1-bit adder connected in a regular manner, i.e. by connecting the carry output of i-th circuit with the carry input of (i+1)-th circuit, where 1 < i < n -1.
This circuit diagram is shown in (Fig. 3). A fault de- for all its single stuck-at faults is conducted by simply tection test for a testable circuit of n-bit binary adder iterating the test shown in (Fig. 1).
p a b S P
1 0 0 1 1 0
2 0 0 0 0 0
3 1 1 0 0 1
Figure 1. Testable 1-bit adder circuit and its fault detection test
Figure 2. Schematic of EQUIVALENCE gate in MOS transistors
pi b a b a2 b a3 Si S2 S3
0 1 0 1 0 1 0 1 1 1
0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 0 0
Figure 3. Testable n-bit adder circuit and its fault detection test
u Qe D1 D2 D3 d4 N1 N2 N3 N4 N5 N6 N7 Q, Q2 Q3 Q4 R1 R, R4 R5 R6 R7
1 0 1 1 1 1 1 1 1 1 1 1 1 1 e e e e 1 1 1 1 1 1 1
2 1 0 e e e e e e e e e e e e e e e e e e e e e e
3 1 1 e e e e e e e e e e e 1 1 1 1 e e e e e e e
Figure 4. Testable circuit of 4 x 4-bit nonrestoring array divider and its fault detection test
The testable functional-logical circuit of the n = 4 is shown in (Fig. 4). In Fig. 4 nonrestoring n x n bit array divider for array with (N1,N2,N3,N4,N5,N6,N7) and (D1,D2,D3,D4)
represent the dividend and the divisor, respectively. N1 and D1 are the respective sign bits. (Q1,Q2,Q3,Q4) are the quotient bits. (R1,R2,R3,R4,R5,R6,R7) are the remainder bits. The value of Qi _1 determines whether subtraction or addition should be performed in the ith row. Since the initial subtraction must always be carried out, Q0 = 1. The considered circuit contains seven additional two-input EQUIVALENCE gates and one additional input u. In this case, in the operating mode, the logical (1) signal is fed to the input u. The fault detection test for all single stuck-at faults of this circuit contains 3 vectors and is described in table shown in (Fig. 4).
The fault-detection test for the general case also contains 3 vectors and is constructed as follows:
- the sequence 1,0,0 (j e {1,2,...,n}) is fed to each D. input;
- the sequence 1,0,0 (i e {1,2,...,2n -1}) is fed to each Ni input;
- the sequence 1,0,1 is fed to Q0 input, and the sequence 0,1,1 is fed to u input.
It is easily seen that in general the testable n x n bit nonrestoring array divider contains 2n-1 additional two-input EQUIVALENCE gates. The testable circuit found in [1] requires significantly bigger amount of hardware resources for its implementation than the proposed testable circuit.
References:
1. Qiao Tong, Niraj K. Jha. Design of C-testable DCVS Binary Array Dividers // IEEE Journal of SolidState Circuits,- Vol. 26.- No. 2.- February 1991.- P. 134-141.
2. Яблонский С. В. Введение в дискретную математику.- М.: «Наука». Гл. ред. физ.-мат. лит. 1986.384 с.
3. Мурога С. Системное проектирование сверхбольших интегральных схем. Кн. 1.- М.: Мир, 1985.288 с.
