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ON DESIGNING OF TESTABLE DIGITAL COMBINATIONAL CIRCUITS
ROMANKEVICHA., GROL V., RIDA AL SHBUL
National technical university of Ukraine “KPI”
E-mail: romankev@scs.ntu-kpi.kiev.ua
Abstract. Method of easy-to-test combinational digital devices construction that based on using of elements with variable logical functions had been offered. The method is oriented on procedures of probabilistic (pseudorandom) testing being combined with signature analysis and it is characterized by reduction of pseudorandom test sequence length.
1. Introduction
control points for reading of diagnostic information during testing. In this case it is supposed that basic combinational structure is represented by some Boolean function in one of perfect (disjunctive or conjunctive) normal forms that is of PDNF or PCNF.
3. General logical element
Representation of initial combination structure by the PDNF or PCNF determine elements’ base function set, that is functions AND, OR, NOT. It is proposed to use a probability characteristics of XOR element for increasing of a circuit’s testability degree, namely: a fact of stabilizing of such element’s output probability on 0.5 level under condition even if only to one of element’s input a binary sequence of equal probability independent signals is applied [5]. For implementation of basic logical element a descriptions of non-equivalence element (XOR) or correspondingly an equivalence element are selected:
fxOR = (x v y) • (x v y) = (x • y) v (x • y),
Organization of effective procedures to test logical structures is obtaining more importance with increasing of the structure complexity. Moreover labor expenditures to solve this problem are increasing. Sometimes labor expenditures accompany with unacceptable cost. So designing of deterministic tests [1,2] aimed on detection of specified class faults (usually it’s a single constant faults on inputs or outputs of logic elements) needs a multiple implementation of simulation procedure for finding of test pattern sets in deterministic test sequence. Using as testing a pseudorandom sequences [3] quite decreases an expenses for testing sequence synthesis and leads to decreasing of both algorithmic and hardware complexity of control testing device. However, significant dimension of testing sequence is a fundamental limitation of pseudorandom testing method. For example, test’s length Tk of pseudoexhaustive testing of n-input combinational circuit is determined by the value of n and preset value of Pt - a probability of the circuit total testing on an interval of Tk (so ifn=20 and Pt=0.99 a value of Tks2-107 cycles). A prospective direction in digital devices’ technical diagnostics is a development of designing of testable (easy-to-test) circuits methods [5], which are based on insertion of some redundancy into basic structure during its designing in order to decrease a cost of following test procedures. Paper [6] shows a method that suggests a decomposition of initial circuit on a set of subcircuits. It leads to necessity in preliminary analysis of tested object’s topology, it means that it needs a detail information about structure if an initial device. General limitation of the methods is a significant number of additional control points and this number will be increased essentially under decreasing of complexity of sub circuits or correspondingly under increasing ofa number of sub circuits on which an initial complex digital structure had been decomposed during test procedure.
2. Essence of problem
Problem of digital combinational circuits synthesis, thai differ by an higher degree of testability during testing with using pseudorandom test signals of equal probability is presented and enough actual. Object of work is increasing efficiency ofpseudorandom diagnostic procedures for digital circuits that depends on decreasing of time expenses for tesi control procedures and also on reduction of the number o1
XOR
= (x • y) v (x • y) = (x v y) • (x v y).
Fig. 1
Basic logical element is implemented by modification of nonequivalence elements. (XOR) as insertion additional control input C (as it’s shown on fig. 1).
Obviously, that logic circuit on fig. 1a is functioning in conformity with next conditions:
J(c = 0) ^ (z = x ® y),
[(c = 1) ^ (z = x v y), (1)
and for circuit fig. 1,b. these conditions are:
J(c = 0) ^ (z = x ® y),
{(c = 1) ^ (z = x • y). (2)
In that way in dependence on a state of input C a logic node realizes a XOR-functionunder C=0 and OR-function (fig. 1,a) or NAND (fig. 1 ,b) under C= 1.
Similarly it is possibly to modify an equivalence element (fig-2).
Fig. 2
b
a
b
a
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(c = 0) ^ (z = x © y), (c = 1) ^ (z = x • y)
(3)
Modifications for the circuit on fig.2,b are:
J(c = 0) ^ (z = x v y),
|(c = 1) ^ (z = x© y). (4)
Unit on fig. 2 implements a set of AND, NOR and XOR functions. As result, units on fig. 1 and fig.2 implement a Boolean expressions system that own functional fullness, which allows implementing of such functions’ representations as PDNF and PSNF. Control input C is being used for assigning of a unit’s operative mode: C=0( 1) assigns a testing mode for circuit onfig. 1 (2), C=1(0) determine a unit’s work on fig.1(2) in system (operative) mode.
4. Testability ofbasic element
Let’s observe the structure on fig. 2,a for evaluation of basic element’s testability (the structure is chosen arbitrarily, procedure of testability’s estimation of other three possible configurations of on fig. 1 and fig.2,b could be carried out in the
C X Y Z Faults being detected
1 0 0 1 8(0), 6(0), 2(0), 1(1),
1 0 1 0 8(1), 6(1), 7(1), 5(1), 3(0)
1 1 0 0 8(1), 6(1), 7(1), 4(1), 1(0)
1 1 1 0 8(0), 7(0), 4(0), 5(0)
0 0 0 0 8(1), 6(1), 7(1), 2(1)
0 0 1 0 8(1), 6(1), 7(1), 5(1)
0 1 0 0 8(1), 6(1), 7(1), 4(1)
0 1 1 1 8(0), 7(0), 4(0), 5(0)
same way). In the table a unit’s input patterns are included and in right column the circuit poles’ faults are represented. These faults are in form of changing of the unit’s output conditions on corresponding input pattern (a characters of i(0), i(1) are faults of constant “0” or constant “1” for node i= 1,2,.,8).
Data analysis on the faults being detected shows that in test mode (C = 1, z = x© y) an arbitrary pole’s faults of basic element are showed on Z output even if on one pattern. Exclusion is the only input controlling signal C, which fault of “2(1)” is showed only in system (operational) mode of the element. For detection of the fault a special procedure to carry out a testing of such testable combinational circuit will be described lower. If to take into account that 6(0)=7(0)=8(0), 6(1)=1(0)=3 (0), and also 7( 1 )=4(1)=5(1), then basic element will be represented as a circuit on fig. 3.
Also it can be noted additionally that:
(x=0) ^ (<11> ^ <01>),
(x = 1) ^ (<01> ^ <11>),
(y = 0) ^ (<11> ^ <10>),
(y = 1) ^ (<10> ^ <11>),
where <aia2> ^ <bib2> means the same reaction of fault circuit on the <a1a2> pattern and reaction of fault circuit on
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the <b1b2> pattern, a1, a2, b1, b2 e {0,1}. Therefore a basic functional element (BFE) can be described as three-input combinational unit (fig.4), where it’s all internal faults show themselves on Z output in test mode under conditions that comolete set of input patterns is applied to X and Y nodes.
Fig. 3
Fig. 4
5. Pyramid structure testing
As it’s stated above, in correspondence with conditions (1), (2), (3) and (4) BFE in test mode (C=0 for conditions (1) and (2), and C=1 for conditions (3) and (4)) implements a XOR element’s function (or its inversion). Let’s observe a connecting circuit of BFEs as it is on fig.5, which is a well-known multi-input wrap modulo 2 circuit.
Fig. 5
If as input sequence a pseudorandom sequence of n-bit binary patterns of equal probability is in use, then it can show that on all internal points of a circuit (and on its output)
S1 S, Sj Sr
Fig. 6
independent sequences of equal probability binary signals will be present. Really let’s extract a chain of elements from pyramid structure (fig. 6). It is accepted that it is nothing known about probabilistic characteristics of input signals (these signals are formed on outputs of other BFEs of a pyramid structure).
Known a priori is only a fact of input xi’s signals equal probability and these signals are being formed on the outputs of external control apparatus. The device in simplest case is apseudorandom pattern generator PRPG [3] and its parameters determine a signal’s parameters of input xi. In test mode each BFE implements XOR function (or its inversion). Then probability P(a) of “one” signal in a point is:
P(a)=P(Si)-[1 - P(xi)] + P(xi)[1- P(S1)].
But because P(xi)=0.5, then P(a)=0.5. Likewise for node b:
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P(b)=P(a)-[1 - P(S2)]+P(S2)[1 - P(a)].
It’s easy to determine that P(b)=0.5 and is independent from probability of signals on S2 output, P(c)=...=P(d)=0.5
independently from signals’ nature on S3,..,Sr outputs.
Thereby, if a sequence of equal probability n-bit patterns are applied from external PRP G to inputs of the circuit (fig. 5) than each BFE will obtain all possible two-bit input patterns with probability of 0.25 for every single one of the patterns. If to guess that arbitrary BFE will be switched incorrectly as result of single stuck-at failure, then on this clock given error shows itself on output ofpyramidal structure. Thereby, ifa signature analyzer is attached to circuit input then the errors would be detected during working of all BFEs of testable combinational structure.
6. Control circuit testing
As it follows from table all possible faults of a BFE ’ s components show themselves on BFE output if on the one of four possible input patterns through a testing (thereby and on a pyramidal circuit’s output under pseudorandom test, as it was noted previously). Control input C is an exclusion for its testing it is needed to switch a BFE in an operational (system) mode. However, a switching all pyramidal circuit in operational mode can in much degree to decrease a probability of supplying of all test patterns on elements’ inputs for some elements and also can decrease a probability of surveillance of caused by fault error on a circuit output. Sequential switching of all BFEs in an operative (system) mode only for one level is proposed to solve a problem ofBFE control inputs testing. All other BFEs should be switched intest mode. This procedure shouldbe implemented for BFEs of all levels. Let’s assume that an elements of level i
(i=1,2,..., log2n) implement mainsystemfunctionfor instance,
OR (condition (3)), and all other log2n -1 levels - an equivalence function(fig. 7). In such configuration an equivalence elements
of“lowef'’ levels 1,2,.,i-1 serve to generate anequal probability
2-bit independent patterns on inputs of AND-elements (BFEs are in operative (system) mode). BFEs of “higher" levels are to convey an output signals of i - level on circuit output f, which is a single controlpoint. Consequently if all elements are being switched in operational (system) mode sequentially (from first tier to log2ntier) then all BFEs will be tested fully including and control inputs C. The question about test duration for every single level being in operational (system) mode needs some detailed observation. For probabilistic testing of every single two-input element of concrete i - level needs T2 clocks for supplying of equal probability 2-bit patterns, moreover as it is showed at paper [5]:
T ^ ln(1 - ^Pe)
12 ^--------------
2 ln 0.75
(5)
X1 x2 x„
Fig. 7
levdh; i+1, i+2J....log?nJ C=1
Level j, C=Q
Levels 2........i-1, C=1
where: Pe - an assigned probability of exhaustive testing of any 2-bit input element.
With above mentioned, length of testing Tn of pyramidal n-input structure can be found as:
Tn ^ T2 x log 2 n .
Possible solution for switching of pyramidal circuit’s control inputs C is represented by fig. 8. Waveform diagram is onfig. 9.
C-input, level 1 C-input, level 2
C-input,
System ---------
mode ______________________
Test _________|""|_______________
Shift______________n_TL_J"L
1 2
Fig. 9
7. Testable implementation of perfect normal forms
Pyramidal structure that is shown on fig.5 suggests an absence of branching points not only on circuit elements’
outputs, but also on xi inputs (i=1,2,.,n) of input variables.
In the realization of perfect normal form circuits it could be possible to select a circuit of constituent generation CC (constituents of ones for PDNF and constituents of zeroes for PCNF), as it is shown on fig. 10. Subsequently, a combining circuit CoC represents OR element (PDNF) or AND element (PCNF) of N-outputs each, N- the number of constituents in the record of function. It’s obviously, that all structure’s components on fig.10 can be realized as pyramidal connection of two-input elements (as the elements a BFEs of related topology can be used). From structure configuration on fig. 10 follows that the circuit includes a branch points on level of input variables only. Organization of input variables inversion for k - kn circuits can be variable. Para-phased applying of signals x1 -xn (as it is shown on fig. 11) increases testability parameters of the structure. There are two circuits
ofkj andkj+j, i = 1,3,., N-1, under evenvalue ofN onfig.11.
Moreover circuit k selects input pattern aj and circuit k;+i selects input pattern ak in operational (system) mode
(j ,k=0,1,2,.,2n-1). Logic element LE CoC is a component of
pyramidal combining circuit. Pattern of aj can be represented as aj =< x^2...xn >, and for circuit on fig. 11: aj =< 1x2...xn_10 > , correspondingly for ak pattern: ak =<X1x2...xn > , and for circuit on figure 11 ak =< 1X2-Xn -11 >.
It’s obviously that for random choice of j and k couple of indexes next condition is true: |aj © ak 0. It means that
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Fig. 10
any two patterns that determine an active state for circuit of corresponding constituent realization (state of one for PDNF and zero state for PCNF) differ by inversion if only in the one
Testable realization of the constituents for perfect normal forms assumes using of BFEs, thus each circuit of CC is a n-input wrap modulo 2 circuit in test mode. Equal probability of all 2n output test patterns leads to situation when probability of signals on all N inputs of CC will be 0.5 (for circuit on fig. 11 P(a)=P(b)=0.5, where P(a), P(b) is signal probabilities on outputs of circuits k and k1+1 correspondingly). However existence ofbranch points on x1 -xn inputs affects a dependence of output states of CoC’s elements (LE of CoC on fig. 11). Really, if to observe the expression:
R = (|< a1~2...an > © < b1b2 ...bn >|) mod 2,
then obviously that Re {0,1}, furthermore R=0 corresponds to even the number of co-inverse bits in these aj and ak patterns, and R=1 corresponds to uneven the number of coinverse bits in these patterns (ai, bi e {1,0}, i = 1, 2, ... n - are a states of corresponding inputs of ki and ki+1 circuits under para-phased applying of input variables x1-xn). Then:
(R = 0) ^
a = b = 0 for even weight input patterns, a = b = 1 for uneven weight input patterns
and also:(R = 1) ^ {a = b for any input patterns, for example, a=0, b=1 for even patterns and a= 1, b=0 for uneven ones}.
Thereby, combining CoC circuit’s elements don’t get all possible test patterns in test mode, due to statistic dependence in input signals of CC’s components. To solve this problem next option (fig. 12) of applying of input variables for logical CC block had been proposed (such approach to guarantee a statistic independence of dependent signals is reviewed in paper [4]). In case of applying ofindependent pseudorandom sequences of equal probability binary signals from external PRPG of diagnostic system to inputs of Pr the sequences in points 1 and 2 will have a statistic independence (in the same way for x2, x3,., xn variables) that guarantees a testing of CoC’s input elements because trueness of inequality (6). Signals on all outputs of CC’s components also will have a static independence (of course, in test model.
To inputs of CC
Fig. 12
8. A combining circuit structure
CoC should realize an OR function (PDNF) or AND function (PCNF) in the operational mode and could be constructed as pyramidal circuit on the basis of BFEs. It’s obviously that in this case there is a need in testing of a control inputs C. It leads to increasing of circuit’s check procedures length as whole, because test time Tr is being derived as:
Tr > T2 (log 2 n + log 2 N^
and moreover Tr is time of two-input element’s exhaustive testing and can be find from expression (5), log2n is the number of layers in CC unit, log2N is the number of layers in the unit CoC. But because the weight Q of binary vector on N outputs of constituent production circuitbelongs to {0,1} set in system mode (if a function is conformed either to PDNF description or to PCNF description with accuracy up to inversion of CC outputs), then CoC canbe realized as n-output wrap on modulo 2 only on the basis of XOR elements without using of BFE configuration. In this case general structure of testable digital circuit, that realize some Booleanfunction, whichis represented by PDNF (PCNF) description, may be constructed as it is on fig. 13. At this structure a circuit of mode switching (CMS) is realized according to fig. 8. The control signals are “test”, “shift” and “system mode” (fig.8). It’s obviously, that Tk test time of such circuit can be found as:
Tk ^ T2 * log2 n.
Then if there is a need to apply approximately 2.4* 103 of equal probability pseudorandom patterns in case of usual procedure of pseudorandom exhaustive test organization, then under using of proposed method aimed to testable combinational devices design the test time Tk will be:
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Tk ^
ln(1 - ^0,99) ln0,75
* ]log2 20[ = 105(takts)
Structural redundancy of this method includes three components:
a) Redundancy of logical element construction (it’s XORs for CoC circuit and BFEs for CC);
b) n XOR elements instead of inversion elements for x1-xn variables;
c) ] log2 n[+1 memory elements for the CMS circuit.
As a matter of fact that switching of testable structure to operational (system) mode is being carried out by:
- applying of corresponding control signals to elements of all CC layers;
- applying of constant signals to all XOR elements (Pr inputs on fig. 12), that is by switching of theses elements in transmitting mode or in an inverter (in last case there is a need to apply a single-phase signals of input variables);
- applying of real input work patterns x1-xn instead of test pseudorandom sequences of equal probability patterns.
9. Conclusion
The method and corresponding structural implementation of designing of combinational digital devices that are
represented by perfect normal forms has been offered. As opposed to well-known methods of such devices, this method differs: firstly, by sufficient reduction of input test pseudorandom sequence length (by a number of degrees). Secondly, this method is being formalized enough and it doesn’t need preliminary topological analysis of an initial circuit to guarantee the needed degree of testability. Procedure of schematic synthesis in accordance with this method consists of: a) replacement of constituent’s realization circuit elements by the basic functional elements, b) construction of combining circuit as many-input wrap modulo 2 circuit and c) development of external circuit to control a BFEs’ working modes according to the number of levels into constituent generation circuits.
References: 1. CourtoisB. CAD and testing of IC’s and systems. Where are we going? TIMA, France, 1995. 250 p. 2. XaxaHoe B.H. TexHnnecKaa guarnocraKa ^neMeHTOB u y3noB nepcoHantHtix KOMnrroTepoB. K.: H3MH, 1997. 308 c. 3. HpMonuK B.H.. ffeMu-deHKo C.H. reHepnpoBaHne u npuMeHeHue nceBgocnynanHLix cnraanoB b cucTeMax ucnriTaHnn u Kompona. Mhhck: HayKa u TexHnxa, 1986.200 c. 4. ParkerK. P., McCluskey E.J. Probabilistic treatment of general combinational networks. IEEE Trans. on Comput. 1075. Vol. C-24. N° 6. P. 668-670. 5. PoMameeuu A.M., rpoMbB.B. MeTog nocTpoeHna TecTonpnrogHtix uu^poBtix cxeM, opueHTupoBaHHtix Ha nceBgocnynanHoe TecrupoBaHue // ^neKT-poHHoe MogenupoBaHue. 1996. T.18. N°5. C. 29-33. 6. AKcemea r.n, Xanuee B.0. MeTog napannentHo-nocnegoBaTentHoro ca-MoTecTupoBaHHH CEHC Ha ocHoBe nx geKoMno3nuun // ABToMaTu-Ka u TeneMexaHHKa. 1991. N°4. C. 147-156
DOES IT POSSIBLE DESIGNING A MEMORY WITH ESSENTIALLY GREATER FAULT TOLERANCE?
MICHAIL F. KARAVAY1 2,
VLADIMIR V. SINELNIKOV
1 - ICS RAS, mkaravay@ipu.rssi.ru, (095)334-77-39, 117997, rcn-7, B-342, Moscow, Profsoyuznaya str,, 65
2 -FSUE MECB MARS, (095)978-34-94,103030, Moscow,1-st T schemilovskiy lane. ,16.
Annotation.The new fault tolerant main memory architecture based on three features: controller ofHamming’s code (ED AC), controller recovering true information of stack-type errors in memory words, and a small additional memory for storing recovered words (“diagnostic cache”) is proposed. Information recover algorithm is hardware realized and does
not introduce any essential additional delay in access to information would it be correct or erroneous memory cells. Modern n-channel fault tolerant systems where n usually is equal 2^5, supported by EDAC controller, cannot tolerate double and more stack-at failures in the memory word. These failures evoke of channel’s upset and after redundancy exhausting - system’s crash. Naturally the situation requires using extremely reliable and expensive memory chips especially into hard radiation environments. Proposed new architecture is capable to tolerate up to tenfold or even hundreds of failed cells having multiple stack-at failure in every channel. This feature becomes very valuable for using of not only SRAM but a much larger DRAM as well in the hard external circumstances. If take as a unit for basic comparison the fault tolerant system with EDAC possibilities then the proposed architecture demands only a small overhead of extra hardware not exceeding a few percents. All new actions are free from any software overheads and transparent for programmer.
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