CC BY
31
Tk ^
ln(1 - ^0,99) ln0,75
* ]log2 20[ = 105(takts)
Structural redundancy of this method includes three components:
a) Redundancy of logical element construction (it’s XORs for CoC circuit and BFEs for CC);
b) n XOR elements instead of inversion elements for x1-xn variables;
c) ] log2 n[+1 memory elements for the CMS circuit.
As a matter of fact that switching of testable structure to operational (system) mode is being carried out by:
- applying of corresponding control signals to elements of all CC layers;
- applying of constant signals to all XOR elements (Pr inputs on fig. 12), that is by switching of theses elements in transmitting mode or in an inverter (in last case there is a need to apply a single-phase signals of input variables);
- applying of real input work patterns x1-xn instead of test pseudorandom sequences of equal probability patterns.
9. Conclusion
The method and corresponding structural implementation of designing of combinational digital devices that are
represented by perfect normal forms has been offered. As opposed to well-known methods of such devices, this method differs: firstly, by sufficient reduction of input test pseudorandom sequence length (by a number of degrees). Secondly, this method is being formalized enough and it doesn’t need preliminary topological analysis of an initial circuit to guarantee the needed degree of testability. Procedure of schematic synthesis in accordance with this method consists of: a) replacement of constituent’s realization circuit elements by the basic functional elements, b) construction of combining circuit as many-input wrap modulo 2 circuit and c) development of external circuit to control a BFEs’ working modes according to the number of levels into constituent generation circuits.
References: 1. CourtoisB. CAD and testing of IC’s and systems. Where are we going? TIMA, France, 1995. 250 p. 2. XaxaHoe B.H. TexHnnecKaa guarnocraKa ^neMeHTOB u y3noB nepcoHantHtix KOMnrroTepoB. K.: H3MH, 1997. 308 c. 3. HpMonuK B.H.. ffeMu-deHKo C.H. reHepnpoBaHne u npuMeHeHue nceBgocnynanHLix cnraanoB b cucTeMax ucnriTaHnn u Kompona. Mhhck: HayKa u TexHnxa, 1986.200 c. 4. ParkerK. P., McCluskey E.J. Probabilistic treatment of general combinational networks. IEEE Trans. on Comput. 1075. Vol. C-24. N° 6. P. 668-670. 5. PoMameeuu A.M., rpoMbB.B. MeTog nocTpoeHna TecTonpnrogHtix uu^poBtix cxeM, opueHTupoBaHHtix Ha nceBgocnynanHoe TecrupoBaHue // ^neKT-poHHoe MogenupoBaHue. 1996. T.18. N°5. C. 29-33. 6. AKcemea r.n, Xanuee B.0. MeTog napannentHo-nocnegoBaTentHoro ca-MoTecTupoBaHHH CEHC Ha ocHoBe nx geKoMno3nuun // ABToMaTu-Ka u TeneMexaHHKa. 1991. N°4. C. 147-156
DOES IT POSSIBLE DESIGNING A MEMORY WITH ESSENTIALLY GREATER FAULT TOLERANCE?
MICHAIL F. KARAVAY1 2,
VLADIMIR V. SINELNIKOV
1 - ICS RAS, mkaravay@ipu.rssi.ru, (095)334-77-39, 117997, rcn-7, B-342, Moscow, Profsoyuznaya str,, 65
2 -FSUE MECB MARS, (095)978-34-94,103030, Moscow,1-st T schemilovskiy lane. ,16.
Annotation.The new fault tolerant main memory architecture based on three features: controller ofHamming’s code (ED AC), controller recovering true information of stack-type errors in memory words, and a small additional memory for storing recovered words (“diagnostic cache”) is proposed. Information recover algorithm is hardware realized and does
not introduce any essential additional delay in access to information would it be correct or erroneous memory cells. Modern n-channel fault tolerant systems where n usually is equal 2^5, supported by EDAC controller, cannot tolerate double and more stack-at failures in the memory word. These failures evoke of channel’s upset and after redundancy exhausting - system’s crash. Naturally the situation requires using extremely reliable and expensive memory chips especially into hard radiation environments. Proposed new architecture is capable to tolerate up to tenfold or even hundreds of failed cells having multiple stack-at failure in every channel. This feature becomes very valuable for using of not only SRAM but a much larger DRAM as well in the hard external circumstances. If take as a unit for basic comparison the fault tolerant system with EDAC possibilities then the proposed architecture demands only a small overhead of extra hardware not exceeding a few percents. All new actions are free from any software overheads and transparent for programmer.
R&I, 2003, Ns 3
99
