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ADVANCED SOFTWARE TOOLS FOR FAULT SIMULATION AND TEST GENERATION
VLADIMIR HAHANO V, ALEXANDER EGORO V, OLGA MELNIKOVA, VOLODYMYR OBRIZAN, EVGENIYKAMENUKA,
OKSANA KRAPCHUNOVA, OLESYA GUZ
Abstract. Fast software tools oriented on processing of complex digital devices containing hundreds of thousand equivalent gates are offered. All methods and algorithms realized in programs are oriented on considerable (dozens and hundreds of times) fault simulation and test generation time decrease. Such results can be achieved due to application of new structural and logical analysis technologies, object reconfiguration during the processing. Data structure is oriented on compilative, interpretative realization of algorithms, that makes system flexible and high-speed.
1. Intorduction
Actuality of new fault simulation means design is conditioned by necessity of considerable increase of test generation speed for complex digital devices implemented in FPGA and ASIC. Automatic test generation systems of known firms (Cadence, Mentor Graphics, Synopsys, Logic Vision [www.cadence.com, www.logicvision.com,
www.simucad.com,www.syntest.com, www.synopsys. com, www.mentorgraphics.com]), oriented on processing of chips containing at most hundred of thousand equivalent gates can be considered as prototypes of designed software tools. This systems have following disadvantages: 1. The cost of mentioned means is hundreds of thousands dollars. 2. Processing time is unacceptable if digital device contains millions of gates. Therefore, it is necessary to increase the speed of complex digital devices analysis. Forproblem solving the new technologies are used. They are: structural analysis of digital devices, model reconfiguration during the processing, combination of advantages of deductive and parallel fault simulation methods, test generators selection from the number of deterministic, algorithmic, pseudorandom.
The unit under test is a digital device described in VHDL in a form of Boolean equations implemented in FPGA.
The purpose of the work is the development of fast software tools for digital devices testing at the stages of their formalization, implementation and synthesis, which enable the decrease of digital devices verification time.
The tasks are:
1. Tool design for test quality evaluation by software implementation of parallel, deductive, deductive-parallel, backtraced-deductive-parallel fault analysis algorithms.
2. Test synthesis tools design on the base of software implementation of deterministic, algorithmic, pseudorandom generators.
3. Realization of multiwindow user-friendly interface which allows to display fault-free and fault simulation results, obj ect structure and testing results statistics, to select test synthesis mode.
4. Simulation and synthesis tools testing and verification on test examples from ISCAS library.
The research tasks are:
1. The development of structural compilative-interpretative model of digital device for test generation and fault simulation.
2. Development of structure functional analysis algorithms for combinational and sequential circuits with the purpose of circuit structure reconfiguration during the test synthesis and fault simulation. 3. Deductive-parallel, backtraced-deductive-parallel, backtraced quasi-exact fault simulation algorithms development. 4. Deterministic, algorithmic, evolutional, pseudorandom generators development.
Source information for the development of test generation, fault simulation, structural analysis algorithms is presented by publications: BDP fault simulation method [1,2,8,11,14], Fault transposition deductive models [3,4-7,10], Backtraced fault simulation method [8,10,11,15], parallel method of fault lists processing [4-6], digital system structural analysis with the purpose of reconvergent fan-outs detection [8,14,16], verification technology during the discrete objects computer-aided design [9,10,12], Digital projects simulation system -Active-HDL[13].
2. SIGETEST Structure
The following modules were designed according to the tasks being solved by SIGITEST:
1. The convertor into internal data structure. It uses VHDL2BOOL compiler designed by firm Aldec[13] and converts the source file described in VHDL(Verilog) into BNF format. It contains code translators BE2SCH, RTL2BESF, EDIF2BESF.
2. Automated test pattern generation unit.
This unit is used for test pattern generation using three groups of methods. They are algorithmic, deterministic and pseudorandom. The first group consists of deterministic and cubical methods. They are the most exact but are not used for complex projects testing. The second group includes algorithmic, pseudorandom and genetic algorithm methods. Pseudorandom test generation is used for complex digital circuits and genetic method initialization. The subsystem of algorithmic test generation methods consists of following generators: logarithmic, Gray code, running 0, running 1, checkerboard, galloping 0, galloping 1.
3. Fault simulation using compilative and interpretative models.
It includes topological circuit analysis with the purpose of feedback and reconvergent fan-out detection. The deductive-parallel analysis is used if there are fan-outs in the circuit. Defects analysis on the basis of superposition procedure needs linear from the number of lines time costs:
Q = (r* 1 2 3/W) + nr + np + (n - r - r0)
where (r2 /W) - r -is fan-out fault simulation time; the number of fan-outs is defined as r = 0.2*n; nr = n is primitive reconfigurationtime, np = n is the time ofsubgraph search, (n - r - r0) = n - 0.2*n - 0.4* n = 0.4* n is the time of superposition procedure for all lines except reconvergent fan-outs. Considering the values of mentioned
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parameters the following evaluation of BDP method speed can be used:
Q=[(0.2*n)2/W]+n+n+(n-0.2*n-0.4*n) =[(0.2*n)2/W|+24*n
Thus, the gain in efficiency of BDP method is so much better the less is the percent of reconvergent fan-outs in the circuit.
4. Diagnostic information processing. Test minimization.
The test minimization procedure for sequential circuits has some features. All test patterns are divided into test segments. They can be reordered by quality. Some segments can be excluded from the test if its quality does not change. This enable to minimize the test.
5. Test conversion into VHDL TestBench.
It includes the conversion of test received into VHDL( Verilog) format which can be used for further project verification in Active-HDL.
3. SIGITEST supported data formats
The purpose is to make test generation and fault simulation system invariant towards existing hardware description languages such as System C, Verilog, VHDL. The compilers from this languages to internal data formats are developed for this purpose. XILINX library of RTL elements is supported. The place of fault analysis system, integrated in automatic test generation environment, as well as compatibility and interaction of internal data formats and hardware description languages are shown on figure:
Figure l.The place of fault analysis system, integrated in automatic test generation environment.
3.1 BNF format.
It is used for digital devices description in a form of Boolean equations using limited number of operators and elements. The operators are: j'-OR, '&'-AND, T-NOT, 'A'-XOR. BNF format is oriented on automatic model construction for realization of test generation and fault analysis algorithms.
Thus the device, described in hardware description languages is automatically converted into BNF format. The feature of combinational and sequential circuits description is that BNF structure contains strongly defined primitive library. The library consists of 18 flip-flop and latch gate equivalents, which have special names. More complex sequential elements, such as counters and registers, are converted into BNF by combination of existing library primitives. The examples of BNF description are shown below.
Listing 1: BNF description of combinational circuit c17 from ISCAS library.
gat10=!(gat1 &gat3);
gat11=!(gat3&gat6);
gat16=!(gat2&gat11);
gat19=!(gat11&gat7);
gat22=!(gat10&gat16);
gat23=! (gat16&gat19);
Listing 2: BNF description of sequential circuit. process equations begin, line: 14 pragma asyn(t-1);
{ C_tmp0=s;
D_tmp0=s&(a);
latch(C_high,D)
S_tmp0=D_tmp0&C_tmp0;
R_tmp0=C_tmp0&!D_tmp0; z(t)=S_tmp0|(!R_tmp0&z(t-1)); } state.out file begin state.out file end process equations end, line: 14
In this example the keyword asyn(t-1) is followed by latch description. The keyword latch(C_high,D) defines the latch type.
3.2 SCH format.
SCH circuit description is used for software implementation of deterministic test generation algorithms. SCH format is oriented on tabular form of primitive functions description. SCH format consists of four parts. They are: the header, circuit structure description, primitive description, look-up table.
1. The header.
It contains general circuit information such as number of lines, inputs, outputs, feedbacks, fan-outs.
2. Circuit structure.
Circuit structure description contains the list of all lines and primitives, primitive numbers and their inputs. All lines are numerated according to the rule: The number of output for each combinational element should be greater than numbers of its inputs.
3. Primitive description.
Primitive description includes a library which contains functional description of each element in a form of cubical
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covering. When using several element of the same type, only one description is kept in the library. Therefore, the library size is defined by the number of primitive types and not the number of primitives.
4. Look-up table.
Look-up table contains the list of lines and their numbers. Before circuit processing the names of the lines are replaced by numbers. The correspondence between names and numbers is tabulated.
3.3 RTL Database Repository.
RTL Database Repository is an output format of RTL Compiler designed by firm Aldec(USA). It is a system for preliminary synthesis of a project described in VHDL. Its function is VHDL code parsing. RTL is a hierarchical, structural combination of standard elements from the Repository library. The examples of VHDL circuit description and post synthesis description in RTL format are shown below.
Listing 3: VHDL latch description.
library ieee;
use ieee.std_logic_1164.all; entity dff is port (
DIN : in std_logic;
CLK : in std_logic;
RES : in std_logic;
SET : in std_logic;
Qout: out std_logic ); end entity;
architecture dff of dff is begin
process (CLK) begin
if RES = '1' then
Qout <= '0'; --(others => '0'); elsif SET = '1' then
Qout <= '1'; --(others => '1'); elsif CLK'event and CLK = '1' then Qout <= DIN;
end if;
end process;
.input (RST, 1, "ASYNCH")
.input (SET, 1, "ASYNCH")
.input (CE, 1, "ACTIVE_HIGH")
.attribute (PRIORITY, "RST")
.attribute (REG_TYPE, "LATCH")
.end primitive
The translator RTL2VHDL is used for verification of RTL structure. It enables to verify structure functional models by test pattern simulation in Active-HDL.
3.4 EDIF Gate Level format.
It is used for gate-level circuit description and specify the synthesized structure taking into account the PLD, which it was implemented in. Besides gate elements implemented system can contain "black box" primitives. It depends on PLD type, optimization level, synthesis character. The description of such primitives is replaced with the help of IP-cores during the EDIF format translation into internal SIGITEST data format.
Thus, SIGITEST supports the following formats: gate description in VHDL, BNF description, RTL Data Base Repository(RTL2BESF translator), EDIF description.
4. SIGITEST for user
SIGETEST - (SImulation, GEneration of TEST) is the fast test generation and fault simulation system. Any digital structure described in a form of Boolean equations can be used as simulation object. The system can process complex digital devices containing hundred thousands of gates. The simplified structure of main user-available modules is shown on figure 2.
DESIGN TESTING ENTRY
end dff;
Listing 4: RTL latch description. .primitive (REGISTER)
.parameter (SIZE)
.output (Q, SIZE, REG)
.input (D, SIZE, "1")
.input (CLK, 1, "ACTIVE_HIGH")
F igure 2. Structure of main user-available modules
System has integrated environment which realizes graphical interface. The design entry for the system should be represented in VHDL or BNF format. The compiler (SDP_MAKE) converts BNF description into internal data structures. It is used by structure analyzer and simulation kernel. Simulation kernel includes Parallel, Backtraced Quasi Exact, Deductive-Parallel and Backtraced-Deductive-Parallel fault simulation algorithms.
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SIGITEST contains the means for test synthesis control. Simulation can be constrained by time. User can define a number of test vectors to simulate. SIGITEST has documentation that gives complete information about interface, supported formats, work examples and frequently asked questions. SIGITEST is compatible with Aldec Active-HDL & Riviera, Synopsys Design Compiler simulation and synthesis tools.
5. Compiler, structure analyzer
Converter is VHDL to BNF conversion tool. BNF has more suitable format for compilation than VHDL, because it is defined on more simple syntax and has no project hierarchy. The Boolean equations in VHDL are converted to similar BNF structures. More complicated algorithms are used for hierarchy flattening. Top-level entity for VHDL model is defined by design hierarchy analysis.
Compiler is a tool for BNF to internal SDP structure conversion. Structure analyzer performs optimization, circuit decomposition on two-input gates, reconvergent fan-outs and feed-backs detection. Special algorithm is implemented for resolving of conflicts which appear if more than one identifier corresponds to one physical line.
6. Simulation kernel
Simulation kernel realizes fault-free and fault simulation. Its functions can be divided into the following parts:
1. SDP-file loading, internal data structure initialization, reconfigurable model construction.
2. Fault- free simulation.
3. Circuit model reconfiguration. Reconvergent fan-outs fault simulation using deductive-parallel fault simulation method.
4. Realization of superposition procedure for fault simulation of tree-type structures.
The mentioned steps make up the base of Backtraced-Deductive-Parallel fault simulation method.
The software implementation of fault simulation algorithms for combinational and sequential circuits differs greatly. The information about two iterations should be stored for sequential circuits processing. As a result, memory and timing costs for sequential circuits processing are twice as many as for combinational circuits.
7. Testing and verification
The purpose of testing is to find bugs in SIGITEST system by fault-free and fault simulation results analysis and their referencing. SIGITEST was tested on more then 600 of combinational and sequential circuits (latches, flip-flops, counters, registers, adders, multiplexers and so on). At the same time the circuits variety was essential: combinational or sequential, number of inputs, outputs, reconvergent fan-outs, feedbacks. The fault-free simulation results were compared with those received with Active-HDL 5.2, Nemesis, ModelSim. The testing of fault simulation results consisted of two steps:
1 .Fault simulation results were compared with those received theoretically and by means of Nemesis, HITECH-PROOFS.
2. Fault simulation results received by different methods (Backtraced Quasi Exact, Deductive-Parallel, Backtraced-Deductive-Parallel) were compared with each other.
On the basis of carried analysis a conclusion was made about number of bugs. The bug report was made with the purpose of further debugging.
The following features of Backtraced Quasi Exact fault simulation method were detected during system analysis:
1. The fault simulation results received by Backtraced Quasi Exact fault simulation method can differ from those received by Deductive-Parallel, Backtraced-Deductive-Parallel fault simulation methods for some sequential circuits.
2. Mismatches predicted by theory can be detected during simulation of circuits containing reconvergent fan-outs. Such circuits should be simulated using any other fault simulation method.
8. Conclusion
Fault simulation and test generation system is oriented on processing of complex digital devices containing millions of gates. The practical use ofthe Backtraced-Deductive-Parallel fault simulation method on hundreds of combinational and sequential circuits gave good results in comparison with deductive and parallel fault simulation methods. The results of SIGITEST, NEMESIS, Turbo Tester speed comparison are shown on figure 3. The advantages of Backtraced Quasi Exact fault simulation method (figure 4) are caused by decrease of reconvergent fan-outs fault simulation accuracy. The memory and time costs for processing of complex circuits using three fault simulation methods are shown on figures 4 and 5.
Thus, the upgrade of deductive-parallel fault simulation method is the main scientific result applied in SIGITEST. It consists in :
1. Generalized model building during the deductive-parallel analysis ofthe circuit on the base of superposition procedure.
2. Deductive algorithms development for structure functional analysis of circuits with the purpose of fan-out detection and structure reconfiguration.
3. Internal interpretative model building for efficient analysis of gates.
The further SIGITEST development is connected with improvement of structural analysis, namely:
1. Analysis of false faults appearance for all kinds ofindustrial flip-flops.
2. Theoretical proof of superposition procedure correctness for riiD-floD structures.
Figure 3. Speed analysis. Nem- Nemesis system, TT -Turbo Tester, DP -deductive -parallel method, BDP - Backtraced-Deductive-Parallel method
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Figure 4. Time costs for processing of complex circuits
Figure 5. The memory costs for processing of complex circuits
3. Investigation of structural analysis problem for asynchronous circuits with global feedbacks.
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