CC BY
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TEST QUALITY EVALUATION FOR COMPLEX DIGITAL SYSTEMS
VLADIMIR HAHANOV, STANLEYHYDUKE, IGOR CHUGUROV
Design Automation Department, Kharkov National University of Radio Electronics, Lenin ave, 14, Kharkov, 61166, Ukraine. Tel.: +380-572-702.1326. E-mail: [email protected]
Abstract. A high performance Back-traced Deductive-Parallel (BDP) fault simulation method based on the superposition procedure is oriented on a using large digital designs processing. Evaluation ofRT and gate level design description is proposed in this work. The data structure and program are developed for algorithms realization of proposed method and integration with automatic test pattern generation systems.
1. Introduction
The actuality ofwork is defined by investigation of simulation and test generation tools for structurally complex digital systems, implemented into ASIC-, PLD-chips. Existing leaders of design automation and testing (Cadence, Mentor Graphics, Synopsys) are oriented on processing designs that contain about 100 000 of gates, during acceptable time, equal to several hours. Existing tools of test synthesis and fault simulation may be not applicable to designs, that contain several millions gates. This problem requires principally new technologies that would allow significantly increase processing speed of digital system fault simulation for test verification. BDP-method for solving problem of high performance stuck-fault simulation for test quality evaluation in digital system design, based on ASIC, PLD is offered. Unit under test - is digital system, represented in form of Boolean equations, described on VHDL language, oriented to implementation on mentioned chips.
Purpose of investigation is development of the high performance stuck-fault simulation method for quality evaluation of generated tests for digital systems, implementing into ICs, containing millions of gates. Practically acceptable fault simulation time should have the number of reconvergent fan-outs (RF O) in digital linear dependence from the number of equivalent gates, if circuit is not more than 20 percents from number of lines.
Basis of Back-traced Deductive-Parallel fault simulation method are - cubic fault simulation [ 1 -3 ], deductive model offault propagation [4,5], parallel method of fault simulation [4,6] and back traced algorithm [7] for processing of digital device.
2. Model of Deductive-Parallel fault analysis
The model of deductive-parallel fault analysis of digital circuits allows defining all defects, detected on test-vector during the one iteration of circuit processing. Such model is based on solving the following formula [1]:
T © F = L, (1)
where F = (F1,F2,...,F;,...Fn) - model of fault-free circuit behavior;T = (T1,T2,...,Tt,...,Tk)- test composed of k
binary patterns; L = (L1,L2,...,Lt,...,Lk)- set ofdeductive functions (DF) for parallel fault simulation on test T, corresponding to fault-free model F.
In general case, when function of the system is represented as truth table, using formula (1) allows to obtain fault propagation table for defined test-vector, fault simulation deductive function can be written using this table. Samples of obtaining of such function are presented as(the first component is test, the second and the third one are truth and fault propagation tables):
L(Y) = X1X2 v X1X2;
L(Y) = X1X2 v X1X2 v X1X2.
For definition of i-line good value functional component description F; e F of digital circuit is presented by Boolean function
Fi = f1(X11,Xl2,...,X1J,...Xln_). (2)
Problems of investigation: 1. To create general deductive parallel analysis model of digital circuits based on back-traced superposition procedure. 2.To develop algorithms of structural-functional analysis of digital systems for the purpose of RFO set searching and structure reconfiguration for implementation of fault simulation superposition procedure. 3. To create internal interpretative-compiled model of digital device for effective fault-free analysis of logic elements and their single stuck faults.4.The algorithmic and program realization of simulation method on the basis of device model reconfiguration during the process of fault simulation for the purpose of significant decreasing test quality evaluation time.
Coordinate Tti e Tt is a result offunctionf good simulation,
when Tti = Fi on test-vector t. Note that test is matrix of
fault-free behavior of digital system with determined values of all coordinates:
T = [TtL| = (Tt1,Tt2,...,Tti,...,Tt„). (3)
For test ofnvectors, equation (1) for obtaining DF for Tt e T
is following: Lt = Tt © F. Since digital circuit description represented by functional components, forming values of all circuit lines, then formula of good primitive model is transformed into deductive function is:
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Lti = Tt ® Fi = fi[(Xii ® Ttl),(Xi2 ® Tt2),... -,(Xij © Ttj),...,(Xjn. © Ttn_)] © Tti, (4)
Expression (4) is analogue to formula of deductive primitive element analysis, represented in [5]. Practical realization of expression (4) leads to creation of defect analysis algorithm:
1. Forming of interpretative models of digital system circuit W = {F,L0} . Primary definition of initial test-vector number t=0. Initialization of detectable fault vectors
V (D0 = 0; D1 = 0) on the test T = [Tti ]. i=1
2. Definition of the next input test pattern number t=t+1 for Tt e T. If there aren’t input patterns (t > k) then the end of simulation.
s = v Mr
VieY 1
(7)
it is applied to all matrix rows, corresponding to the primary output.
7. When the condition V (Si = S0 v S1) is fulfilled evaluation
i=1
of test pattern quality is executed by formula 1 n
Q(Tt) = ttE (s0 + S1>]' (8)
2n i=1
then the transition to the next step is fulfilled, otherwise - pair {S0,S1} is formed by equation
S0 = S aT,(S0 = Si aTi); S1 = S aT,(S1 = Si aTi) (9)
3. Fault-free simulation ofall primitives Fi(i = 1,n) (definition of internal lines values) of digital circuit on input test pattern TtX e Tt via model F e W for the hipping purpose of non
input coordinates TtX e Tt:
If detected faults disappear from vector S = {S0,S1}:
3 [(Si = 0) & (S0 v S1 = 1)] ,
i=1
thanit have to eliminate such defects from process ofsimulation by the rule:
TtX = f(TtX,F). (5)
Condition of transition to the next step is identity of all good line values in the consecutive iterations: Ttr = Ttr_1.
The pair analysis of consecutive vectors: (Tt1, Tt ) is used for processing of sequential circuits and organization of
event-driven simulation it is used. Primitive Fi (i = 1, n) is simulated if there are different input line values [TX1 (Fi) ^ TtX (Fi)] on processed primitive element.
4. Initialization of detected fault matrix on applied test-vector:M = [Mij], according to the expression:
[Mij]
(i,j=1,n)
0 ^ (i * j);
1 ^ (i = j).
(6)
For test-vector Tt e T initialization of detected fault vectors
V(S° = 0; S1 = 0). i=1 i i
Reconfiguration of good interpretative primitive models Li (i = 1,n), Li e W by applying formula (4) for current test vector with defined good lines values:
Tt = (Tt1,Tt2,...,Tti,...,Ttn) for achieving of modification Lti = Tt © Fi.
5. Forming of non input lines values of detected fault matrix by the parallel simulation of primitives: Lti e Lt.
6. Forming of united detected fault vector S by formula:
(S0 = S1 = 0) ^ V[(Si = 0)& (S0 v S1 = 1)].
i=1
Fulfill transition to step 5.
8. Forming detectable fault vectors according to expression D0 = D0 vS0, D1 = D1 v S1 (10)
and evaluation of test quality by formula:
1 n
Q(T)+Di>i. (11)
2n i=1
Fulfill transition to step 2.
Represented algorithmic realization is oriented both on table description of complex primitives of RTL level and gate description of digital systems. Processing speed is invariant to the model type. Interpretative realization is more practically feasible from the view of program realization.
Universal functional promitive for deductive fault simulation is represented at fig. 1.
Phc. 1. Fault simulator
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It is oriented of creation of embedded hardware tools for deductive-parallel fault simulation acceleration in about tenth and hundredth times. At the same time, relations of fault and fault-free models volumes are 7:1. Boolean (x1 ,x2) and register (X1,X2) input variables are represented in simulator. Mode variable for choosing function type (AND, OR) and output register variable Y are represented too. Binary inputs x1,x2 states and signal mode variable define one of the four deductive function for obtaining detectable faults vector Y.
Sample of 4-bit fault vecors propagation to output Y for 2AND logic elemets is represented by the following table:
And/Or x1x2 X1 X2 Y
0 00 0111 1011 0011
1 00 0111 1011 1111
0 11 0101 0110 0111
1 11 1101 0111 0101
Simulator application doesn’t suppose presence of digital device fault-free behavior model. Otherwise, this model is used for deductive model creation of design for purpose of generated test quality evaluation. Such hardware fault analysis approach is improvement of hardware embedded simulation technology like HESTM.
3. Interpretative model offault-free behavior analysis
Structural model of primitive element good logic simulation for digital device is presented on fig. 1. The question about procedure of test vector T(Y) evaluation for definition of coordinate, which correspond to output Y of logic element F is observed here. Its input values are represented by vector: X = (X1,X2,...,Xk), and FT is truth table of Boolean functions set, defined on concatenation of two vectors of binary variables (F*Tx ):
T(Y) = Ft(F*Tx) = FT(F*T(X1)*T(X2)*...*T(Xk)).
Otherwise, for definition of coordinate T (Y) it is necessary to form binary vector of input variable values Tx on the basis of vector of line numbers X (see fig. 2).
Figure 2. The structural model of element analysis
Then it is necessary to make concatenation of obtained vector with binary code of primitive kind F for (F*Tx) row obtaining oftruth table FF, where in column Y, corresponding to the meaning of function, required value of coordinate T (Y) is present. Model of deductive-parallel fault analysis contains fault-free simulation structure that added by two modules (M, Ff ), as it is shown on fig. 3. Analytic expression for calculating detected fault vectors, combined into matrix M with the helping of deductive function Ff which is transformed from F by expression (4), is represented by:
M(Y) = Ff(F* T(X), M(X1) o M(X2) o... o M(Xk)) = = F(F*T(X)) (M(X1) o M(X2) o... o M(Xk)).
Here are operation, marked with the sign o = {a,v} , may be presented by disjunction or conjunction; F(f*t(X)) -deductive element, defined by binary address word
(F*T(X)). For definition of vector-row M(Y) state it is necessary to find address (type) of deductive compiler-driven function, by using obtained concatenation of binary sequences (F*T(X)) during the fault-free simulation process. Input variables for element f(f*T(X)) are register ones, where their theoretical length is equal to the number of lines in digital device. Then sequential execution of (k-1) register operations for all input vectors M(Xi) e M is realized. Result as a formed row M(Y) is written into matrix M. Vector-variable Xi can have inversion sign. In this case before execution of operations ° = {a,v}, inversion of register (variable) M(Xi) = M(Xi) is performed.
Figure 3. Model of deductive-parallel analysis
As an example let’s consider the general truth table of four good behavior functions which contain also information for selection of binary address word of deductive compiler-driven functional element for fault analysis:
S F X1X2 Y ff
A 00 00 0 00
00 01 0 01
00 10 0 10
00 11 1 11
V 01 00 0 11
01 01 1 10
01 10 1 01
01 11 1 00
S F X1X2 Y ff
A 10 00 1 00
10 01 1 01
10 10 1 10
10 11 0 11
V 11 00 1 11
11 01 0 10
11 10 0 01
11 11 0 00
Here column F is identifier code offault-free behavior function, (Xj ,X2) - set of binary input vectors of truth table for each of the four functions, Y - fault-free column value of function output, FF - address word of deductive element compiled model that is represented by four primitives:
Ff =
00 ^ X1 A X2;
01 ^ X1 a X2;
10 ^ Xi a X2;
11 ^ X1 v X2.
The computing complexity of digital circuit processing, which contains n two-input elements, is defined by following expression:
Q = [(2K + A) + A + (2m) / W] = [2(K + A) + (2m)/W] x n,
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where K - the bits concatenation time for obtaining address of function output value; A - the time of bit writing according to mentioned address; x - the time of register operation (and, or, not) execution; W - the register length.
Because the first item 2(K+A) is unessential in comparison with the second one, computing complexity could be
represented as following: Q = (2n2x) / W .
That is why the time expenses of digital circuit simulation are square proportional to the number of gates.
4. Deductive method of structural analysis
Let’s consider the current node (line) Vj e V for the oriented graph G of equipotent lines. The current node Vj e V is so called original which can have corresponding predecessor nodes called image: f-1(Vj). The relations between mentioned subsets of the nodes are presented by formula:
V1 = f _1(Vj),Vi c V, (12)
where V1 c V - is subset of firsthand-predecessors for Vj.
The node model under consideration is a logical element OR, where the number of inputs is equal to its input edges. For example, if the or-graph contains 9 nodes (fig. 4) then it has 9 logical elements where edges are identified with input lines of primitive element OR.
Figure 4. Re-convergent fan-outs graph
Statement 1. Each node of feedback free graph has unique union of original and superposition of its images ff^Vj) u Vj ] that so called extra-original.
Statement 2. All nodes in graph belonging to feedback loop have the equivalent extra-originals.
This statement is true because there is the same contra-reachability of each graph point that belong to the feedback loop from the node that is predecessor for any feedback loop point. There are the nodes predecessors for RFO that are observed in fan-in line like rFo. Such predecessors have the same extra-originals as RFO. Node that has the single path without fan-outs till RFO is an example of such line.
Statement 3. For removing all predecessors ofRFO including in set Vj for node Vj and which are not RFO it is necessary and enough to deduct the intersections union of all pair of combination C2 from set Vj.
nj
The procedure of deductive analysis: for oriented graph that has not the global feedback loops the strategy of RFO searching consists of the one pass around all nodes. This procedure based on the reach ability of deductive processing each of nodes includes three operations:
p=i_____
q=i+1,nj
i)Vj = U[fp_1(Vj) fq1(Vj)];
C2 i=1,n j -1
nj j
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p=i___
q=i+1,mj
2) Vj = Vj \ U [Vp _Q Vq];
C2 j i=1,mj -1 j
mj J
nj
3) Vj = [U fi“1(Vj)uVj]\Vj,
i=1
(13)
where f_1 (Vj) - the element of original f _1 (Vj), the total number of which for node Vj is equal to n^
The first equation is intended for RFO definition based on
C2
operation of union of all original combination Cnj pair
intersection of considered node. The second one is intended for excluding from the list of RFO the nodes that are not reconvergent fan-outs in according to the statement 3. The third one is intended for forming of predecessor list for each node. For the graph example (fig. 3) the sequential processing of all nodes by rules (13) is represented the following result of calculation:
V1 =0; V1 = {1};V2 =0;V2 = {2};V3 =0;V3 = {3};
V4 = (V1 n V2) = 0; V4 = {1,2,4};
V5 = (V1 n V2) u (V1 n V3) u (V2 nV3) = 0;V5 = {1,2,3,5}; V6 = (V2 n V3) = 0; V6 = {2,3,6};
V7 = (V4 n V5) = {1,2};V7 = {1,2,3,4,5,7}\{1,2} = {3,4,5,7};
V8 = (V4 n V6) = {2};V8 = {1,2,3,4,6,8}\{2} = {1,3,4,6,8};
V9 =0;V9 = {2,3,6,9}.
The union of all subsets
VRC = U Vj j=1
represents possibility to obtain the full set of RFO (VRC) of digital structure graph (see fig. 3):
VR = V1 u V2 u V3 u V4 u V5 u V6 u V7 u V8 u V9 = = 0u0u0u0u0u0u {1,2} u{2} u0 = 1,2}.
Because the lines defined as RFO are redundant for the continuing structural analysis, these lines can be excluded from the original list for each node. However the defined set of RFO after evaluation of every node has to be added to separate subset VRC. Taking into account this statement it is necessary to modify equation 1 in (13). Such transformation leads to following equations:
p=i______
q=i+1,nj
1) Vj = U[fp_1(Vj) fq_1(Vj)]
C2 i=1,n j—1
nj j
p=i____
q=i+1,mj ;
2) Vj = Vj \ U [Vp n V_q];
C2 j i=1,mj-1 j
mj j
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3) VRC = VRC u Vj;
n;
4) Vj = [ U fi_1(Vj) u Vj ] \ VRC. (14)
i=1
The differences between procedures (14), (13) are in RFO accumulation into set VRC and its deduction from the list of predecessors for each node. Equation (14) is used for reduction of original line sub-sets for processed node.
5. Parallel-deductive analysis for graph structure
The vector Vj e V is as identifier of node Vj. The value j is position of vector coordinate that is equal to 1. Then the set of vectors (set of nodes in graph) is represented by unitary matrix:
V
Because of isomorphism of Boolean- and set theory algebra, formula (13) can be modified to the algebraic-logical form:
p=i_____
q=i+1,nj
1) Vj = V [fp-1 (Vj) fq1 (Vj)];
C2 i=Uj -1
nj j
p=i____
q=i+1,mj
2) Vj = Vj A—1[ U (Vp A V,q)]; (15)
C2 j i=1,mj -1 j mj
3) VRC = VRC V Vj;
nj i —RC
4) Vj = [Vfi_1(Vj) V Vj] A V .
where the conjunction and disjunction operations are executed under the vectors of matrix V. The same transformation under (14) brings to the result:
II II |1 ^ i = j;
II ljll(i,j=1,n) j [q ^ i ^ J,
p=i_____
. , q=i+1,nj ,
1>Vj = V[fp-‘(Vi)i _A_fq-'CVj)];
Cnj i=1,nj-1
p=i_____
q=i+1,mj
2) Vj = Vj A—[ u (Vp A V,q)];
J i=1,mJ-1 J
3) VRC = VRC V Vj;
nj _1 —RC
4) Vj = [V fi1(Vj) V Vj] A V .
i—1
(16)
The advantages of formulas (15) and (16) are:
1) The simultaneous operations on matrix rows allow to speed-up RFO analysis procedure in 10-100 times. 2) Speedup of RFO list generation due to the operation on vectors corresponding to the identifiers of nodes. There is the sequence of calculation as an example based on formula (16) application (see fig. 4):
1. Matrix V0 initialization:
V0 1 2 3 4 5 6 7 8 9
1 1 0 0 0 0 0 0 0 0
2 0 1 0 0 0 0 0 0 0
3 0 0 1 0 0 0 0 0 0
4 0 0 0 1 0 0 0 0 0
5 0 0 0 0 1 0 0 0 0
6 0 0 0 0 0 1 0 0 0
7 0 0 0 0 0 0 1 0 0
8 0 0 0 0 0 0 0 1 0
9 0 0 0 0 0 0 0 0 1
and initialization of the RFO vector by zero value:
VRC
1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 0
2. During the sequential nodes processing given by graph structure the following matrix V1 is obtained:
V1 1 2 3 4 5 6 7 8 9
1 1 0 0 0 0 0 0 0 0
2 0 1 0 0 0 0 0 0 0
3 0 0 1 0 0 0 0 0 0
4 1 1 0 1 0 0 0 0 0
5 1 1 1 0 1 0 0 0 0
6 0 1 1 0 0 1 0 0 0
7 0 0 1 1 1 0 1 0 0
8 1 0 1 1 0 1 0 1 0
9 0 1 1 0 0 1 0 0 1
3. Accumulation of RFO during the all nodes evaluation leads to the final result represented by vector VKC:
VRC
1 2 3 4 5 6 7 8 9
1 1 0 0 0 0 0 0 0
where meaning 1 identifies on line belonging to RFO list.
6. Graph structure analysis for sequential circuits
For analysis of sequential circuits by method of structural simulation it is necessary to obtain the identical list of original for each node included to the global feedback loop. First of all, the talk is about synchronous devices that have only local feedbacks in comparison with asynchronous one having global feedbacks. Because of delay hazard the last mentioned digital devices are not appeared by modern designing. That is why the circuits with flip-flops (FF) and latches having only local feedbacks are considered below. As an example of FF description, the set of equations in the Boolean Normal Form is represented:
S2_tmp0=C_tmp0*Q3_tmp0(t-1);
Q2_tmp0(t)=! S2_tmp0+(D_tmp0*Q2_tmp0(t-1)); R3_tmp0=!(D_tmp0*Q2_tmp0(t-1));
Q3_tmp0(t)=!C_tmp0+(R3_tmp0*Q3_tmp0(t-1));
Q(t,0)=!Q3_tmp0(t)+(Q2_tmp0(t)*Q(t-1)).
This description corresponds to the logical circuit of FF with 3 feedbacks is shown on fig. 5.
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The graph model for FF contains 8 lines, 3 - RFO, 6 - lines including in local feedbacks (fig. 6).
Figure 6. Graph model for FF. Nodes designation: 1 - ?,2-D,3 -S2,4 - Q3, 5 -Q3 ,6 -Q2,7 - Q2 ,8 -Q,9 -Q
According to the statements 1,2 the criteria to recognize feedback fromRFO is: existence ofidentical extra-originals for more then one node of digital device graph. The problem is in fact that the feedback nodes can be considered as RFO. There are two possible variants to solve this problem: 1) To add all feedback nodes to the set of RFO. 2) To mark feedback node as RFO if mentioned line has more then one outgoing arcs. In the first case the number of RFO is increased, if the circuit contains a lot of FF. The second variant is more preferable because in the real digital structures consisting of FF this one decrease the RFO numbervia cutting offeedbacks. Thus there is the following definitionfor identification of RFO for digital circuits with feedbacks.
Definition: for the synchronous circuits containing FF feedbacks, the loop line is RFO if this one consists of more then one outgoing arcs and has the nearest line of convergence which doesn’t belong to this feedback loop.
For the structure shown on fig. 7 the RFO are the lines (3,4). Considering graph represented in fig. 5 it can be assumed that the RFO is the nodes C, Q3, Q2 .
Figure 7. The graph with local feedback loop
7. BDP fault simulation method
The offered interpretative-compilative model of deductive-parallel fault-free and fault analysis is a base for BDP-method and guarantees finding the correct solution in form of detected
fault set on test-vector during the n2 iterations. The main idea of speed-up is connected with RFO modification into primary pseudo-outputs for superposition procedure execution of tree-like structures and its un-processing in case of undetectable ofRFO presence. The program realization ofBDP method consists of two basic components: 1)structure analyzer, which realizes RFO identification; 2) fault simulation on applied test-vector. Computational complexity of this
procedure is Qr = n2, but this one is executed on the step
of digital circuits pre-analysis and practically don’t impact for the operation speed of test-vector simulation. For procedure of deductive parallel analysis the calculation of binary vector R of RFO lines using one of the considered methods of structural analysis is executed, where:
R = (Ri,R2,...,Ri,...,Rn),
Ri =
1 ^ Ri e RRC; 0 ^ Ri g RRC
Test-vector simulation algorithm consists of the following steps (see fig. 8):
Fault-free simulation of test-vector
Fault simulation of reconvergent fan-outs
Deductive
Deducti ve-parallel
Decomposition of the circuit model
Elimination of undetected subgraphs
][
Parallel
Finding of tree-like sub graphs
Simulation of primitives of tree-like subgraphs
Deductive
Deductive-
parallel
The superposition of primitives faults for tree-like subgraphs
1
2
3
4
5
Figure 8. The strategy of back traced fault simulation
1. Fault-free simulation of digital circuit. It is used to define reaction of all non input lines on applied test-vector
Tt e T = [Tti ]. All lines are divided into input, internal and output lines: (X, Y, Z). It means that test-row from matrix of
fault-free behavior T presents as: Tt = (TtX, TtZ, TtY) Fault simulationvector S = (sX ,sZ ,sY ), is built every time for a new row Tt.
2. Fault simulation of RFO on applied test-vector. RFO reconfiguration into primary pseudo outputs. Vector
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initialization S = (SX = 0, S? = 0,sY = 1). If Si = 1 then stuck-at-fault inversed to the fault-free value of line is detected. Generation of initial list of RFO faults:
{Sj}
jTtj- Rj = 1;
0^ Rj = 0,
8. The speed evaluation of BDP method
As an example for the structure analysis and reconfiguration the circuit fromfig. 9 is represented. Lines 15, 17, 19 are RFO. As a result of applying structure analysis algorithm for RFO finding the circuit is transformed to four tree-like sub-circuits, defined as sub-graphs with root nodes, which are primary outputs or pseudo outputs, fig. 10.
where {Sj} c S; j = 1, n; S - fault list vector.
Fault simulation of RFO lines lr El-(Lr,lR), by
deductive-parallel (deductive) method on reconfigurable model, which corresponds to the test-vector Tt. The method should be used if the number ofRFO is non-significant (20%),
because of Lr / Lr << 1.
3. Circuit model decompositionbased on RFO fault simulation results. The tree-like sub-graphs with root node that is FRO with undetected faults, are excluded:
LU = lu \lr uf 1(l0r).
4. Fault simulation of lines, complemented re-convergent fanouts and sub-graphs with non detected root nodes till complete
set: Lu = LU \[LR uL*R uf 1(L<R)].
The inputs fault analysis of every primitive is fulfilled via application deductive-parallel algorithm to the detected fault matrix of current element only, not circuit. Such analysis can be also executed deductively, by using input fault detected lists of primitive.
5. Superposition procedure for detected fault vectors on modified digital device model which is concluded in transformation of RFO into primary pseudo-outputs. The mentioned procedure is leaded to disjunction ofinput detected
fault vector Si = (S1,S2,...,Sj,...,SI1.) of i-primitive with fault simulation vector S on conditions that line, corresponding
to the output of i-element, has 1-value (Si = 1):
S(ij)=saj)vsj ^ s; = 1,
where ^ = (Ill,I2,...,Ij,...,Iln.) - vector of input line numerical names of i primitive.
Consider the complete circuit superposition which is consequent unity of detected fault vectors for every primitive if its output line is predecessor for obtained set
Ly = Ly ^ Lr .
The fault detecting analysis is used only for primary outputs complemented by RFO, which faults are detected on test-vector Tt:
Ly
- ly ulr e lr -{Lr,lr};|lr| - r,
where Ly ,L*R ,L1r - are primary output lines, RFO with undetected and detected faults correspondingly.
Fault simulation of such circuit with usage of back-traced superposition requires linear dependence of memory- and time expenses from number of equipotent lines and square dependence on number of RFO in the circuit:
Q = (r2 /W) + nr + np + (n-r-r0),
where (r2/W) - fault simulationtime ofr RFO, their number is defined as r = 0.2 x n ; nr = n - the time of reconfiguration
ofcircuit primitives on applied test-vector; np = n- the time
of finding of sub-graphs lines corresponding to undetected faults of RFO;
(n-r-r0) = n-0.2xn-0.4xn = 0.4xn- the time of superposition procedure execution for the set of lines without
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RFO and predecessors for undetected RFO. Considering the actual values of mentioned parameters which are functional dependent on the number of equipotent lines, it is possible to obtain the following estimation of BDP-method speed up:
Q = [(0.2 x n)2 / W] + n + n + (n - 0.2 x n - 0.4 x n) =
= [(0.2 x n)2 / W] + 2.4 x n).
The speed-up benefit of proposed method is as higher, as less percentage of RFO in digital circuits.
Back trace superposition procedure is considered for treelike structue, fig. 11, where fault-free state line are represented in the brackets.
Fig. 11. Tree-like circuit
Vectors of own detectable faults for each primitive are represented in the first four lines of the following table:
1 2 3 4 5 6 7 8 9 L = L u Li ^ L n Li
. . . . 0 0 1 L4
0 - 0 .! L3
..00. . 1 .! L2
11... 0 . i L1
. . . . 0 0. 0 1iL = L4 u L3 ^ L4 nL3 = 0
. . . . 0 0. 0 1 L = L ^ L n L2 =0
1 1 . . 0 0. 0 1 L = L u L1 ^ L n L1 = 0
This lines (detectable fault vectors) are processed in according to back trace superposition procedure:
L = L Li ^ L n Li. The number of operation is n-1, where n is number ofprimitive in the circuit. Simulation oftest vector 00111 is represented as the vector of detected faults in the last line of mentioned table.
9. Conclusions
The offered fault simulation method is oriented on processing of complex digital devices implemented into PLD containing millions of gates. The program realization of the method was tested on several hundreds of combinational and sequential benchmarks and gave good speed-up results in comparison with classic parallel and deductive fault simulation algorithms. The results of speed analysis of three fault simulation methods are represented on fig. 13. The simulation speed-up was increased no less than 10 times. The length of applied test is 1000 patterns. The essential advantage of BDP-method in comparison with deductive-parallel is shown. The speed advantage of BDP-method is more efficient for the VLSI circuits. The number of RFO in samples is about 20% from the
number of lines. The absolute advantage of back-traced quasi exact method (see fig.13) is connected with decreasing adequate of RFO fault simulation. The main results of given work is improving of deductive-parallel method [1-3, 8] that consists in: 1) Creation of general deductive-parallel model of digital circuit analysis based on back-traced superposition procedure which requires the computation complexity linear depending on number of equipotent lines; 2) Algorithms development of structural and functional analysis of digital circuits with purpose of the RFO set definition and circuit structure reconfiguration for superposition procedure realization; 3) Creation of internal interpretative-compiled model of digital device.
-♦—Deductive-Parallel -■-Backtraced Quasi Exact —a—Backtraced-Deductive-Parallel
Figure 13. The speed analysis of 3 methods
The future investigations in area of digital circuit structure analysis for purpose of fault simulation speed up are:
1. Investigation of compensation and appearing of false faults for all existing types of triggers. 2. Theoretical proofs representing correct fulfilling of back-traced fault superpositionforFF-structure. 3. The RFO searching algorithm development via structure analysis for asynchronous circuits with the global feedbacks.
References: 1. Hahanov V.I., Babich A.V., Hyduke S.M. Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices, Proc. Euromicro Symposium on Digital Systems Design, Warsaw, Poland, 2001. P. 228-235. 2. Hahanov V.I., Haque HM. Jahirul, Masyd M.D. Mehedi. Fault analysis models of digital systems based on FPGA. Technologia i konsruirovanie v elektronnoi apparature, 2, 2001. P. 3-11. 3. Hahanov V.I., Sysenko I.Y., Haque HM. Jahirul.The Cubic Fault Simulation of Digital Circuit based on FPGA, Radio Electronics, informatics, management, 1, 2001, 123-129. 4. Levendel Y.H., Menon P.R.. Comparison of fault simulation methods - Treatment ofunknown signal values, Journal of Digital Systems. 1980. Vol. 4. P. 443-459. 5. AbramoviciM., BreuerM.A. and Friedman A.D., Digital System Testing and Testable Design (Computer Science Press, 1998). 6. Hahanov V.I. Technicheskaya diagnostika elementov i uzlov personalnih komputerov ,Kiev: IZMN, 1997. 308p. 7. Ubar R. The analysis ofdiagnostic tests for combinational digital circuits by fault back tracing methods, Automatica and Telemechanica, 8, 1977. P.168-176. 8. Semenets V. V., Hahanova I. V., Hahanov V.I. Digital systems design using VHDL language. Kharkov: KhNURE. 2003. 492 p.
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