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DECIDER: A SYSTEM FOR HIERARCHICAL TEST PATTERN GENERATION
JAAN RAIK, RAIMUND UBAR
Tallinn Technical University, Estonia
{jaan,raiub} @pld.ttu.ee
Abstract. A hierarchical test pattern generation system that uses register-transfer level VHDL and gate-level EDIF netlist descriptions as inputs is presented in current paper. The main novelty of the hierarchical ATPG tool lies in the fact that it implements internal representation ofmixed-level (register-transfer and structural levels) decision diagram models. The system includes appropriate interfaces to synthesize Decision Diagram (DD) models, a DD based test pattern generator and a fault simulator to evaluate the quality of the generated tests. In the paper, the structure of the system is presented. Additionally, representation ofdifferent design abstraction levels using decision diagrams is explained. The performance of the system is compared to other state-of-the-art tools for sequential circuit test generation. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time.
1. Introduction
As the degree of integration in VLSI designs has been growing over the years, so has the need for automation of different design tasks. Design automation helps to shorten the time-to-market cycle and increases significantly designer’s productivity. Automation was first introduced on the lower levels of design tasks, such as placement and routing, and together with the growth of design complexities, moved gradually to higher levels, e.g. logic synthesis, high-level synthesis (HLS) and hardware/software co-design. Nowadays the goal is clearly to automate the entire design cycle from conceptualization to generation of silicon layout [1].
During recent years, more-and-more high-level synthesis tools have become available. These tools are used by designers to automatically generate Register-Transfer Level (RTL) descriptions from design’s behavioral description. In the RTL descriptions the design is usually partitioned into a control part, i.e. a finite state machine, and a datapath part containing a network of interconnected functional units (FU). The HLS tools take into account several constraints, as speed, area, or testability, and allow the designer to quickly compare the trade-offs between alternative RTL implementations.
With the appearance of high-level synthesis, a number of automated test generation approaches [2,3] were introduced that took advantage of register-transfer level information while generating tests for gate-level faults. Current paper presents a hierarchical test generation system that operates on RTL and gate-level model descriptions. At present, the system utilizes Design Compiler [4] from Synopsys Inc. for logic-level synthesis. In Figure 1, the basic design flow and the place of test generation in it is shown.
Fig. 1. Design and test flow of hierarchical ATPG
Several techniques for solving the problem of generating tests for structural faults in sequential circuits have been proposed over the years. On the gate-level, a number of deterministic test generation algorithms [5, 6] have been implemented. However, the execution times are extremely long and for medium and large circuits mostly rather low fault coverages have been achieved. Better performance has been reported of simulation based approaches [7, 8]. The above approaches are fast for smaller circuits only and become ineffective when number of primary inputs and sequential depth of the circuit increase.
Test generation approaches [9, 10] that rely on functional fault models only do not guarantee satisfactory structural level fault coverages. As a solution, hierarchical approaches have been proposed which take advantage of high level information while generating tests for gate level faults. Recently, promising results based on software testing techniques combined with low level test have been published in [ 13 ]. The approach offers high fault coverages for small and medium sized benchmark circuits but the test generation takes relatively much time. Furthermore, the authors do not offer any formal method for generating the high-level test frames and the time needed to generate the frames has not been taken into account in the experiments.
Current paper presents an alternative, very fast high-level path activation technique of hierarchical test pattern generation. The approach is based on using Decision Diagram (DD) models where, differently from known methods, control unit and datapath are handled in a uniform manner. The speed-up of the technique is achieved by implementing simplified propagation and constraintjustification algorithms. The simplification can, in some cases, lead to decrease in fault coverage. However, as experiments show, for the given benchmark circuits this loss is minimal.
The paper is organized as follows. Section 2 gives an overview of the general structure of the DECIDER system. Section 3 provides for the concept of decision diagrams. In Section 4, the hierarchical test generation algorithm is presented. In Section 5, results are given and finally, conclusions are made.
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2. General Overview of the System
Figure 2 presents general structure of the DD-based test generation environment. It consists of DD interfaces from VHDL and EDIF formats, a hierarchical test pattern generator, a fault simulator and a number of libraries and scripts to support the DD synthesis. As an input for the system is design representation in RTL VHDL, where the circuit is partitioned into control and datapath parts. Similar representations can be synthesized by a HLS tool.
Additionally, two libraries of Functional Units (FU) are provided: one in VHDL and the other inDD format. The VHDL FU library describes the behavior of FUs that is necessary for the high-level synthesis tool to map the behavior of the circuit into a netlist of FUs specified in the library. The library is also used, along with the RTL VHDL model, during logic synthesis by Design Compiler. The DD FU library is required by RTL decision diagram synthesis tool to substitute the modules in the RTL model with corresponding decision diagrams.
information about achieved fault coverage. In order to measure the actual gate-level fault coverage of the generated tests, the test patterns have to be fault simulated on the structural level description of the whole device.
3. Decision Diagram Representations
Consider a system S = (F,N) as a set of components F represented by functions y = f(x) and a network Nconnecting these components. A component (sub-network) feF of a system S is described by a functiony=f(x) where y=(yi,-y„) and x=(x1,...xm) are vector variables. The functionfs defined on X=X1x...xXm with values ye Y = Y1x^.xY„, and both, the domainX and the range Y are finite sets of values. Here, xi, i
= 1,2,...,m, are input or state variables of the component/;
whereas yj , j = 1,2,...,...n, are output or next state variables. The values of variables may be Boolean, Boolean vectors, integers.
For representing the functions y=f(x) of components (or subnetworks) fOF we use decision diagrams Gy.
Design Compiler performs logic synthesis and writes out gate-level EDIF netlists of the whole design and of each FU separately. Dedicated scripts for automating these tasks have been implemented. Subsequently, the netlists are converted into Structurally Synthesized BDD (SSBDD) models. (The concept of SSBDD model representations is briefly discussed in Section 3).
The hierarchical Automatic T est Pattern Generator (ATPG) operates on the SSBDD models of the FUs and on the RTL DD model of the circuit. As an output the ATPG generates test patterns. However, the patterns do not offer precise
Logic Synthesis Scripts
Register-Transfer Level Model (VHDL)
Design Compiler (Synopsys Inc.)
Gate-Level Descriptions for the FUs (EDIF)
Definition 1. A Decision Diagram (DD) G is a directed noncyclic graph G=(M,G,x). Mis a set of nodes. G is a relation on M where G(m) M M denotes the set of successor nodes of meM. The nodes meMare marked by labels x(m). The labels can be: variables xi, algebraic expressions of xi, or constants. For nonterminal nodes m, where G(m) ^0, an onto function exists between the values of x(m) and the successors meeG(m) of m. me denotes the successor of m for the value x(m)=e.
Definition 2. The edge (m, me) which connects nodes m and me is called activated iff there exists an assignment x(m)=e.
Activated edges which connect mi and mj make up an activated path l(mi,mj). An activated path l(m0,mT) from the initial node m0 to a terminal node mT is calledfull activated path.
FU
Library
(DDs)
SSBDD Synthesis
Flattened Gate-Level Model of the DUT
SSBDD Models of FUs
RTL DD Model
SSBDD Synthesis
+
2L
Hierarchical ATPG
SSBDD Model of DUT
RTL Test Patterns
Test Pattern Converter
Gate-Level Test Patterns
Fault Simulation
RTL DD Synthesis Definition 3 Decision Diagram Gy =
(M,G,x) represents a function y = f(x) iff
for each value of x, a full path in Gy to a terminal node mT is activated, where x(mT)
=y.
A DD can represent a subnetwork of a datapath, and the output or next state logic of the control part. DDs can represent functions y = f(x) both on the RT and gate levels. On the gate level, y represents a binary variable and x is a binary vector. In this case we are dealing with binary decision diagrams (BDD). For representing a structure of a combinational circuit we use structurally synthesized BDDs (SSBDD) or alternative graphs [14].
Definition 4. A set of DD-s G(S) ={Gy} represent a digital system S = (F,N) if for each functiony=f(x) in Fthere exists a graph Gy = (M,G,x). The set G(S) ={Gy} is called the DD-model for the system S.
4. Hierarchical Test Generation on DDs
4.1 Concept of constraints
/ \
Gate-Level Fault Coverage of DUT \________________
Fig. 2. Data flow of the DECIDER system
The concept of test generation constraints is presented below. The path activation technique is explained basing on the following definitions. The set of all variables xS ofthe DD model G(S) can be viewed as a partition xS = xj u xR u xL u
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xO, where xj is the subset corresponding to inputs, xR is the subset corresponding to registers, xL is the subset corresponding to internal lines, and xO is the subset corresponding to outputs of the circuit, respectively.
Definition 5. A condition C = g(x), x c xS, where C is an integer, Boolean or symbolic value and g(x) is an expression on a subset of variables x of the DD model G(S) is refered to
as constraint.
Definition 6. A subset of variables x’ c x n xj in g(x) is called justified variables. On the other hand, the subset x \ x ’ in g(x) is refered to as the set of unjustified variables of the constraint, respectively.
Definition 7. Consider a constraint C = g(xI,...,xk, xj,..., x’l), where x ’i is the set of justified variables of the constraint. The process where variables xi, i =I,...,k in the expression g are replaced by other variables of the model G(S) is called updating the constraint. Updating the constraint C = g by replacing xk with a corresponding subexpression creates a new constraint C=g’(xI,..., xk-I, x”I,..., x”) where g’ can be viewed as a superposition of functions on a set of variables xS.
The constraints considered in current approach can be divided into two categories: path activation constraints and transformation constraints. Path activation constraints correspond to the logic conditions that have to be satisfied for the control part (FSM) in order to propagate symbolic values through the circuit. Transformation constraints, in turn, reflect the value changes along the activated paths. These constraints are necessary in order to calculate the local test patterns for the module under test. Both types of constraints can be represented by common data structures and manipulated by common procedures for creation, update, modeling and simulation.
4.2. Introduction to the path activation algorithm
Test generation for a component represented by a node m in graph Gy begins with the fault manifestation procedure. Two methods are used: scanning test generation (for terminal nodes) and conformity test generation (for nonterminal nodes). These methods are described in [15].
During the fault manifestation phase in graph Gy, fault effect symbol D is assigned to the function variable y, y = D. In addition, symbolic transformation constraints are created in form ofDi = xi, i = I,...,n, where n is the number ofvariables in the expression x(m) i.e. the number of inputs of the Module Under Test (MUT). Di are symbolic values representing local test patterns applied to corresponding inputs of MUT and xi are the variables of DD model G(S) representing the inputs of MUT.
F ault manifestation is followed by fault propagation.
During the propagation stage we move forward in time (clock-cycles), fault effect symbol D is propagated towards primary outputs and path activation constraints are created whenever conditions in the FSM have to be satisfied. Subsequent to propagation, constraint justification starts.
Justification moves
propagation ended. During this process existing constraints are updated and additional path activation constraints are created. Sections 4.3 and 4.4 explain on examples how the creation of path activation constraints during propagation and justification phases takes place. Updating constraints is discussed in section 4.4.
a
inputs pres. state next state outputs
in1 A B ...
... ... ... ... ...
1 1 2 1 1
0 1 1 0 X
X 2 3 1 1
1 3 4 1 0
0 3 1 0 X
... ... ... ... ...
b
Fig. 3. Circuit fragment
4.3. Fault effect propagation
The goal of fault propagation procedure is to propagate the fault effect D from MUT to a primary output of the device. During the process, the state sequence required to propagate D to the output is calculated and path activation constraints are created. In the following, the algorithm for fault effect propagation is presented and explained on a small example. Prior to the algorithm description, we introduce the definition of consistent FSM terminal node.
Definition 8. Let mT be a terminal node of the DD GF corresponding to the FSM. If the constant values of the vector variable x(mT) are consistent with previously made variable assignments then node mT is refered to as consistent FSM terminal node.
Table 1. Benchmark circuits
Circuit Gates Faults PIs POs Flip-flops FSM states
gcd 227 844 9 4 15 8
mult8x8 1058 3915 17 16 95 8
diffeq 4195 15,836 81 48 115 6
Table 2. Test generation results
DECIDER GATEST [3] HITEC [1]
F ault cover, % Time, s Fault cover, % Time, s Fault cover, % Time, s
gcd 89.6 1.2+0.6 91.0 75.0 81.1 195.6
mult8x8 73.3 6.8+20.4 69.2 821.6 65.9 1243.1
diffeq 96.0 9.7+85.4 96.0 4850 95.1 > 4 h
backwards in time, starting from the clock-cycle where
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Algorithm 1.
Let us denote by xi the variable where the fault effect has been propagated, xi = D.
While (xi does not correspond to a primary output)
{
Choose a datapath graph Gy containing a terminal node mT labeled by xi (or a function whose one ofthe arguments is x).
Activate a full path l(m0,mT) in graph Gy.
Create constraints Ci=x(mi), where mi are the non-terminal nodes along the path l(m0,mT) and Ci are the values of x(m) activating the path .
If (it is the first step of propagation^)
{
Let Gf be the graph corresponding to the FSM.
Choose a consistent FSM terminal mT from GF.
Activate a full path l(m0,mT) in graph GF.
}
else
{
Activate the path to node m labeled by state variable q in graph GF.
Let e be the present state value, i.e. q = e.
Let me be the successor node of m at this state.
If (me is a nonterminal node of GF)
{
If (exists a path l(me,mT) from node me to a consistent FSM terminal mT)
{
Activate the path l(me,mT).
Create constraints Ci=x(mi), where mi are the nonterminal nodes on l(me,mT) and Ci are the values of x(mi) activating the path .
}
else
{ Backtrack.}
}
} /* End If */
Fault effect has propagated to variable y corresponding to graph Gy. i.e.y = D.
Move to the next clock-cycle.
} /* End While */
The fault propagation algorithm described above is simple and fast. It activates the state sequence necessary for propagating the fault effect to primary outputs. No transparency rules for modules are applied and no exact calculation of the fault effect value is performed during the process. This helps us to avoid the detailed justification of values which have to be set in the datapath in order to create transparent paths through components [16]. The task of
justifying such values may lead to very high number of backtracks because of conflicts if datapaths with complex sequential structure are considered. On the other hand, this simplification may sometimes lead to lower fault coverage. According to experiments presented in Section 8, the overall speed of the proposed approach is very high while the loss in fault coverage, when it exists, is minimal.
A single step of the propagation algorithm is explained by the following example. Consider the circuit fragment depicted in Figure 3, where Figure 3 a shows a slice of datapath connected to a control unit and Figure 3b describes a part of the state table of the control part FSM. The DD representation of the circuit is presented Fig. 2a.
Let us assume that L is the variable in the model where the fault effect D has been propagated, L = D. We choose DD GY whose one of the terminal nodes is labeled by variable L and activate the path to that node. By doing that, we obtain variable assignments A=1, B=0, Y=D. Subsequently, in GF corresponding to the FSM, the path to node m labeled by state variable q is activated. Assuming that current state value is 3, we activate the path to the node m3 labeled by logical conditionM>N. We have to search for a terminal node mT in GF which is consistent with current control signal assignments (variables A and B represent control signals in our example). As an additional requirement it must be possible to activate a path l(m3, mT). In current example such node mT exists and the path l(m3, mT) is activated, resulting in the state variable assignment (for the next state) q=4. In addition, a constraint C=g(x) is created, where C is 1 and g(x) is M>N. In Figure 4a, all the paths which were activated during the propagation example are marked by bold arrows.
4.4. Constraints justification
As it was mentioned above, justification process starts from the clock-cycle where propagation finished. Justification traverses backwards the state sequence calculated by propagation phase until the clock-cycle of fault manifestation is reached. During this process, constraints previously created by propagation are updated. Starting from the clock-cycle of manifestation phase, a reverse state sequence is calculated, existing constraints are updated and additional constraints are created of the conditions in FSM that have to be satisfied. Note that at each clock-cycle, from all the created constraints only those are considered during justification that were created in a later clock-cycle than current one.
During the clock-cycles earlier than the manifestation, each justification step consists of three consecutive stages. These are selection of current objective, justification of the objective and updating ofexistingconstraints, respectively. Constraintupdating is explained at the end of current section, basing on an example.
Current justification objective is found as follows. If there exist unjustified variables in transformation constraints then justification objective will be to justify first such variable. Otherwise, currentjustification objective will be tojustfy the first unjustified variable in path activation constraints. Justification ends when there are no constraints left containing unjustified variables.
In the following, the algorithm for symbolic constraint justification is presented.
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Algorithm 2.
While (exist constraints with unjustified variables)
{
If (current clock-cycle is earlier than that of manifestation phase.)
{
Let current objective be to justify variable y.
Choose a terminal node mT from the graph Gy that calculates the value of y.
Activate a full path l(m0,mT) in graph Gy.
Update constraints by substituting y with x(mT).
Let Gf be the graph corresponding to the FSM.
If (exists consistent FSM terminal mT in GF)
{
Activate a full path l(m0,mT) in graph GF.
Let m be the node labeled by state variable q.
Create constraints Ci=x(mi), where mi N° m and mi are the nonterminal nodes on l(m0,mT) and Ci are the values of x(mi) activating the path.
}
Let current objective be to justify variable Y of a constraint C=g(x), YOx. We choose a terminal node mTfrom the graph GY that calculates the value of Y, and activate a path to that node. From the activated path we obtain variable assignments A=1, B=1.
We already know the state value of q calculated by previous justification step. Let us assume that it was q=2. Subsequently, we look for a terminal node mT in GF which is consistent with the above value assignments, where GF is the graph corresponding to the FSM. We activate the full path l(m0,mT) to the node mT in GF Activating this path gives us assignment q=1, which corresponds to present state value.
During eachjustification step all the unjustified variables in the constraints, that were created at a clock-cycle later than current time step, are updated according to present state and control vector. InFigure 4c DD representation ofthe fragment inFigure 3 is shown, which explains how the unjustified variables in the constraints are replaced by new ones during the update process. Let variable Yb e anunjustified variable in a constraint. Assuming that current state is equal to 2, values of the variables A and B in currently active control vector determine an activated path to the terminal node mT labeled by variable K in the DD corresponding to Y. Hence K replaces Y in all of the constraints containing Y.
5. Experimental results
else
{
Backtrack.
}
} /* End If */
Update all other constraints that were created at the later clock-cycle than current one.
Move to the preceding clock-cycle.
} /* End While */
An example in Figure 4b explains the justification process on DD model created fromthe circuit fragment shown in Figure 1.
In Table 1, main characteristics of the benchmark circuits are presented. Table 2 shows a recent comparison of test generation results of three ATPG tools. These are DECIDER, GATEST [7] and HITEC [5], respectively. GATEST is a genetic algorithmbased test generator. HITEC is a deterministic gate-level ATPG. Both of the tools have been developed at the University ofIllinois at Urbana-Champaign In[15] indirect comparison of results of the three test generators were published. In current paper, the tools are compared on the same hardware and exactly the same circuits for the first time.
The experiments were run on a 366 MHz SUN UltraSPARC 60 server with 512 MB RAM under SOLARIS 2.8 operating system. Actual stuck-at fault coverages of the test patterns generated by all the three tools were measured by the fault
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Fig. 4. Path activation on decision diagrams
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simulator from TURBO TESTER (TT) system, created at Tallinn Technical University, Estonia. The test generation times for DECIDER include both, test generation and exact evaluation of the gate-level stuck-at fault coverage by the TT fault simulator.
As it can be seen from Table 2, HITEC offers the poorest performance, both, in terms of fault coverage and test generation time on all the three example circuits. Fault coverages achieved by GATEST and DECIDER are almost equal. GATEST reaches 1.4 % higher fault coverage for the gcd circuit and only slightly better coverage for diffeq. DECIDER in turn has a 4.1 % advantage inthe case ofmult8x8 example. However, the test generation times of the two tools differ greatly. DECIDER spends 30 - 50 times less CPU time for test pattern generation process than GATEST, even if the evaluation oftest patterns by separate stuck-at fault simulator is taken into account. Though this must not be taken as a rule, for the chosen set of examples, the difference in speed tends to increase with the size of circuits.
6. Conclusions
In current paper, the role of hierarchical test pattern generation in an automated design cycle is explained. The general structure of a hierarchical test generation system, called DECIDER, is presented. In order to support automated test pattern generation for hierarchical systems, a number of diagnostic tools and appropriate interfaces have been implemented.
In addition, a hierarchical test generation method and its implementation based on using decision diagrams is described. DDs provide a joint description of structural properties, functions, and faults. Differently from known methods both, higher and lower design abstraction levels, and both, control and data paths are handled by uniform fault models and by uniform fault propagation procedures.
A novel concept of mixed-level combination of deterministic and simulation-based techniques in test generation is introduced. On the RT -level, deterministic path activating is combined with simulation-based techniques used in
constraints solving. The gate-level local test patterns for components are randomly generated driven by high-level constraints and partial path activation solutions.
The dramatic increase in the speed of test generation was reached by simplifying the fault propagation procedure, which in some cases may lead to lower fault coverage. For the givenbenchmark circuits, however, the loss in fault coverage was minimal.
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