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TEST PATTERN GENERATORS FOR PSEUDOEXHAUSTIVE TESTING
DERBUNOVICH L, SUZDAL V., SOBOLEV A., TATARENKO D.
Kharkov Natonal Polytechnic University, Ukraine
Abstract. Nanometer technologies present new challenges for test and test equipment. Designers can now place millions of transistors on a single chip and propagate a signal through them at speeds more than one gigahertz. More complex designs also pose problems for manufacturing and especially acute in test. Given the difficulties the test industry has gravitated toward using structured design for test, a methodology that falls into two broad categories: scan design and built-in techniques. In this report we assume that the sequential circuit has been designed according to the Level Sensitive Scan Design rules [1]. From a testing grand point it means that the testing problem has been reduced to testing the combinational section of the sequential circuit.
In recent years considerable attention has been given to pseudoexhaustive testing of a combination circuit. This approach involves applying all possible input patterns to all individual output cones. An output cone consists of all gates that feed the output.
Consider a combinational circuit with n inputs and m outputs. Let k be the number of inputs on which the any of “m” outputs depend. These three parameters: the number of inputs (n), outputs (m) and maximum dependency (k) among output cones, determine the size of pseudoexhaustive test set. Pseudoexhaustive testing of the circuit requires 2k patterns and provides applying exhaustive tests to the (m) output cones.
Several approaches to the pseudoexhaustive testing have been proposed. Pseudoexhaustive test pattern generators (TPG) are usually based on maximal length linear feedback shift registers (LFSR) [2]. An n-stage maximal length LFSR has a period of 2n-1 states and utilizes a primitive polynomial for its feedback connections. Universal pseudoexhaustive TPG generates test containing n-tuples that cover any “k” columns of the exhaustive test sets of all 2k possible patterns. This test sets can be generated by LFSR based on linear codes [4, 5] or constant weight codes [3].
Specific TPGs such as LFSR/SRs and LFSR/XORs can be designed for (n, m, k) circuit by using the knowledge of the circuit output cones [5, 7, 8]. An LFSR/SR consists of an LFSR and a shift register (SR) and canbe realized with low hardware overhead. However, the pseudoexhaustive test set generated by LFSR/SR is often significantly greater than the bound (2k). An LFSR/XOR is composed of an LFSR and an XOR gates and requires high hardware overhead. The TPG design procedures based on convolved LFSR/SR are presented in [7]. In this approach two concepts LFSR/SR and LFSR/XOR are merged. The single LFSR/SR ensures linear independence for all outputs. Circuit inputs assigned residues generated by successive cause linear dependencies for some output are avoided by using XOR gates.
In this report we present our TPG designs that generate pseudoexhaustive test by utilizing nonlinear feedback shift register (NLFSR) for the generation of full-length shift-register cycles, also referred to as de Bruijn sequences [9]. We propose algorithmic method of constructing full-cycles by using one-dimensional cellular arrays as the nonlinear feedback of the shift register [10, 11]. We have designed various pseudoexhaustive TPGs for examples of the combinational circuits frompapers [5, 6, 7, 8]. Forthese circuits TPGs utilizing NLFSR require less test size and hardware overhead.
References: 1. Bennets R.G. Design of Testable Logic Circuits. Addison Wesley Publishing Company, 1984. 2. Bardell P.H., McAnney W.H., Savir J. Built-in Test for VLSI: Pseudorandom Technincs. New York John Wiley & Sons, 1987. 3. TangD.T., Woo L.S. Exhaustive Test Pattern Generation with Constant Weight Vectors // IEEE Trans. Computers, vol. 32, no 12, pp. 1145-1150, Dec. 1983. 4. TangD.T., Chen C.L. Logic Test Pattern Generation Using Linear Codes // IEEE Trans. Computers, vol. 33, no. 9, pp. 845-850, Sept. 1984. 5. WangL.T., MacCluskey E.J. Condensed Linear Feedback Shift Register Testing - A Pseudoexhaustive Test Technique // IEEE Trans. Computers, vol. 35, no. 4, pp. 367-370, April 1986. 6. Barzilai Z., Savir J., Marnovsky G., Smith M.G. The Weighted Syndrome Sums Approach to VLSI Testing // IEEE Trans. Computers, vol. 30, no. 12, pp. 996-1000, Dec 1981.7. Srinivasan R., Gupta S.K., Breuer M.A. Novel Test Pattern Generators for Pseudoexhaustive Testing // IEEE Trans. Computers, vol. 49, no. 11, pp. 1228-1240, Nov 2000. 8. Barzilai Z., Coppersmith D., Rosenberg A.L. Exhaustive Generation of Bit Patterns with Application to VLSI Self-Testting // IEEE Trans. Computers, vol. 32, no. 2, pp. 190-194, Feb 1983. 9. Fredricken H. A Survey ofFull Length Nonlinear Shift Register Cycle Algorithms // SIAM Review, vol. 24, no. 2, pp. 195-221, April 1982. 10. Derbunovich L., Bohan V., Liberg I. Generator pseudosluchainyh chisel. Patent SU, No1377167, kl. HO3K/84, 1986. 11. Derbunovich L, Koss M, Temnikov I. Sintez legkotestiruemyh discretnyh ustroistv. Vestnik, Kharkov Polytechnical Institute, Avtomatika i priborostroenie, vol. 102, pp.46-51, 2000.
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