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Timoshkin Andrey Ivanovich, candidate of physical and mathematical sciences, professor National Metallurgical Academy of Ukraine
Ukraine, Dnepr E-mail: timoshkin1964@gmail.com
TESTABLE LOGICAL CIRCUIT OF A BINARY ARRAY MULTIPLIER IN NONSTANDARD BASIS
Abstract: In the information processing systems LSIs with regular structure (adders, substractors, array multipliers, array dividers and so on) perform increasable part. A testable functional - logical circuit of a binary array multiplier in nonstandard basis has been elaborated. The circuit being represented possesses a fault detection test of the length of three and a small hardware complexity.
Keywords: logical circuits with regular structure, stuck-at fault, fault detection test.
It is easier to design testable digital integrated where a and b are the values of the original 1-bit
circuits with a regular structure, including adders, multipliers, substractors, dividers, and various memory circuits, than integrated circuits with an irregular structure. The article [1] presents a testable functional logical circuit of a binary array multiplier with a fault detection test with a sequence length 5 for single stuck-at faults. However, its implementation requires a significant amount ofhardware resources, which is a major flaw. This article proposes a testable functional logical circuit of a binary array multiplier with a fault detection test with a sequence length 3 of the same fault class and with less hardware complexity.
Layers of 1-bit adders combined within each layer into parallel adder with serial transfer are the basis of this circuit. At the same time, the construction of a testable 1-bit adder circuit that underlies the multi-bit adder of each layer is based on the representation of the sum S and transfer P functions of a full 1-bit adder as polynomials dual to the Zhegalkin polynomials [2, p. 24] (since the sum S and transfer P functions are self-dual) and also on the fact that these polynomials for sum S and transfer P functions of a 1-bit adder are simple: P = (avb)G(av p)G(bv p),
S = aGbGP, (1)
operands; p and P are the values of the input and output transfer signals, respectively, S is the value of the sum signal, v is the symbol of the disjunction operation, Q is the symbol of the biconditional operation (equivalence).
The formula for the transfer function P from (1) can easily be converted to convenient form: P = (a v b) G[p v (a ©&)] = (a v b)G[p v (a Ob)] (2)
Then the testable logical circuit of the 1-bit adder can be implemented in a logical basis consisting of NOR and EQUIVALENCE two-input gates. This diagram is shown in (Fig. 1). At the same time, a rather simple schematic diagram of EQUIVALENCE gate on MOS transistors, containing only 3 transistors [3, p. 196], is known. This scheme is shown in (Fig. 2). The fault detection test for the 1-bit adder circuits in the selected basis for all single stuck-at faults contains 3 vectors and is described in table shown in (Fig. 1). Stuck-at-0 fault at the inputs of the EQUIVALENCE gate 5 are tested using the input vectors that feed the inputs of this gate with sets of «01» and «10», i. e. on the first and second input test vectors.
P a b s P
1 0 0 1 1 0
2 0 0 0 0 0
3 1 1 0 0 1
Figure 1. Testable 1-bit adder circuit and its fault detection test
Figure 2. Schematic of EQUIVALENCE gate in MOS transistors
The testable n -bit ( n is a positive integer) circuit of the binary adder of each layer of the array multiplier is composed of n testable circuits of a full 1-bit adder connected in a regular manner, i.e. by connecting the transfer output of i -th circuit with the transfer input of( i + l)-th circuit, where 1 < i < n -1. This circuit diagram is shown in Fig. 3. A fault detection test for a testable circuit of n -bit binary adder for all its single stuck-at faults is conducted by simply iterating the test shown in (Fig. 1).
The testable functional-logical circuit of a single-contact n x m bit array multiplier (where n is the number of multiplicand bits, m is the number of
multiplier bits) for array with n = 6, m = 4 is shown in (Fig. 4). This circuit, as well as the circuit of a conventional 6 x 4-bit array multiplier, contains three layers of adders and four layers of conjunctors. However, adder circuits are implemented using the above formulas. In addition, the considered circuit contains two additional two-input EQUIVALENCE gates and one additional input u . In this case, in the operating mode, the logical(O) signals are fed to the inputs c, u, pp p2, p3. The fault detection test for all single stuck-at faults of this circuit contains 3 vectors and is described in table shown in (Fig. 4).
Pi bi a1 b2 a2 b a3 Si S2 S3
0 1 0 1 0 1 0 1 1 1
0 0 0 0 0 0 0 0 0 0
1 0 1 0 1 0 1 0 0 0
Figure 3. Testable n -bit adder circuit and its fault detection test
u c Yi Y2 Y3 Y4 Y5 Y6 x1 X2 X3 X4 Pi P2 P3 z1 Z2 z3 Z4 z5 z6 Z7 Z8 Z9 zi0
1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0
2 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
3 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1
Figure 4. Testable circuit of 6 x 4-bit array multiplier and its fault detection test
The synthesis of the test sequence for the considered testable circuit of binary array multiplier can be carried out on the basis of a combination of formal and heuristic methods. First, a fault-detection test is created for the 1-bit adder circuit using formal methods (for example, using D - algorithm [4, p. 236]), and then, using this test as a basis, a general test sequence is built for the array multiplier circuit using heuristic methods. It is easily seen that in general, when n and m - are arbitrary positive integers, then testable functional logical circuit of a single-contact array multiplier contains m -1 adders with serial transfer, m, layers of conjunctors, as well as m - 2 additional two-input EQUIVALENCE gates. The number of additional inputs will not change and will remain equal to one.
The fault-detection test for the general case also contains 3 vectors and is constructed as follows:
- the sequence 1,0,1 (j e {1,2,...,n}) is fed to each y input;
- the sequence 0,1,1 (i e {2,3,..., m}) is fed to each x{ input;
- the sequence 1,1,0 is fed to each x1 input;
- the sequence 0,0,1 (k e {1,2,..., m -1}) is fed to each pk input;
- the sequence 0,1,0 is fed to u input, and the sequence 1,0,0 is fed to c input.
The study found that the algorithm for constructing of a fault detection test for the proposed circuit is much simpler than the algorithm for constructing a fault detection test for the circuit found in [1]. The testable circuit found in [1] is also requires significantly bigger amount of hardware resources for its implementation than the proposed testable circuit.
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