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11
Timoshkin Andrey Ivanovich, candidate of physical and mathematical sciences, professor, National Metallurgical Academy of Ukraine E-mail: timoshkin1964@gmail.com
ON ONE XOR CIRCUIT
Abstract: The article analyses the topological realization of the XOR circuit, which allows detect ing all its stuck-at faults by fault detection test with two test-vectors.
Keywords: Basic-circuit arrangement, stuck-at fault, fault detection test.
The article [1], at the functional-logical level, de-
scribes the method of realization of linear Boolean functions that essentially depend on all its variables [2, p. 11], in the form of tree-structured circuit, 2-verifiable (i.e., possessing verification tests with sequence length 2 for single stuck-at faults on their signaling lines. At the same time, 2-testable tree-structured circuits were built from three-input XOR gates, which are 2-testable for single stuck-at faults at their inputs and outputs.
However, the 2-testability of the functional gate for stuck-at faults at the inputs and the output (or external signaling lines) does not guarantee its 2-test-ability for all its stuck-at faults. An analysis of the basic-circuit arrangement of the three-input XOR gate showed that stuck-at faults in most of its internal signaling lines are not detected by a test with sequence length 2 for stuck-at faults on external lines. All this creates a problem of finding such constructive realization of the XOR gate, which would ensure its full 2-testability (for single stuck-at faults), and therefore complete 2-testability of tree-structured circuits using it as basis.
This article proposes a circuit diagram of the XOR gate, 2-testability for all its single stuck-at faults. The proposed 2-testability for all single and multiple stuck-at faults of the three-input XOR gate is based on S1 basic-circuit arrangement with n -MOS-transistors as its basis, described in [3, p. 177]. Its diagram is shown in Fig. 1. At the paraphase output of the considered circuit, the values of functions
x1 © x2 © x3 and x 1 © x2 © x3 are simultaneously formed, which allows building multilevel tree-structured circuits with implemented linear Boolean functions without using inverters.
Figure 1. S1 diagram
Q1 test of sequence length 2 shown in Table 1 detects singular stuck-at 0 and 1 faults (i.e., stuck-at " = 0 " and " = 1" faults) at the input lines a, b, c, d, e, f and on the output lines s and t of this circuit. In addition, this test detects a single stuck-at 1 fault at the input lines g, h, p, and q. The single stuck-at 0 fault at the input lines g, h, p, and q is not detected by this test. Therefore, in order to solve the problem denoted in this article, it is necessary to modify the original circuit in such a way as to ensure that the stuck-at 0 faults on the g, h, p, and q lines are detected by the test.
ON ONE XOR CIRCUIT
Table 1.- Q1 test
— — — —
x1 x1 X 2 x 2 x 3 x 3 u u
1 0 1 0 1 0 1 0
0 1 0 1 0 1 0 1
Ifwe combine transistor gates T and T2 into one the aforementioned procedure for transistors T3 and
gate at the constructive (topological) level, and re- T4, T5 and T6, T7 and T8, and, by replacing a part of
lated input signaling lines b and g into one signaling metal couplings with diffusive couplings. In this
line, then stuck-at 0 and 1 faults on this line will be case, we advise to use polysilicon as a material for
detected by the test , shown in Table 1. Topology transistor gates T1 and T2, T3 and T4, T5 and T6, T7
of circuit S2 shown in Fig. 2 is created by executing and T8.
Figure 2. S2 diagram
All physical defects of circuit S2, shown in the faults such as source-drain short circuiting [4] of all single stuck-at faults model are detected by the test functional transistors of the considered circuit. Q1. The test also reveals some typical MOS-circuit
Table 2. Q test
х1 х; х 2 х 2 х 3 х 3 u u
1 0 1 0 1 0 1 0
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
Replacing metal couplings with diffusive couplings allows one to significantly reduce the likelihood of such faults as open fault in the sources and drains of transistors T, T2, T3, T4, T5, T6, T7 and T8. Open faults in drains and sources of transistors T9
References:
and T10 are consistently detected by Q2 test, consisting of 3 vectors and described in (Table 2). This test also detects all single ac fault (delays) at the inputs and outputs of S2 circuit.
1. Тимошкин А. И. О реализации линейных булевых функций 2-проверяемыми древовидными схемами // Радиопромышленность. 1995.- № 3/4.- С. 90-95.
2. Яблонский С. В. Введение в дискретную математику.- М.: Наука, 1986.- 384 с.
3. Мурога С. Системное проектирование сверхбольших интегральных схем. Кн. 1.- М.: Мир, 1985.288 с.
4. Вейцман И. Н., Кондратьева О. М. Тестирование КМОП-схем // Автоматика и телемеханика. 1991.- № 2.- С. 3-34.
