CC BY
14
Timoshkin Andrey Ivanovich, candidate of physical and mathematical sciences, National Metallurgical Academy of Ukraine
Ukraine, Dnepr E-mail: timoshkin1964@gmail.com
TESTABLE DUAL-CHANNEL CIRCUITS OF DIGITAL COMPARATORS
Abstract: The article presents testable dual-channel logical circuits of digital comparators. These circuits intend for implementation as printed circuit board assemblies.
Keywords: testability, dual-channel digital comparators, printed circuit board assembly.
It is known fact that the functional testing and diagnosis of faults in printed circuit board assembly of communications electronics (CE) is one of the longest and most labor-intensive stages of their production and operation [1]. The issue of duration of functional testing of printed circuit board assemblies and CE units, as well as labor intensity can be alleviated by increasing their testability.
A prospective approach in the testability improvement of digital printed circuit board assemblies and CE units is described in [2]. This approach is based on the modification (as a rule, the complication) of basic logic gates and the synthesis of testable logic circuits using those gates.
This article presents two testable dual-channel (paraphase) logical circuits of digital comparators, synthesized according to the considered approach and intended for implementation as the printed circuit board assemblies. AND, OR, IDENTITY and XOR special functional gates of two-channel logic are used to draw these circuits, which are implemented as separate monolithic [3] integrated circuits. Special dual-channel functional gates AND and OR are gates of dual-channel tree-structured circuits S1 and S2, enclosed in rectangles 1, 2, ..., n - 1 (where n is an even number), respectively in (Fig. 1 and Fig. 2).
EQUIVALENCE and XOR special dual-channel functional gates, enclosed in rectangles, are shown respectively in (Fig. 3 and Fig 4).
Figure 1. S1 diagram
Figure 2. S2 diagram
Figure 3. EQUIVALENCE gate
Figure 4. XOR gate
The main feature of these four types of gates, which distinguishes them from ordinary gates of dual-channel logic architecture [4], is that they possess fault detection tests with a sequence length 2 for single and multiple stuck-at-faults at their inputs and outputs. The structure of these tests for AND and OR gates is the same and is shown in (Table 1).
Table 1.- Fault detection test for AND and OR gates for single stuck-at faults at their inputs and outputs
z1 z 2 z f fl g 1 gl
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
The structure of the above mentioned tests for EQUIVALENCE and XOR gates is also the same and is shown in (Table 2).
Table 2.- Fault detection test for EQUIVALENCE and XOR gates for single stuck-at faults at their inputs and outputs
x1 jq x 2 X2 h h S S
1 1 0 0 1 0 0 1
0 0 1 1 0 1 1 0
For brevity sake, hereinafter these functional faults contain five vectors each, and are shown in gates will be called 2-testable. Full fault detection Table 3 and Table 4 respectively. tests for these functional gates for single stuck-at
Table 3.- Full fault detection test for AND and OR gates for single stuck-at faults
z1 z z 2 ¿2 f f g 1 gl
1 0 0 1 0 1 1 0
0 1 1 0 0 1 1 0
1 1 0 0 1 0 0 1
0 0 1 1 1 0 0 1
1 0 1 0 1 0 1 0
Table 4.- Full fault detection test for EQUIVALENCE and XOR gates for single stuck-at faults
X1 X1 X 2 X2 h h S S
0 1 0 1 0 1 1 0
1 0 1 0 0 1 1 0
1 1 0 0 1 0 0 1
1 0 0 1 1 0 0 1
0 1 1 0 1 0 0 1
Necessary and sufficient conditions for 2-test-ability of functional gates of dual-channel logic structure for single stuck-at faults at their inputs and outputs, as well as tree-structured circuits for single stuck-at faults of signaling lines, were discussed in [5]. Tree-structured circuits S1 and S2, that implement AND and OR functions of dual-channel logic structure dependent on n pairs of variables (ZpZl); (Z2,Z2); ( Zn,Zn) are 2-testable for single and multiple constant faults of signaling lines not belonging to their dual-channel gates according to these conditions. (AND and OR dual-channel gates of these circuits, as already noted, are enclosed in rectangles). These signaling lines ate the interconnections of the printed circuit board assemblies.
Testable dual-channel logical circuits of digital comparators are shown in (Fig. 5 and Fig. 6).
Figure 6. Testable dual-channel logic circuit of a digital comparator. Option 2
They are created by connecting the inputs of the tree-structured circuits S1 and S2 to the outputs of parallel units from the dual-channel EQUIVALENCE and XOR gates, respectively.
Fault detection tests for testable dual-channel digital comparator circuits for single and multiple stuck-at faults of signaling lines corresponding to printed circuit board assemblies interconnections, consist of two vectors and are shown in (Table 5).
These tests also detect faults of more than half of AND- and OR-conduits of interconnections of the printed circuit board assemblies under consideration.
Figure 5. Testable dual-channel logic circuit of a digital comparator. Option 1
Table 5.- Fault detection tests for testable dual-channel digital comparator circuits for single and multiple stuck-at faults in their signaling lines
*1 y 2 y2 ... xn Xn yn F F P P
1 1 0 0 ... 1 1 0 0 1 0 1 0
0 0 1 1 ... 0 0 1 1 0 1 0 1
Finally, it should be noted that the presented testable logical circuits of digital comparators are self-testable for single and unidirectional multiple of interconnect faults of their printed circuit boards assemblies, since all of the noted faults occur at F, F
or P, P outputs as pairs of values of 00 or 11. (Unidirectional multiple stuck-at fault is a multiple fault, in which all its components are single stuck-at faults of the same type: "1" or "0".)
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