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SYNTHESIS OF SEQUENTIAL CIRCUITS ON PROGRAMMABLE LOGIC DEVICES BASED ON COMMON MODEL OF FINITE STATE MACHINE
ADAMKLIMOWICZ, VALERYSOLOVJEV
aklim@ii.pb.bialystok.pl, walsol@ii.pb.bialystok.pl
Abstract. In this paper, a new method of synthesis of finite state machines (FSM) is presented. This method uses the features of modern programmable logic devices (PLD), such as, the possibility ofusing combinatorial and buffered inputs and outputs and registers in feedbacks of PLD. An efficiency of this method is basing on joining in the one structure different FSM models, such as: class A, class D and class E models. This fact allows to level disadvantages of separate FSM models. There are presented experimental results which are compared to results obtained from other known methods and obtained from the Max+Plus II design system.
1. Introduction
Programmable Logic Devices (PLD) is widely usedforbuilding many digital systems. Most of systems include finite state machines in their structure, so there is important thing to find most efficient algorithms of a synthesis of this circuits. The state assignment is the main problem in the design FSMs on PLD devices. There are many methods proposed, such as two-level symbolic minimization methods [3,4], which are developed in the NOVA application [14] and multilevel synthesis methods for example implemented inthe MU STANG program [5]. On the other hand there are a lot of other methods, for example: genetics algorithms [2], which give good results in the FSM synthesis.
Foregoing methods have some disadvantages, because they don’t take into consideration the specific features of modern PLD devices. New FSM’s models were proposed in [9-11] These models are called class A, B, C, D, E and F machines, where class A corresponds to Mealy’s machine [7] and class B to the Moore’s machine [8] In this paper the common model of class A, D and E FSM is considered. This model j oins class A, class D and class E models in the one structure, that allows to use the best features of these models and to level their disadvantages. Presented model takes into consideration features of modern PLD structures such as the possibility of using combinatorial and buffered inputs and outputs and registers in feedbacks of PLD.
The paper is organised as follows. In section 2, the used model of FSM is described. The synthesis algorithm and the state assignment algorithm are presented in section 3. Experimental results are presented in section 4. Section 5 concludes this paper.
2. Structure of the common model of FSM
Proposed model of FSM is generally the Mealy’s machine, because output functions depend on the present state and the input vector. The structure of the machine contains the models of three FSM, which are described as follows:
a) the class A FSM (the Mealy’s machine)
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at+i = 9 ( zt, at); wt = V ( zt, at); ( 1 )
b) the class D FSM (every output vector is the same as corresponding code of the next state)
at+1 = 9 ( zt, at); wt = at+1; ( 2 )
c) the class E FSM (every input vector is the same as corresponding code of the next state)
at+1 = 9 ( zt, at); wt = V ( zt, at); ( 3 )
where: at - the current state of machine, at+1 - the next state of machine, zt ,wt - input and output vectors, 9 - the transition function, V - the output function.
The structure of the common model of FSM classes A, D and E is presented in fig. 1, where CL is the combinatorial logic, RGI is the input register, RGO is the output register and RG is the internal register. They save codes of machine states accordingly: E, D and A. Contents of input register RGI are defined by the input vector from the set X = {x1,...,xL}, contents of the output register RGO are defined by the output vector from the set Y = {y1,...,yN} and contents of internal register RG are defined by values of the transition functions vector from the set D={d1,...,dR}. Internal state codes of machines are defined by variables form sets G={g1,. ..,gL}, Z = {z1,...,zN} and E = {e1,...,eR}, formed on outputs of registers accordingly: RGI, RGO and RG.
Fig. 1. The structure of the common model of FSM of classes A, D and E
In the common model of FSM the set of states is considered as a sum of subsets Aa, Ad i AE related to states of machines A, D and E classes accordingly. In the general case the intersection of these subsets is allowed. Individual subsets features are shown below:
AA - the set of that machine states, such that on the transitions from the one state to other can be formed different output vectors,
AD - the subset of AA, contains states, such that on the transitions to any state from the set AD there can be formed the only one, the same output vector, which doesn’t appear on transitions to other machine states,
AE - the subset of AA, contains states, such that any transition to any state from the AE set is caused by the same input vector of conditions, which doesn’t appear on transitions to other machine states.
3. The metho d of synthesis
Let FSM be described by a state transition table, which consists of four columns am, as, X(am,as), and Y (am,as), where am is the current state, as is the next state, X(am,as) is the input vector, and Y (am,as) is the output vector. One line in the state transition table corresponds to one FSM transition.
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The synthesis of the common FSM model is based on state assignment algorithm and state splitting algorithm (main synthesis algorithm). They are described as follows.
3.1. The state assignment algorithm
The essence of the state assignment in this method, depends on making all states different from each other, i.e. all state codes must be orthogonal. Using for the state assignment input and output variables from G and Z sets, partially leads to solving of this problem. Next steps lead to inserting of a minimal number of the additional variables ei,...,eR, from the set E and to the assignment of binary codes to separate groups of states.
There is constructing the Boolean matrix W to solve the state assignment problem. Rows of the matrix W are corresponding to FSM states and columns are corresponding to variables from sets G and Z. On the intersection of a row corresponding to the state a!, ai e A and a column corresponding to the variable gj, gj e G, must be put the one if the input variable Xj belongs to the conditional vector X(ad in a non-inverted form, the zero - an inverted form, and the “don’t care” value (‘-‘) if the xj doesn’t influence the transitions to the state a;. The value of X(aO is determined as way as follows: if all of transitions to state a;, ^ e A take place under the influence of the same input vector X(am,ai), then X(ai) := X(am,ai), else X(ai) = 0 (empty set). On the intersection of a row corresponding to the state ai, ai e A and a column corresponding to the variable zj, z_j e Z must be put the one ifyj e Y(ai), the “don’t care” value if Y(ai) = 0 , and the zero in every other case, where Y(ai) - the subset of output variables, equal to one in transitions to state ai. Value ofY(ai) is determined as way as follows: if on all transitions to state ai, ai e A, is formed the same output vector Y(am,ai), then Y(ai) :=Y(am,ai), in other case Y(ai) := 0 .
When the matrix W was created there must be entered a number of R additional variables ei,...,eR, and rows of matrix W must be coded by that method, which makes all of rows from the matrix orthogonal to each other. To solve this problem there must be created the graph of orthogonality H of the matrix W rows, i.e. states of the FSM. Two vertices number i and j of the graph H are connected, if rows number i and j of the matrix W are orthogonal to each other. The next part of this problem follows to searching in the graph H for the minimal number T of full subgraphes Hi,... ,HT, which have all vertices connected to each others and an assignment of binary codes to all subgraphes determined by values of variables e1,...,eR. For this method the following algorithm is proposed:
Algorithm 1 (of a state assignment)
1. Create the graph of orthogonality H ofthe matrix W rows.
2. From the graph H delete all vertices connected with all others vertices of graph. That means that appropriate rows of matrix W are orthogonal with all other rows).
Set t:=0.
3. Set t: =t+1. In the graph H find the maximal full subgraph Ht.
4. From the graph H delete all vertices that belong to the subgraph Ht. If set of graph’s vertices is empty then go to the step 5, else - go to the step 3.
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5. Determine the parameter R as a number of additional variables e1,...,eR, R=int log2T, where T is a number of all full subgraphes.
6. For all of subgraphes Ht, determine the value Ct, as follows:
Ct = Z |C(ai)|, ( 4 )
aieAt
where At - the set of the machine states, corresponding to
vertices of the subgraph Ht ,t=1,T, C(ai) - the set of all of transitions to the state ai, ai e A.
7. For each subgraph Ht, t=1,T, assign a binary code, determined by values of variables e1,...,eR. Binary vectors with a minimal number of ones assign to subgraphes with the maximal Ct value.
8. Insert to the matrix W additional columns corresponding to variables e1,...,eR. Values of the columns are the codes assigned to subgraphes.
9. Specify the machine state codes such as the code K(ai) of the state ai, ai e A, is equal to the contents of the row i of the matrix W. If on the intersection of the row number i and the column number j, is one, then the variable corresponding to the columnj belongs to the code K(ai) of the state ai in a noninverted form, if the zero value, then in a inverted form, if the “don’t care” value then the variable doesn’t belong to the code K(ai).
10. End.
Notice that the execution of steps 6 and 7 of this algorithm leads to a simplification of a realization of register input functions from the set D on PLD devices.
3.2. The main synthesis algorithm
Using of the common model of the FSM classes A, D and E in a synthesis leads to two main aims:
a minimization of the parameter R (a number of additional registers),
a simplification of transition and output functions, i.e. a combinatorial part of FSM.
Both of that aims are realized by the way of taking an advantage of D and E classes FSM models. But abusing of these models, can lead to an increase of an number of FSM state table rows and to a creation of more complex transition and output functions as a result of the state splitting. The state splitting has a sense only if it leads to a decrease of the parameter Rvalue. In the following algorithm the state splitting is cancelled if it leads to a increase of R value. The solution which last time led to a decrease R value is taken as the final result.
Let V(ai) be the set of output vectors formed on transitions to the state ai, ai e A.
V(ai) = { Y(am,ai) | ame B(a() }, ( 5 )
where B (ai) is the set of states, from which there is possibility to go into the state ai. The state ai, ai e A, is the FSM class D state, i.e. ai e AD, ifthere are performed following conditions:
I V(a) | = 1 ( 6 )
and
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V(a) n V(aj) = 0 ( 7 )
for i^j for each aj e A.
If the condition (6) is performed then the same set of output vectors on all transitions to the state ai is formed. Condition (7) ensures, that the output vector Y(ai) isn’t formed on transitions to other FSM states.
Let VD(ai) be the set of output vectors formed on transitions to other states i.e. VD(ai) - the subset of the set V(ai), VD(ai) c V(ai), where there are performed conditions (6) and (7). Let A*d be the set of states where isn’t performed the condition (6), i.e. states, which must be split to gain the class D machine states.
Let U(ai) be the set of all condition vectors of the transition into the state ai, ai e A. The state ai is the class E machine state i.e. ai e AE, if there are performed following conditions:
I U(ai) | = 1 ( 8 )
and
U(ai) n U(aj) = 0 ( 9 )
for i^j for each a_j e A.
Let UE(ai) be the set of condition vectors of transitions into the state ai, which doesn’t appear according to transitions to other FSM states, i.e. there is performed the condition (9), UE(ai) c U(ai), and let A*E be the set of states where the condition (8) isn’t performed, i.e. the set of states, which must be split to gain the FSM class E states.
Let S(ai) be the cost parameter of splitting the state ai specified as a number of additional rows in the FSM transition table gained as a result of the state ai, aie A*D u A*E splitting.
S(ai) = |V(ai) - 1| • |P(ai)|, if ai e A*d; ( 10 )
S(ai) = |U(ai) - 1| • P(ai)|, if A*e;
where P(ai) is the set of transitions from state ai. In the process of a synthesis the choice of the proper S(ai) value depends on the method of splitting: using output vectors (ai e A*D) or using input vectors (ai e A*E). The algorithm of a synthesis of the common model of Mealy’s FSM classes A, D, and E is shown below:
Algorithm 2 (of a synthesis)
1. Set R* := 1000.
2. Construct the state assignment matrix W, perform the algorithm 1 (of the state assignment), as the result gain the parameter R value.
3. If R i R*, the go to the step 7, else set R*:= R and save results of the synthesis (FSM transition table and codes of states).
4. Determine sets V(ai), VD(ai), U(ai) and UE(ai), ai e A and sets A*d and A*E. If A*D u A*E = 0 then go to the step 7, else go to the step 5.
5. Select the state ai, ai O A*D u A*E to split, according to following criterions:
a) max(|VD(ai)| , | Ue^)=max
b) | S(ai)| = min.
The first criterion ensures a highest efficiency of using FSMs of classes D and E, the second criterion ensures a minimal increase of the FSM transition table lines.
6. Split the state ai, chosen in the step 5 of the algorithm. If | VD(ai) | > | UE(ai) |, then splitting is performed using output vectors V(ai), else - using input vectors U(ad. Go to the step 2.
7. Accept the solution saved in the step 3 as the final result of a synthesis.
8. Determine Boolean equations of the realized transition and output functions.
9. End.
Notice that if |VD(ai)| = |UE(ai) | then splitting of the state ai is performed using the set of output vectors, because it allows to obtain orthogonal rows of the matrix W with a greater probability. In the beginning of the algorithm 2 the R* value must be set greater than it is necessary, so the state assignment and saving results are performed at least one time.
In the case when AD = AE = A*D = A*E = 0 , performing of the algorithm 2 is the same as the synthesis of the class A Mealy’s FSM.
4. Experimental results
The proposed synthesis algorithm has been implemented in a package called ZUBR. The package ZUBR is developed on Faculty of Computer Science of Bialystok University of T echnology. The proposed algorithm of synthesis of common model FSM on PLD was used on the benchmark examples from the suite developed in MCNC [15].
The efficiency of synthesis method of common model machine was compared with synthesis of A-class machine for realization on PALCE26 V12 device. Each macrocell of this device has 16 product terms connected. This device allows to configure macrocells with the register infeedback. Results of comparison are shown in table 1, where L is number of inputs, N - number of outputs, P - number of lines in FSM transition table, M -number of states, RA and CA are number of memory elements in feedbacks and number of used for class-A model, RC and CC are the same parameters for common model, parameter
A C= Ca - Cc.
Table. 1. Comparisons between realizations of class-A model and common model of FSM
Name L N P M Ra Ca Rc Cc AC Ca /Cc
Bbsse 7 7 208 13 4 11 3 10 1 1,10
ex4 6 9 21 14 4 13 3 12 1 1,08
Keyb 7 2 170 19 5 11 4 8 3 1,33
Mc 3 5 10 4 2 7 0 5 2 1,40
Pma 7 6 44 20 5 24 3 21 3 1,14
s1 8 6 107 20 5 17 0 6 11 2,83
S27 4 1 30 5 3 4 2 3 1 1,33
S298 3 6 681 135 8 69 7 63 6 1,09
S386 7 7 64 13 4 11 3 10 1 1,10
Average 1,38
Analysis of obtained results shows that in every case a number of additional memory elements R is reduced. A number of macrocells needed for realization is 1,38 times lower if the common model of FSM is used instead of class-A model.
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Table 2 shows results of comparison of realization of common model machine and algorithms used in Max+Plus II system,
Table 2. Results of synthesis of common model of FSM compared to Max+Plus II system
Name Cm1 Cz1 CM1/CZ1 Cm2 Cz2 C21/CZ2
beecount 11 6 1,8 37 9 4,1
Dk14 12 11 1,1 75 39 1,9
Dk17 7 6 1,2 35 23 1,5
Ex2 16 12 1,3 45 37 1,2
Ex3 8 4 2,0 22 9 2,4
Ex5 12 4 3,0 23 8 2,9
Ex7 10 4 2,5 20 4 5,0
keyb 27 13 2,1 102 72 1,4
lion9 7 3 2,3 23 5 4,6
s1 48 11 4,4 122 35 3,5
s27 4 3 1,3 40 9 4,4
shiftreg 4 3 1,3 10 3 3,3
train11 7 2 3,5 24 6 4,0
train4 3 2 1,5 6 4 1,5
Average 2,1 3,0
where CMJ, CM2 are numbers of used macrocells for Max+Plus II synthesis methods for CPLD families MAX 9000 and FLEX 10K accordingly; CZJ, CZ2 are numbers ofused macrocells for realization of common model FSM applied to Max+Plus II for the same devices accordingly.
The method of synthesis of common model of FSM allows to reduce a number of used macrocells in comparison with MAX+PLUS II, on average, 2,1 times for MAX 9000, and 3 times for FLEX 10K.
5. Conclusions
The method of synthesis of common model of FSM classes A, D and E was presented. Presented algorithm was more effective than traditional Mealy’s model. It needs lower number of used macrocells for realization of combinatorial part ofFSM and lower number of additional memory elements. Experimental results show efficiency in comparison with industrial package MAX+PLU S II.
There are some limitations for proposed algorithm. Applied PLD structure must have specific features as flip-flops in feedbacks, and possibility of using combinatorial and registered inputs and outputs of PLD at the same time.
Future research work should take into consideration other common models ofFSM, i. e. class A and D common model of Mealy’s FSM and class B and F common model of Moore’s
FSM. Variety of currently used programmable devices causes necessity of working out new methods of selection of synthesis method which should be applied to specific programmable device.
References: 1. AvedilloM., Quintana J., Huertas J. State merging and splitting via state assignment: a new FSM synthesis algorithm, IEE Proceedings. Part E, Computers and Digital Techniques, vol. 141, No. 4, July 1994. P.229-237.2.AlmainiA., MillerJ., Thomson P., BillinaS. State assignment offinite state machines using a genetic algorithm, IEE Proceedings, Part E, Computers and Digital Techniques, vol. 142, no. 4, July 1995. P. 279-286. 3. DeMicheli G. Symbolic design of combinational and sequentional logic circuits implemented by tow-level logic macro s, IEEE T rans. on Computer-Aided Design, vol. CAD-5, Oct. 1986. P. 597-616. 4. DeMicheli G., BraytonR.K., Sangiovanni-VincentelliA. Optimal state assignment for finite state machines, IEEE Trans. on Computer-Aided Design, vol. CAD-4, July 1985. P. 269-285. 5. Devadas S., Ma H.-K., NewtonR., Sangiovanni-Vincentelli A. MUSTANG: State Assigment ofF mite State Machines T argeting Multilevel Logic Implementations, IEEE Transactions on Computer-Aided Design, Dec 1988, Vol. 7. No. 12. P. 1290-1300. 6. MAY+PLUSII Programmable Logic System, Altera, 1992. 7. Mealy G.H. Method for synthesizing sequential circuits, Bell System Techn. Jourhal, vol. 34, 1955. P.1045-1079. 8. Moore E.F. Gedanken-experiments on sequential machines, In C.Shannon and J.McCarthy editors. Automata Studies, Princeton University Press, 1956. P.129-153. 9. Solovjev V. Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines, Proc. of the EUROMICRO Symposium on DIGITAL SYSTEMS DESIGN (DSD’2001), September 4-6,2001, Warsaw, Poland. P. 170-173. 10. Solovjev V. Design of digital systems based on Programmable Logic Devices, Hot-Line Telecom, Moscow2001.636 s. 11. Solovjev V., Chyzy M. Models of the finite state machines, Proc. of the Sixth Int. Conf. on Methods and Models in Automation and Robotics (MMAR 2000), 28-31 August 2000. Miedzyzdroje, Poland, Vol 2. P. 909-914. 12. Solovjev W., BulatowaI. Synthesis ofD-class Finite State Machines on Programmable Logic Devices, in Proc. Of the 3rd International Workshop on Computer Science and Information Technologies (CSIT-2001) Ufa, 2001, Vol. 1. P. 164-170. 13. Sentovich EM, Singh K.J., Lavagno L., Moon C., Murgai R., Saldanha A., Savoj H., Stephan P.R., Brayton R.K., Sangiovanni-Vincentelli A. SIS: A system for sequentional circuit synthesis, Memorandum No. UCB/ ERL M92/41, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkley, May 1992. 45p. 14. Villa T., Sangiovanni-Vincentelli A. NOVA: State Assignment for Finite State Machines for Optional Two-Level Logic Implementation, IEEE Trans. on Computer-Aided Design. Sept. 1990. Vol. C-9. PP. 905-924. 15. Yang S. Logic synthesis and optimization benchmarks user guide. Version 3.0., Technical Report, Microelectronics Center of North Carolina, 1991. 43p.
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