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КОМПЬЮТЕРНАЯ ИНЖЕНЕРИЯ И ТЕХНИЧЕСКАЯ ДИАГНОСТИКА
УДК 519.714.5
IMPLEMENTATION OF CONCURRENT LOGIC CONTROLLERS BASED ON DECOMPOSITION
INTO STATE MACHINE COMPONENTS
MAREK WEGRZYN, AGNIESZKA WEGRZYN * 1 2
The main aim of this paper is to demonstrate a practical application of the Petri net decomposition algorithm based on finding deadlocks and traps. Obtained in such decomposition Concurrent Digital Systems represented by set of State Machine components are implemented using Programmable Logic. The experimental results have shown that presented approach may produce economical implementations of dedicated Application Specific Logic Controllers. Petri nets are considered as formal models as well as intermediate models for hardware descriptions in Verilog-HDL that are used for synthesis and final implementation into FPGAs.
1. Introduction
Digital System designers more frequently used a concurrent view of the modeled behavior. Petri nets (PNs) provide a mechanism, which is accurate to representing concurrency and hierarchy in digital processes [7,11]. The control part of the system can be effectively described and verified using the well-developed Petri net theory, and it is translated through automated processes into a selected synthesis tool’s format.
The main aim of this paper is to demonstrate a practical application of the Petri net decomposition algorithm based on finding deadlocks and traps. Obtained in such decomposition Concurrent Digital Systems represented by set of State Machine components are implemented using Programmable Logic, especially FPGA devices.
The behavioral descriptions of Control Interpreted Petri Nets (CIPN) [7,10] may be formally transformed into a format accepted by standard CAD tools based on HDLs (like Verilog) or equivalent Boolean equations [1,11].
2. Decomposition of Petri net 2.1. Linked State Machines
Concurrent Logic Controller can be presented using a concurrent view of the modeled system behavior (Fig.
1) . The logic controller model should retain the natural partitioning of the behavior imposed by the designer (Fig.
2) . The functionality very often is represented as a set of concurrent blocks of a manageable size that communicate using few signals.
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The initial partitioning generates interacting Finite State Machines (FSM) with separate state registers [1,3]. They form a conservative interpreted SM-colored Petri net [2,11]. A Petri net can be expressed graphically, then decomposed [9] into Linked State Machines (LSMs) [5], and finally translated into an equivalent set of Verilog models [10].
The collaborated State Machines can be implicitly given by means of CIPN or industrial formats (Grafcet, IEC-SFC) [7]. The generic architecture of interactive FSMs is a set of interconnected FSMs which exchange data (local internal state signals or output signals) through input and output ports. Each component is characterized by input and output ports that connect it with other components and external controller ports. The set of communicating FSMs is called a concurrent state machine (Concurrent Controller) iff two or more FSMs are not exclusively active.
2.2. Algorithm of decomposition
Algorithm of decomposition of Petri net [9] is based on verification algorithm of Petri net that has been presented in [8]. For decomposition P-invariants are used. Subsets of places representing deadlocks and traps at the same time can be P-invariants. Each such vector is verified by incidence matrix. If the result is equal to 0 it means, that such vector is P-invariants.
Fig. 1. A Petri net model of the control program
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Such P-invariant corresponds to one automat and to one color in Petri net. The number of colors depends on number of P-invariants for flat Petri net.
If it is possible to color Petri net, i.e. that Petri net could be decomposed into automata. P-invariants correspond to automata subnets.
As an example a Petri net from Fig. 1 is considered. For such Petri net, two Horn formulae were prepared (one for deadlocks and one for traps).
Below two formulae are shown, HF_D for deadlocks and HF_T for traps. Horn formula for deadlocks is as follow:
HF_D = (/p1 v p2) л (/p2 v / p3 v p4) л л (/p4 v p5) л (/p5 v p6) л л (/p6 v p7) л (/p6 v p1) л л (/p7 v/p8 v p10) л (/p9 v p8) л л (/p10 v p11) л (/p11 v p9) л л (/p11 v p3).
Horn formula for traps is as follow:
HF_T = (p1 v/p2) л (p2 v/p4) л л (p3 v / p4) л (p4 v / p5) л л (p5 v /p6) л (p6 v /p7 v /p1) л л (p7 v /p10) л (p8 v /p10) л л (p9 v /p8) л (p10 v / p11) л л (p11 v /p9 v /p3).
For such formulae Thelen trees were generated and sets of deadlocks and traps was received. These sets were compared and vectors, which were deadlock and trap at the same time was received. These vectors were multiplied by incident matrix. There are obtained three P-invariants:
([0,0,1,1,1,1,1,0,0,1,1],[1,1,0,1,1,1,0,0,0,0,0],[0,0,0,0,0,0,0,1,1,1,1])
Each element of vector represents place in Petri net, i.e. first element corresponds to place p1, second element -place p2 , etc.
These three P-invariants represent three colors, which cover whole Petri net. It means that Petri net is bounded [8]. Each color presents one automaton.
First vector corresponds to color C1, second vector corresponds to color C2 and the last - to C3 color, i.e. places p1,p2,p4,p5,p6 is colored by color C1 , places p3, p4, p5, p6, p7, p10, p11 is colored by color C2 and places p8, p9, p10, p11 is colored by color C3 . Places p4,p5,p6 are colored by two colors C1 and C2 , and places p10, p11 are colored by two colors C2 and C3 (Fig. 2).
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Each color corresponds to particular automaton. In considered example, there are tree automata (SM-components) named A, B, C that are shown respectively in Fig. 3, 4 and 5. In presented case color C1 represents automaton A, color C2 represents automaton B, and color C3 represents automaton C.
Because places p4, p5, p6 are common for two automata, in automaton A occur these places, and the remainder automaton B was added additional place pB [9]. The same situation occur in the automaton A and C, places p10,p11 are common for these two automata. These places occur in automaton A, and for automaton C was added additional place pC .
r4D
Y1
t2" «L
p3
t5" X2*p6
t1
X1
Fig. 4. The second SM-component of the net
Fig. 5. The third SM-component of the net
3. Verilog Modeling and Synthesis of SM-components
Implementation of decomposed Petri nets onto set of SM-components can be carried out on different methods. In the presented paper a modeling of automata in Verilog is focused. Other methods of automata implementation are subjects of several works, for example as microprogram control unit (MCU) [4].
Figure 6 shows a part of Verilog model with using of two processes (two always statements) [6]. There is presented only the first SM-component (i.e. the biggest automaton A).
For place encoding one-hot method has been applied. Such approach is recommended for using FPGA devices as a final implementation technology.
In such model, a sequential process is separated from the combinatorial process. In specification with two processes, the first process has in its sensitivity list a clock signal (CLK) that synchronizes the system, and a reset signal (RESET) to set-up automata into initial state. The set-up of current state and next state is done in the first process. The second process has in its sensitivity list the current state (represented the local place). The automaton outputs are set-up in the second process. Such code is easy readable, because outputs changes are separated from changes of the states sequence.
parameter [6:0] p3 = 7’b0000001,
p4 = 7’b0000010,
p5 = 7’b0000100,
p6 = 7’b0001000,
p7 = 7’b0010000,
p10 = 7’b0100000, p11 = 7’b1000000;
always @(posedge CLK, posedge RESET) begin
if(RESET == 1)
PLACE_A <= p3; else
if(CLK == 1) begin
case (PLACE A)
p3: if (p2== 1) PLACE_A <= p4;
p4 : if (X2== 1) PLACE_A <= p5;
p5: if (X3== 1) PLACE_A <= p6;
p6: if (X2== 1 && pB==1) PLACE_A л и -j
p7: if (p8== 1) PLACE_A <= p10;
p10: if (X5== 1) PLACE_A <= p11;
p11: if (X6== 1 && pC==1) PLACE_A <= p3;
default PLACE _A <= p3;
endcase
end
end
always @( PLACE_A) begin
case (PLACE_A)
p4: Y <= 6 о о 22 О О 10
p5: Y <= 6 О О 22 01 о о
p6: Y <= 6 О О 22 О О 10
p10: Y <= 6 b01 о о о о
p11: Y <= 6 b10 о о о о
default Y <= 6 О О 22 о о о о
endcase
end
Fig. 6. Verilog model of the first SM-component 4. Conclusion
An application of the symbolic method of decomposition of a Petri net has been discussed in the paper. The decomposition algorithm of Petri net is based on finding all deadlocks and traps, and then calculations of P-invariants. The P-invariants are interpreted as State Machine components, and they are represented by colors on the considered Petri net.
For implementation of set of Linked State Machines a modeling in Verilog-HDL of the particular SM-components has been demonstrated. There has been used two-process (always statements) model of an automaton. One-hot encoding method has been applied for local places encoding (states in a SM-component). Such approach is recommended for FPGA devices. Standard CAD tools can be used for synthesis.
Decomposition of concurrent controllers into set of linked states machines, in combination with possibilities
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of new FPGAs offers opportunities for partial reconfigurations. A change only of the part (that is represented by the particular SM-component) of a control program requires data exchange only in a small part of the considered FPGA. The reconfiguration is carried out with the small differential configuration bit-stream.
References: 1. M.Adamski, “Parallel Controller Implementation using Standard PLD Software”, in: W.R.Moore, W.Luk (Eds), FPGAs, The Oxford 1991 International Workshop on Field Programmable Logic and Applications, Abingdon EE&CS, Abingdon (UK), 1991, pp.296-304.2. M.Adamski, M. Wegrzyn, “Hierarchically Structured Coloured Petri Net Specification and Validation of Concurrent Controllers”, Proceedings of the 39th International Scientific Colloquium, IWK’94, Ilmenau (Germany), 27-30.09.1994, Band 1, pp.517-522. 3. M.Adamski, M. Wegrzyn, “Field Programmable Implementation of Concurrent State Machine”, The Third International Conference on Computer-Aided Design of Discrete Devices, CADDD ’99, 10-12.11.1999, Minsk, Belarus, Vol. 1, pp.4-12. 4. A.Barkalov, M. Wegrzyn, Design of Control Units with Programmable Logic, University of Zielona Gyra Press, Zielona Gyra, 2006. 5. H.Belhadj, L.Gerbaux,M.-C.Bertrand, G.Saucier, “Specification and Synthesis of Communicating Finite State machines”, Synthesis for Control Dominated Circuits, (A-22), Elsevier Science Publishers B.V. (North Holland), 1993, pp.91-101. 6. S.Chmielewski, M.WKgrzyn, “Modelling and synthesis of automata in HDLs”, Proceedings of SPIE (XVIII IEEE-SPIE Symposium on Photonics, Electronics and Web Engineering), Wilga (Poland), 29.05-
04.06.2006, (to be published). 7. R.David, H.Alla, Petri Nets and Grafcet, Prentice Hall, New York, 1992. 8. A.Wegrzyn, Symbolic Analysis of Logical Control Devices using Selected Methods of Petri Net Analysis, Ph.D. Thesis, Warsaw Univ. of Technology, 2003, (in Polish). 9. A.Wegrzyn, M.Wegrzyn, “Petri Net Decomposition Algorithm based on Finding Deadlocks and Traps”, IEEE East-West Design & Test International Workshop, Sochi (Russia), 15-19.09.2006. 10. M.Wegrzyn, P.Wolacski, M.A.Adamski, J.L.Monteiro, “Field Programmable Device as a Logic Controller”, Proceedings of the 2nd Conference on Automatic Control - Control’96, Oporto (Portugal), 11-13.09.1996, Vol.2, pp.715-720. 11. M.Wegrzyn, Hierarchical implementation of Logic controllers by means of Petri nets and FPGAs, Ph.D. Thesis, Warsaw Univ. of Technology, 1999, (in Polish).
Поступила в редколлегию 27.07.2006
Рецензент: д-р техн. наук, проф. Хаханов В.И.
Wegrzyn Agnieszka, PhD., lecturer at University of Zielona Gora. Interested in: formal analysis, Petri net, databases, DBMS, Internet applications. Address: Computer Eng. and Electronics Institute, University of Zielona Gora, ul. Podgorna 50, 65-246 Zielona Gora, Poland, E-mail: A.Wegrzyn@iie.uz.zgora.pl Ph.: (+48 68) 3282 484.
Marek Wegrzyn, PhD., lecturer at University of Zielona Gora. Interested in: formal analysis, Petri net, databases, DBMS, Internet applications. Address: Computer Eng. and Electronics Institute, University of Zielona Gora, ul. Podgorna 50, 65-246 Zielona Gora, Poland, E-mail: A.Wegrzyn@iie.uz.zgora.pl Ph.: (+48 68) 3282 484.
УДК638.235.231
СУБЪЕКТНО-ОБЪЕКТНАЯ МОДЕЛЬ НЕСАНКЦИОНИРОВАННОГО ДОСТУПА С ИСПОЛЬЗОВАНИЕМ АППАРАТНЫХ ЗАКЛАДОК К КОМПЬЮТЕРНОЙ ИНФОРМАЦИИ
ГОРБАЧЕВ В.А., СТЕПАНЕНКО В.В., ИВАНИСЕНКО И.Н.
Использован субъектно-объектного подхода при разработке моделей функционирования аппаратной закладки. Полученные результати могут быть использованы при построении формальных моделей политики безопасности КС.
Целью работы является анализ угроз информации, исходящих от аппаратных ресурсов компьютерных систем. Для достижения этой цели решаются следующие задачи: разработка математической модели несанкционированного доступа, который реализуется аппаратными закладками, а также определение функции управления доступом к аппаратным ресурсам.
Для построения модели взаимодействия электронных компонентов компьютерной системы (КС), среди которых имеются аппаратные закладки, применяется субъектно-объектный подход. В рамках данного подхода все множество электронных компонентов представляется в виде двух подмножеств: субъектов и объектов. Разделение на соответствующие подмно-
жества осуществляется по признаку активности каждого компонента. Полученные результаты могут быть использованы при построении формальных моделей политики безопасности КС.
Анализ литературы по защите информации в КС [ 1 -5 ] позволяет утверждать, что в настоящее время сам компьютер, его аппаратные ресурсы (электронные компоненты) могут содержать различные источники угроз безопасности информации, расположенные как в отдельном компьютере, так и в КС в целом. Это обстоятельство обусловлено рядом причин. Во-первых, современная технология позволяет разместить на достаточно малых площадях, которые составляют 5-10% от размеров всего кристалла интегральной схемы, устройства, способные выполнять широкий спектр не специфицированных функций. Во-вторых, информация в КС рано или поздно появляется в открытом виде, и аппаратные ресурсы могут получить доступ к этой информации. В-третьих, высокая степень интеграции электронных компонентов и технологии, применяемые для их производства, усложняют работу по их сертификации, а также по наблюдению за их функционированием.
В настоящее время активно исследуется проблема несанкционированного доступа, который реализуется программными закладками (ПЗ) [1,2,4, 5]. На практике можно внедрить ПЗ в ядро операционной системы или в любое приложение таким образом, что она будет как контролировать и модифицировать всю деятельность системы безопасности, так и осуществлять несан-
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