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UDC 681.326:519.713
MATHEMATICAL MODELLING OF PARAMETER FLUCTUATIONS WITH APPLICATIONS TO FAULT DETECTION IN ANALOGUE VLSI CIRCUITS
H. J. KADIM
While a circuit’s manufacturing yield is high it might be very sensitive to variations in environmental conditions such as power supply and temperature. Such sensitivity causes the circuit to have low operating performance. The method proposed integrates design and test. It is based on analytical modelling equations to estimate the sensitivity of analogue circuits to faults and parameter variations, and determining the reliability of circuits when operating in the presence of faults. The work presented in this paper is twofold: (i) an investigation of systems dynamics to estimate the reliability of the circuit when operating in the presence of faults; (ii) a proposed method for minimal realisation.
1. Introduction
Analogue testing is a challenging task, and it is one of the most important problems in analogue and mixed-signal integrated circuit design. The challenge stems from the fact that the physical quantities of analogue circuits vary over time. The great variety ofpossible input and output signals make it difficult to determine which of the many circuit’s parameters are important. Accurate analogue simulation has to be performed at the device level and this is very demanding of CPU time and memory. Consequently, it can only practically be applied to small analogue designs; otherwise the analysis effort and time requirements would be prohibitive. There are numerous techniques in the literature for testing analogue/mixed-analogue VLSI circuits, some of these techniques use simulation methods [1] and others use symbolic methods [2], but few attempts have been made to estimate the robustness of these circuits to faults. Techniques which are either aimed at testing [3] or at identifying faults which have no effect on analogue circuits’ behaviour [4], or aimed at testability analysis [5] generally have high computational cost even for relatively small circuits because of the number of variables and parameters involved. Most of the methods for testing analogue circuits [6-9] require that the circuit under test to operate in a test mode, during which time the circuit has to cease its normal operation. Furthermore, faults which have no effect on a circuit’s behaviour are an indication of a redundancy in the circuit [10] [11] which is another contributor to the problem suffered by established techniques since the inclusion of a redundant part of a circuit in any analysis process will add to the overall cost in terms of time and effort. The redundancy may be the result of an accidental failure to implement minimal design in which case there is a need to eliminate such redundancy, or it may be included deliberately in order to satisfy some other design criterion, in which case it is important to be identified
and excluded during testing or analysis of the circuit under test.
Due to the development of system-on-a-chip (SOC) and market potential, the trend of designing mixed-signal intellectual property (IP) cores has increased. However, the evolution of SOC has brought with it challenges to the test engineers. For instance, IP-cores with different clock regimes, the high ratio between internal and external pins, the high number of protocols and test patterns required for testing are an example. Therefore, test methodologies that are independent of an IC’s operating speed will be well suited for SOC devices [12]. The work presented in [12] was centred on testing analogue IP-cores from outside the chip. Already evaluated behavioural responses can be stored in a database against which the responses of IP-cores are continuously checked for possible functional abnormality during the chip’s normal operation. This allows for a process to be implemented independently of SOC normal operation and operating frequency. Analysis and simulation was proposed to evaluate the sensitivity of analogue IP-cores to parameter variations. However, in many cases it is important not only to know whether or not a circuit is sensitive to parameter variations, but also the effect of such variations on stability. This allows to accurately synthesise the degree of effect of parameter variations on circuit performance. Variations could be due to external or internal disturbances in the form of faults, which may be hard or soft. It is not always the case that faults can result in abnormality in circuits’ behaviour [10] [13], and such circuits are said to be tolerant to these particular faults. If for a maximum bound of fluctuations which drift a circuit closer to its marginal stability, optimal component values can be chosen. This allows the integration of design and test by coupling dynamic circuit behaviour to parameter fluctuations.
The aim of this paper is to: (i) investigate the effect of faults on the dynamic characteristics of analogue IP-cores, (ii) calculate the sensitivity of a circuit to parameter changes in terms of the positions of the poles in the complex plane [ 10]; (iii) estimate the maximum bound of parameter fluctuations that maintains a normal functional behaviour.
2. State-space: Mathematical background
The state space representation [10] of an analogue circuit or system is given by:
x’(t) = Ax(t) + Bu(t), (1)
y(t) = Cx(t) + Du(t), (2)
where x(t) — state vector (n elements); y(t) — output vector (m elements); u(t) — input vector (r elements); A — system-interconnection matrix (n.n); B: driving matrix (n.r); C: output matrix (n.m); D: transmission matrix (m.r)
The diagonal matrix of A (i.e. A^) has its main diagonal representing the distinct poles of an analogue circuit which can be real or complex (Xi; i: 1, 2, ..., n).
Ad = (Xii), (3)
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where Xjj = 0 when iф j.
The state space vector representation of Ad is given by d’ = Ad d (4)
(d — diagonal-circuit vector).
X t
With the natural modes being e jJ . The relationship between the actual states of the circuit and the diagonal states is given by
x = V d (5)
(V: a matrix with eigenvectors as columns).
Differentiating both sides
x’ = V d’ (6)
The matrix V can be considered as a transducer matrix transforming the state vector d into the state vector x. The eigenvector can be determined using the following equation:
A Vw = X w Vw (7)
where Vw — an eigenvector of A; X w —the corresponding eigenvalue.
For undriven analogue circuit, equation (1) becomes
x’ = A x (8)
From (4), (6) and (8)
A= V Ad V-1 (9)
From equation (9), since V can be chosen arbitrarily, there is an infinite number of circuits that can be obtained, all having the same eigenvalues (or poles).
From the above it is informative that circuits with different realisations may have the same poles, and hence their characteristics are identical. With reference to a reducible circuit, faults occurring in such a circuit may result in reconfiguring the circuit into its reducible realisation without affecting its poles (i.e. there is a
nonsingular matrix such that A = V A V-1; A —faulty circuit).
3. Faults and Circuit Poles
To illustrate the effect of faults on pole characteristics consider a second order faulty circuit such that the fault has no effect on the output.
From equations (1) and (2):
x'+x = [A + A ][x'+x ] + BU У = [ci c2][x'+x ] + DU
Separating the faulty signals
A A A
x = Ax,
A A A
a11 a12 W11
A A A
_a21 a22 _ LW21_
A A A
a11 a12 W12
A A A
a21 a22 J _W22 _
From (10) Л Л Л /
a11 W11 + a12 W
л Л Л X
and a 21 Wn + a22W
From (11) Л Л A
a11 W12 + a 12 W
and л Л A A
a 21 W12 ^ a 22 W
A Assume W11 = aW11 and W
—
— A, 2
A
W11
A
W21
A
W12
A
W22
л л
^21
Л Л
X 2W,2
Л Л b 2W22
(10)
(11)
(12a)
(12b)
(13a)
(13b)
P are factors representing the change in the eignvectors Wn and W2i respectively in the presence of a fault.
л
Substituting W11 in equations 12a and 12b, and rearranging
Л Л Л /А A \
W21/W11 = (a / P)[(X1 - an)/a12] (14a)
W21/W11 = (a / P)[a21/(X1 - a22), (14b)
similarly
л л л /к ч
W12/W22 = (У/к)[(Х2-a22)/a21], (15a)
W12/W22 = (У / K)[al2/(X 2 - a^1)], (15b)
where у and к are factors representing the change in the eignvectors W12 and W22 in the presence of fault.
Re-arranging equations 14a and 14b, and differentiating with respect to a or b
Л Л Л Л Л
0 = ^1 - an ^ ^1 = an , and a12 = 0.
Re-arranging equation 15a and 15b, and differentiating with respect to g or k
Л Л
0 = X 2 - a 22 Hence
Л Л Л
^ 2 = a22 , and a21 = 0 .
A
0
Л
0 ^2
(16)
Л x1 Л Л a11 Л Л a12 Л Л x1 Л Equation (16) shows that faults introduces a change in the elements of the main diagonal of the matrix of the eigenvalues of an analogue circuit. For the case ofnon-
x 2 _ _a 21 a 22 _ _x 2 _ irreducible circuits, the introduction of a fault may not affect the overall circuit behaviour [13].
From equation (7) 104
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Illustration: The state space representation of a third order analogue circuit is given as follows:
W12 _ a12 / P
6 -11 - 6" T
A = 1 0 0 B = 0
0 1 0 0
C = [< 0 1 2l 0 II Q
V =
0.9435 0.8729 0.5774
- 0.3145 - 0.4364 - 0.5774
0.1048 0.2182 0.5774
The circuit realisation is shown in figure 1.
U-
Fig. 1. A third order circuit
The circuit’s response to a unit step input is shown in Fig. 2.
4 6
Time (sec)
10
W21 ^1 _ an/a
(17a)
W22 A, 2 - an/ a' (17b)
Manipulating Equations (17a) and (17b): a = 3/2, p =2.
Re-arranging equations 13a and 13b in terms of the eignvectors ratios, and matching the coefficients with their correspondent in equations 14a and 15b
л л
a11 = - 4, a12 = - 3.
Repeating the above procedure for 14b and 15a
л л
a22 = - 0 a21 = 1.
The state space representation of the new circuit (i.e. faulty circuit) is as follows:
(18)
(19)
6 Л Г- 4 - 3] л Г1]
A = 1 0 B = 0
л
V =
C = [0 1 D = 0 ,
- 0.9487 0.7071"
0.3162 - 0.7071
Fig. 3. The fault free and faulty response of the circuit
in Fig. 1
The reduced circuit realisation is shown in Fig. 4.
Fig. 2. The fault free response of the circuit in Fig. 1
A fault is applied to the circuit such that the output of the integrator of the state variable x3 is kept at 0 value. Hence, the circuit is reduced to a second orderwith only two state variables.
From equations 14a and 15b
W11 _ a12/ P
Fig. 4. A reduced order system
The eignvector matrix shows that the new circuit has the same eignvectors ratios and the same poles when compared with the original circuit.
For the irreducible circuit in Fig. 4, a change in any of the poles as a result of a fault(s) triggers abnormalities
0
2
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in the circuit’s characteristics, as investigated in the following section.
4. Soft and Hard Faults
To illustrate the effect of hard and soft faults on the circuit shown in Fig. 4, only the integrator representing the state variable x1 is considered. The analogue representation of the integrator is shown in Fig. 5.
Fig. 5. An integrator representing x1
The analogue representation of the integrator of Figure 5 is shown in Figure 6.
Any slight or large variations (i.e. soft or hard faults) in either R1 or R2 would introduce changes in the value of the feedback coefficient and eventually affect the eignvalue of the state variable x1. The change in the eignvalue yields a change in the circuit’s behaviour as illustrated in Figure 7.
Fig. 6. Analogue representation of an integrator
R
= 4
2
(the integer ‘4’ is the value of the feedback coefficient in Fig. 5)
1
S
"E.
5 ^ )f£ Ш " s=-1.5 ± j1.75 (R1/ R2 decreased by 2%)
s = -1 L j1 45 CRJ by 95%)|/
5 \
1 \ 1 X
5 2 +1 jb •— in \ j1.66 (R1/R2 decreased b ' 50%)
Time (sec)
10
Fig. 7. Changes in the behaviour of the circuit of Fig.6 as a result of changes in the coefficient of the sate variable x1
Fig. 7 shows that the characteristics of the poles are severely disturbed by the changes in either R1 or R2. The changes in the circuit’s parameters are shown in Table.
The irreducable circuit shown in Figure 4 represents an overdamped circuit, but its behaviour was drifted into oscillation prior to reaching its steady state as a result
of the changes in R1 and R2, which in turn affect the state variable x1 (i.e. the characteristics ofa pole). If the variations in the characteristics of this pole are within a prescribed limit permitted by the specifications, then the circuit can be kept in operation without a noticeable compromise in performance. Maximum and minimum bounds of tolerance are evaluated at the design stage. These bounds provide a window within which a circuit can operate satisfactorily in the presence of parameter fluctuations. This information can then be used as a guide to test the circuit in the presence of hard and soft faults. The following section illustrates how the tolerance limits can be determined using mathematical modelling of parameter uncertainties.
5. Parameter Uncertainties
In the presence ofparameter uncertainties equation (1) can be rewritten as follows:
d(x(1)* Ax(t>> = A(x(t) + Ax(t)).
Isolate the uncertainty signal and re-arranging d(Ax(t))
dt ) = ЖДх(1)) (20)
and p(s) = Ddet (si — A). (21)
Considering that: (i) equation (4) is the result of parameter uncertainties, and (ii) a circuit may consist of a number of parameters, it is possible to model parameter fluctuations as infinitesimal transfer functions within the main transfer function of the circuit. If all the infinitesimal transfer functions are represented by Dp and are related to the main transfer function T as shown in Figure 8, then the transfer function ‘T’ of a
Performance of the circuit of Figure 6 in the presence of soft and hard faults
Circuit parameters R1/R2 decreased by 2%
natural frequency Wn 1.732 rad s-1
damped frequency Wd 1.75 rad s-1
damping ration £, 0.65
overshoot Mp 0.064
tp 6.4% overshoot occurs at 1.794 sec
settling time 2.637 sec
No. of oscillations necessary to reach ts 0.558 oscillations
R1/R2 decreased by 25% R1/R2 decreased by 50%
1.733 rad s-1 1.761 rad s-1
1.65 rad s-1 1.69 rad s-1
0.29 0.28
0.38 0.39
38% overshoot occurs at 1.9 sec 39% overshoot occurs at 1.85 sec
5.97 sec 6.08 sec
1.576 oscillations 1.637 oscillations
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circuit in the presence of parameter fluctuations can be defined as [15]:
Л Л Л
x = Ax , (22)
where Tn — nominal transfer function, A n — parameter fluctuation.
Refer all fluctuations to the main transfer function [15,16]:
Ap = Wi AWj; і Ф j, (23)
where Wi and Wj — weighting matrices; and
| A|<y, (24)
where у — maximum bound to ensure stability and desired performance.
Ei^ л Pi/W, T - 4 A M + tPfvWl &
1 T L Л _Pn_ in - Ap Л -►En
Fig. 8. Representation of parameters fluctuation
From Figure 8
X' Ei'
= M
_ Pi _ _Po _
with
M =
M„
M2,
M12
M22
Л Л
The equation relating Po to Pi is given by:
(25)
(26)
jh_
Wi
(1 + Tn) = -W2Po
(27)
where I — unity matrix.
Re-arranging, and from equations (10), (11) and (13)
M22 =-W2(I + Tn)-1Wi. (28)
o~ і
It is assumed that in the absence of parameter variations the designed circuit is stable. In the presence of parameter variations the circuit can maintain a stable behavioural operation as long as:
| Д |<y , and A,(M22 A) < 0 . (29)
The determinant in a state-space form is given by:
det (si - A) = 0. (30)
For a small variation in parameters | ai | < у , where ai is a coefficient of matrix A.
For small changes, the sensitivity ‘S’ of Tn with respect to ai is given by [17] :
STn = _a^ ai Tn ‘ 5a і .
(31)
From equation (31), the change in parameters represents a range of values, у max < ai < у min .
The coefficient ai now represents an uncertain range of values. The sensitivity of X with respect to ai, as д ai approaches zero is given by [17]:
SX = АЯ
ai Aai / ai
(32)
In certain cases, it is important to know how close a circuit is to instability. This can be achieved by
modifying equation (29) as follows: Xs (M22 A) ^ k ; k - integer, so that
к s(M22 A) = MM22 A)
k ^0
and X = Xs - |k . (33)
Example
Using equations (18) and (19), the transfer function of the reduced order circuit of Figure 4 is given by:
Tf =
1
s2 + 3s + 4
(34)
The characteristic equation of a second order analogue circuit is given by:
s + a,s + ao — 0. (35)
From equation (34): ao = 4, a, = 3 .
For consistent circuit performance, the pole must not move substantially during the circuit operation, and, hence, the root sensitivity must be relatively small.
For k = 0.1, substitute equation (33) into equation (35)
(s - 0.1)2 + 4(s - 0.1) + 3 = 0 .
Solving for s
s1 = -2.9 s2 =-0.9
k=0.1
For other values of k:
s1 =-2.5 s1 = -3.0263 s1 = 2.2
s2 =_0.5 k=0.5’ s2 =_0.853i k =0.0/ s2 =_0.1
k=0.9
Fig. 9 shows that for k = 0.07, the transient behaviour of the circuit is nearly close to the nominal one, and may not be detected by conventional test techniques.
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Fig. 9. The effect on step-response of increasing k From Fig. 9 and for a robust operation k < 0.07
If k is chosen to be 0.07, and since A mag = 3.162, then for a robust operation AX / X can be calculated from equation (23): AX/X = к/ X ^ < 0.026.
For any chosen value of k, it is possible to predict a circuit’s component values using equations (30) and (33).
6. Conclusion
A method for fault detection in analogue circuits has been introduced. It was based on analytical modelling equations to estimate the sensitivity of analogue circuits to parameter variations as well as the uncertainty bound for robust operation, independent of simulation.
Depending on the realisation of the circuit under test, faults occurring in an analogue circuit may not have an effect on the circuit’s behaviour. Therefore, analogue circuits under such faults can operate without compromising performance. The paper also demonstrated a method for eliminating hardware redundancy.
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H.J.Kadim, School of Engineering, Liverpool JM University, Byrom Street, Liverpool L3 3AF, England, UK, e-mail: [email protected]
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