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EDUCATIONAL PURPOSE CAD TOOL FOR TESTING AND DIAGNOSIS OF ANALOG CIRCUITS:
FAULTS SIMULATION
SERGEY G. MOSIN______________
Computer Science Department, Vladimir State University, Vladimir, RUSSIA; e-mail: smosin@ieee.org
Abstract. This paper proposes the educational purpose tool (TeDiAC) for simulation of parametric and catastrophic faults in analog circuits, and also for decision of some test and diagnosis tasks (test point selection and fault dictionary construction, minimization of test vectors, etc.). This tool allows estimating the influences of internal component parameters’ deviations on circuit’s output characteristics in static, frequency and time domains.
Keywords: analog circuits, parametric and catastrophic fault simulation.
1. Introduction
Testing of analog circuits functioning is expensive and difficult process. Unlike the case of digital circuits, where output signals are described by two possible states (one and zero), behavior of analog circuits is more complex and all processes in analog circuits are continuous. As a result, in contrast to digital circuits, the function of analog circuit can not be described by a closed form expression such as a set of Boolean equations. Usually for description of analog circuits’ behavior the sets of equations (linear, non-linear, differential, integro-differential, etc) are used. In the digital testing domain easy fault models such as “stuck-at” faults, which correspond to shorts and open defects, can be applied for simulation of fault circuit’s performance. The faults of analog circuit are usually split into two basic types: parametric and catastrophic. Parametric faults, which are results of inevitable fluctuation peculiar to the manufacturing process, are usually modeled by small deviation of the circuit parameters. Typically, a limit of ±5% deviation from nominal is acceptable. Such limit is also often called as tolerance range. Catastrophic faults, which occur due to spot defects, are usually modeled by topological changing of the circuit. The detection of parametric faults is regarded as a much more difficult problem then the detection of catastrophic faults. In many respects it depends on different, unpredictable influence of parametric faults. Parameter of each analog circuit’s component has some deviation. The value of this deviation defines the status of internal component: faulty or fault-free. The component is considered as faulty if deviation value is placed outside the tolerance range.
Thereupon, the output characteristics of analog circuits do not take on an algoristic value. Output characteristics have some deviation from their values. In this case there is one additional problem - the output response of analog circuit may be situated in range of its tolerance, even if one or several internal components are faulty. Besides, output response of analog circuit may be situated outside of its tolerance range,
if none of internal components is faulty. Such circumstances very often result in two of possible during testing errors: alpha and beta errors, i.e. consideration of faulty circuit as fault-free and consideration fault-free circuit as faulty. Thus it is very important to investigate the influence of deviation of different in-circuit components’ parameters on total performance of analog scheme during its designing. Most studies in the field of analog circuits testing are based on deviation of circuit characteristics or behaviors from those of a fault-free circuit when a fault occurs in the circuit.
Simulation of fault-based analog circuit may be fulfilled in different domains (static, frequency and time) with usage of one from two possible strategies: functional and structural approaches. During functional approach, simulated circuit saves its structure but components’ parameters take different values, which can be both in tolerance range and outside of tolerance range. One of the most famous functional approaches is Monte Carlo analysis. Structural approach is based on exploiting of the specific structural differences between the faulty and fault-free circuits. These two approaches are not rivals because are intended for simulation of different types of faults. So, functional approach is more suitable for simulation of parametric faults in analog circuits. Structural approach is more appropriate for simulation of catastrophic faults ’ influences on analog circuits’ functioning.
Exploration of specific features peculiar to different analog applications is usually performed with usage of special CAD tools, such as Spice-like simulators. Distinction of such tools is orientation on needs of circuit designers. Recently several commercial CAD tools for satisfying the requirements of test engineers were proposed [1, 2].
In this paper the educational purpose CAD tool for investigation of features of analog circuits functioning is presented. This tool, called as T eDi AC (Testing and Diagnosis of Analog Circuits), is intended not so much for usage in real commercial projects as for teaching of test engineers. Using this tool, students can study different approaches to simulation of analog circuits ’ faults, compare of several methods of test point selection, consider of some approaches to construction of fault dictionary and minimization of cardinality of input test vectors.
The paper is organized as follows. In next section the approaches to functional and structural simulation of faults and defects in analog circuits are considered. In section 3 the structure of TeDiAC is given. Section 4 gives result ofthe tool usage for the test bench analog circuit.
2. Simulation of Analog Faults and Defects
The parametrical and catastrophic faults in linear and nonlinear analog circuits in different ways influence on their functionality. In linear circuits the parametrical fault, which can be result of fixed technological tolerances, aging or parasitic effects, causes unessential changes in the characteristics of the circuit. Such changes practically have no effect on circuit functioning. In this case it is very difficult to detect a presence of a fault at the device.
In the non-linear circuits, where the input and output signals are connected by complex non-linear relations, using parameters of in-circuit components as variables, parametric faults have more complex influence on analog circuit’s
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functioning. In practice the parameters of all fault-free incircuit components do not accept definite nominal values, but values from some range in view of tolerances on them. In this connection not only fault, but also deviation of the component parameter within the tolerance range can essentially affect on the value of an output signal of the nonlinear analog circuit.
Usage of CAD tools is convenient for investigation and taking into account of influence of circuit component tolerances on the output characteristics. The parametric faults of passive components can be rather simply simulated that one can not be said about active components. Such simulation can be performed with usage both functional approach and structural one. At functional approach the real value of in-circuit parameter is taken into account during simulation instead ofits nominal value. At structural approach additional compensating component is put into simulated scheme. So, at simulation of a resistor the compensation of deviation ofits parameter from nominal value can be executed by parallel connection of nominal and correction resistors. The series connection usually is not used, because it is results in appearance of an additional node in the circuit. Suppo se that the actual admittance of a particularb ranch (fig.
1., a) is deviated from its nominal admittance by Ay(fig. 1., b). The deviation may be caused by tolerance (in which case Ay is small), or by a fault (in which case Ay is large). According to a circuit theory, the deviation can be compensated by a current source, which depends on the deviation Ay and its branch voltage. The simulation of the circuits with taking into account the possible deviations of internal components parameters allows to determine probable diversities of the output characteristic values, and also to define tolerances on them. Simulation of active components ’ deviations is more complex task. It is well known that active components are described by a set of parameters. For instance, the model of semiconductor diode is described by 25 parameters, model of bipolar transistor, described by Ebers-Moll’s scheme, has more than 40 parameters. Thus, in order to take into account influences of deviation of some active component’s characteristics it is required to change the set of model parameters.
a b
Fig. 1. Model of parametric fault: a - Actual admittance, b) Nominal admittance
The catastrophic faults in contrast to parametric ones always result in essential violations of the analog circuit operation. The hard faults usually deal with appearance of shorts or opens of either printed circuit boards routed or conducting paths of integrated circuit, and also with physical destruction of elements (for example, thermal breakdown or mechanical damage).
Shorts, sometimes called bridging faults, are the most common faults originating during integrated circuit fabrication. They
are due to additional conducting paths that connect two or more nodes of the circuit together. In IC the shorts arise as a result of conducting paths contact among themselves or with package under the influence of mechanical vibrations or impacts, or as a result of local overheating and fusing of overheated place. The studying of such faults influence on analog circuits functioning is executed by their simulation. The modeling of shorts on schematic level is carried out by simple insertion of a resistor between two nodes. The insertion process canbe repeated for all combination of two nodes. The value of used resistor must be sufficiently small and is selected usually from the range from 1 up to 10 Ohm. With raising of designed circuits’ complexity, when a number of possible combinations is increased, such simulation present a great problem.
The second frequently encountered catastrophic fault is the open, which occurs in conducting paths of integrated circuit as the missing section of them. In IC the opens can appear due to both mechanical influences (such as vibrations, impacts) and in result of electrochemical and chemical processes. In first case, as rule, the electric coupling of bonding wires with contact pads on die or with chip pins are destroyed. As to electrochemical and chemical processes, they can appear in various variants, for examples, 1) as corrosion of metallization layer and contact connections; 2) derivation of intermetallic connections, that is typical for contact of heterogeneous metals; 3) electromigration. The simulation on schematic level of open faults influence on analog circuit’s functioning canbe performed by forced disconnection of different devices contacts. On practice as long as the CAD tools do not permit the “floating nodes”, or nodes with less than two connected conductor lines. Thus, a resistance of high value is used, which is connected up between component electrode on the one hand and circuit node on the other hand. However such disconnection is not ideal for high frequency effects a capacitor is connected in parallel with the resistor. In present solution the resistor value is selected from range from 10 Mohm up to 100 Mohm, and value of capacitors lies in the range from 0.1fF up to 1fF. The disadvantages of such model are, firstly, appearance of additional node at circuits for each open fault and, secondly, the increasing of computational and time expenses at the rising of simulated circuit’s dimension.
One of the option of proposed TeDiAC tool (fig. 2) is investigation of influence of different kind of faults (hard and soft) on analog circuits functionality. For that purpose the approaches of functional and structural simulation are used.
3. Functionality of TeDiAC tool
The source external data for analog circuits simulation is scheme description on Spice-language. Such description may be created in any test editor or with usage of built-in TeDiAC circuit description editor. The description contains the netlist of analog circuit under simulation with nominal parameters of internal components.
Depending on choosing in the tool the type of analysis and setup of appropriate settings there are several ways of circuit simulation in TeDiAC. First of all, this is circuit modeling with nominal values ofinternal parameters in three possible domains - static, frequency and time, and also calculation of sensitivity function. Secondly, there is possibility to investigate influence of parameters deviation of some in-circuit components. In that case, user has to specify a value of relative deviation (in
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Fig. 2. Structure of TeDiAC
percents) for each interested component. The parameters of components hand-picked by such way will take random value from the specified tolerance region. The Gaussian (normal) distribution law is used for that purpose in the tool. Using Monte Carlo analysis, user obtains opportunity to get the acceptable region for output circuit characteristics. For that purpose it is important to specify a number of iterations, i.e. the quantity of simulation retry with new values of components parameters, which lie in range oftolerance. In this case we get the diversity of possible values for output characteristics under the stipulation that parameters of all in-circuit components are fault free.
In order to simulate analog circuit functioning with some predefined faults it is necessary to change circuit description by editing of parameters’ values of some components (for parametric faults) or including additional resistances (for catastrophic faults). Such description transformation may be easy performed in TeDiAC editor.
The results of circuit simulation are used either for graphical display or for further processing during procedures of test point selection, fault dictionary construction, minimization of test vector cardinality.
The graphics of functional dependencies of output characteristics from variable parameters are represented in plot windows. For each domain (static, frequency and time) a new window is constructed. Plots obtained for various conditions are marked by different colors. This allows to distinguish different results and improves observation of specificities of analog circuits’ functioning in faulty and fault-free states.
4. Experimental results of TeDiAC tool usage
The testbench circuit of second-order bandpass filter was used as experimental scheme (fig. 3). The deviations of incircuit components’ parameters were accepted as + 5% for
resistors and + 10% for capacitors. These values are specified in the input circuit description and may be changed by user.
Fig. 3. Second-order bandpass filter
The influences of components parameters deviations, which are in tolerance range, result in deviation of circuit outputs. The results of investigation of parametrical faults influences on the circuit functioning are presented in fig. 4 and 5.
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Fig. 5. Frequency output voltage
These figures show the filter output responses in static and frequency domains, which were obtained during multiple repeating of simulation at different parameters of all passive in-circuit components. The number of such iteration is specified in the TeDiAC by user. Circuit’s parameters are generated in the tool randomly by Gaussian’s distribution law and lie in the determined tolerance range peculiar to each component. Such simulation demonstrates the possible dispersal of output characteristics of fault free filter (a number of thin lines). Also the output response of circuit with direct nominal values of internal components’ parameters is put in the results windows (thick line).
Thus, it is possible to compare output characteristics of pure nominal circuit (ideal case) with the same characteristics of more real circuit, parameters of components of which are deviated in their tolerance range (actual case).
The simulation of predetermined parametrical fault can be performed in the same way. But here it will be necessary to specify the fault component and its deviation.
Conclusion
Analog test development requires careful manual optimization, and efficient interactions between circuit designer, and also process and test development engineers. The educational purpose tool for investigation influences of different kind of faults, and studying of some methods of analog circuits testing and diagnosis has been presented.
Acknowledgement
This work is supported by EU Commission in the frame of IST-2000-30193 (REASON) Project.
References: 1. Saab K., Marche D., Hamida N. B., Kaminska B. LIMSoft: automated tool for sensitivity analysis and test vector generation // IEE Proc. Circuits Dev. Syst., Vol. 143, No. 6, 1996. P. 386-392. 2. Hamida N.B., Saab K., Marche D., Kaminska B. FaultMaxx: A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits. In Proc. of Asian Test Conf., 1997. P. 182-187.
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