CC BY
12
oefficient of electrons in silicon, a the conductivity of silicon, and S stands for the Seebeck coefficient for silicon.
The calculation has led to the values jE = 6.98 • 106 A/cm2, jAn = 4.83 • 106 A/cm2, and jAT = 3.78 • 102 A/cm2. It is observed that the thermal current density is several orders of magnitude lower than the other two types of current density. It can therefore be taken into account that the main contribution to the resulting current density has a drift current (lower inset in Fig. 5) and a diffusion current (upper inset in Fig. 5), which have the same order of values.
In Fig. 5, it can be seen that the concentration gradient has two components with opposite directions and different values. This is related to the different influences of the normal (vertical) gate field at the source and drain end on the drain current.In fact, one component is directed along (Jn+) and the second one is directed opposite (Jn-) to the field between source and drain (upper insertion in Fig. 5). The estimations show that the resulting diffusion current ( Jn = Jn+ - Jn-) is directed opposite to the drift current. The resulting channel current is therefore defined as the difference between the drift and the resulting diffusion current.
A comparison of the dependencies in Fig. 4 shows that the increase in the current density at a high TSi/WSi is due to an increase in the diffusion current. It can be seen that the current density is increased for transistors with TSi/WSi greater than 1.75, while the lattice temperature in the middle of the channel increases monotonically in all ranges with increasing TSi/WSi (Fig. 6), which is not appropriate to the current density dependence on TSi/WSi.
Our findings allow the conclusion that the resulting current density in the channel is not only the main factor for the dependence of the lattice temperature on the channel shape. It is mainly related to the structure's capability/ability to dissipate heat and not just to the power of the heat source. The main routes for heat dissipation from the center of the channel are through the back oxide layer and the gate oxide layer. These heat dissipation capabilities can be expressed by the formula (see Eq. (4)) of the dependence of the temperature change in a channel on the thickness of the back oxide
Fig. 5. Typical distribution of the temperature, electron concentration, and the field along the middle of the channel. TSi/WSi = 0.4
Fig. 6. Dependence of the temperature in the middle of the channel on the ratio TSi /WSi for transistors of the first group
layer, proposed in [23]:
At = (Pt ' Tox), (4)
Kb • A
where Pt stands for the heat power generated by current in the channel, Kb is the heat conductance of the oxide layer, and A represents the area of the contact surface between the oxide layer and the channel. To compare the heat dissipation through back oxide and gate oxide layers, we used equation (4) for both gate oxide and back oxide layers. From equation (4), the gate oxide is justified, because the physical mechanism of heat dissipation through the back oxide and gate oxide are the same. For the back oxide layer A = WSi • L and gate oxide layer A = (2TSi + WSi) • L, where L stands for the channel length. Therefore, when using the independent heat dissipation through the oxide layers, the temperature changes associated with the heat dissipation through the back oxide layer and gate oxide layer, normalized to the heat power, can be written from (4) using the following formulas:
AT Tbox
Pt Kbox • WSi • V
AT T
— = -^-, (6)
Pt Kg ox • (2 • Tsi + Wsi) • V
where, Tbox is the thickness of the back oxide layer, Tgox represents the thickness of the gate oxide layer, Kbox and Kgox are the heat conductivity of the back and gate oxide layers, respectively. For these two heat dissipation mechanisms, the AT/Pt dependence on TSi/WSi (channel shape) is presented in Fig. 7. For simulation, we considered SiO2 as the back oxide layer and HfO2 as a gate oxide. The heat conductance of the hafnium oxide layer is in the range from 0.49-0.95 W/(m-K) in the temperature range from 300-500 K, and the heat conductance of SiO2 is in the range from 1.2-2 Wt/(m-K) in the temperature range from 200-1500 K. In the simulation we used the value of the heat conductance 0.6 for HfO2 and 1.5 for SiO2. As it appears from Fig. 7, a big gap in the values of heat conductances results in a higher heat dissipation through the back oxide layer. The curve of the AT/Pt dependence on TSi /WSi for the back oxide layer (Fig. 7, curve 1 (SiO2)) grows monotonically like the T dependence on TSi/WSi depicted in Fig. 6. At the same time, during the heat dissipation through the gate oxide, the AT/Pt slowly decreases with increasing TSi /WSi (insertion in Fig. 7). This testifies to the main role played by the back oxide layer in heat dissipation and temperature setting in the center of the channel.
Fig. 7. AT/Pt dependence on TSi/WSi in cases of the heat dissipation through back oxide (curve 1) and gate oxide (curve 2) layers for the transistors of the first group
Fig. 8. Dependence of the temperature in the middle of the channel on the ratio TSi /WSi for transistors of the second group
Fig. 9. AT/Pt dependence on TSi/WSi in cases of the heat dissipation through the back oxide (curve 1) and gate oxide (curve 2, inset) layers for the transistors of the second group
3.2. Performance Analysis of nanoscale JL FinFET with different channel shapes
In order to define the role of back and gate oxide layers in SHE in transistors with different channel cross-sections, the temperature dependence (in the channel center) on TSi /WSi was simulated for transistors of the second group. With transistors of this group, the channel width and the channel cross-sectional area are constant, while the cross-sectional shape changes from rectangular to trapezoidal shape (Fig. 2). In this case, the values of TSi/WSi can be changed only in the range from 0.4 up to 0.7. The results of the simulation are shown in Fig. 8. It can be seen that the temperature in the center of the channel is practically unchanged. This is associated with a constant channel base width while the cross-sectional shape is changed. In the case of heat dissipation through the back oxide layer, AT/Pt practically does not change with the increase in TSi/WSi, as shown in Fig. 9. In the case of heat dissipation through the gate oxide layer, the AT/Pt dependence on TSi/WSi does not have a monotonic character (inset in Fig. 9). The underlined dependence does not correspond to the temperature dependency in the center of the channel on the channel cross-sectional shape. Therefore, in this case too, a back oxide layer plays the main role in heat dissipation.
4. Conclusions
The above results revealed that for nanoscale JL FinFET with the different channel cross section shapes and with a defined thickness of back and gate oxide layers, the main factors that define the temperature at the center of the channel are the thermal conductivity of the oxide materials and the contact surface area between the channel and the oxide layers. In the case of transistors with SiO2 as the back oxide layer and HfO2 as the gate oxide layer, the temperature in the channel center is mainly defined by the width of the channel base in contact with the back oxide layer. Considering an increase in the TSi/WSi ratio with a constant channel cross-sectional area, the channel temperature rises, which is associated with a reduction in the channel base width of a transistor with a rectangular cross-section. Therefore, when considering the channel shape for nanoscale JL FinFETs, in order to reduce the SHE and obtain a more reliable nanoscale device, the main focus should be given to the contact surface between the channel and the oxide layers.
References
[1] Srivastava N.A., Priya A., Mishra R.A. Analog and radio-frequency performance of nanoscale SOI MOSFET for RFIC based communication systems. Microelectronics Journal, 2020, 10473198.
[2] Shahroury F.R., Mohamad A.A. Design of a passive CMOS implantable continuous monitoring biosensors transponder front-end. Microelectronics Journal, 2019, S0026-2692(18)30866-8,
[3] Babadzhanov R.D., Palvanov S.R., Razhabov O. Equipment for intrachamber irradiation of samples by betatron Bremsstrahlung. Instruments and Experimental Techniques, 1997, 40(2), P. 154-155.
[4] Lackner E., Krainer J., Wimmer-Teubenbacher R., Sosada F., Christian Gspan, Rohracher K., Ewald Wachmann, Kock A. CMOS Integrated Nanocrystalline SnO2Gas Sensors for CO Detection. Procedia Engineering, 2016, 168, P. 297-300.
[5] Colinge J., Chi-Woo Lee, Afzalian A, Akhavan N.D., Ran Yan, Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A., McCarthy B., Murphy R. Nature Nanotechnology, 2010, 5, P. 225-229.
[6] Abdikarimov A.E., Yusupov A., Atamuratov A.E. The Effect of the Fin Shape and Thickness of the Buried Oxide on the DIBL Effect in an SOI FinFET. Technical Physics Letters, 2018, 44(11), P. 962-964.
[7] Atamuratov A.E., Khalilloev M.M., Yusupov A., Garcia-Loureiro J., Chedjou J., Kyandoghere K. Contribution to the Physical Modelling of Single Charged Defects Causing the Random Telegraph Noise in Junctionless FinFET. Applied. Sciences, 2020, 10(15), 5327.
[8] Fossum J.G., Zhou Z., Mathew L., Nguyen B. SOI versus bulk-silicon nanoscale FinFETs. Solid-State Electronics, 2010, 54, P. 86-89.
[9] Han M.H., Chang C.Y., Chen H.B., Wu J., Cheng Y., Wu Y. Performance Comparison Between Bulk and SOI Junctionless Transistors. IEEE Electron. Device Lett, 2013, 34, P. 169-171.
[10] Ahn W., Shin S. H., Jiang C., Jiang H., Wahab M.A. Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits. Microelectron. Reliability. 2018, 81, P. 262-273.
[11] Kumar A., Gupta A., Rai S., Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor. International Journal of Electronics and Communications, 2018, 95, P. 162-169.
[12] Ferhati H., Douak F., Djeffal F. Role of non-uniform channel doping in improving the nanoscale JL DG MOSFET reliability against the self-heating effects. Superlattices and Microstructures, 2017,109, P. 869-879.
[13] Zhang G., Lai J., Zhu Sh., Wei S., Liang F., Chen Ch. Numerical study on the self-heating effects for vacuum/high-k gate dielectric tri-gate FinFETs. Microelectronics Reliability, 2019, 95, P. 52-57.
[14] Liu H., Li B., Li J., Yuan B. A comparative study of self-heating effect of nMOSFETs fabricated on SGOI and SGSOAN substrates. Microelectronics Reliability, 2010, 50, P. 1942-1950.
[15] Rahimian M., Ali A. A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect. Materials Science in Semiconductor Processing, 2012,15, P. 445-454.
[16] Park S.J., Jeon D.Y., Kim G.T. Impact of fin shapes and channel doping concentrations on the operation of junctionless transistors. Microelectronic Engineering, 2019, 15, P. 50-54.
[17] Karimi F., Ali A. Electro-thermal analysis of non-rectangular FinFET and modeling of fin shape effect on thermal resistance.Physica E: Low-dimensional Systems and Nanostructures, 2017, 90, P. 218-227.
[18] Atamuratov A.E., Abdikarimov A., Khalilloev M., Atamuratova Z.A., Rahmanov R., Garcia-Loureiro A., Yusupov A. Simulation of DIBL effect in 25 nm SOI-FinFET with the different body shapes. Nanosystems: Physics. Chemistry. Mathematics, 2017, 8(1). P. 71-74.
[19] Atamuratov A.E., Xalilloyev M.M., Abdikarimov A., Atamuratova Z.A., Kittler M., Granzner R., SchwierzF. Simulation of DIBL effect in junctionless SOI MOSFETs with extended gate. Nanosystems: Physics, Chemistry, Mathematics, 2017, 8(1), P. 75-78.
[20] http://www.synopsys.com
[21] Loureiro A., Seoane N., Aldegunde M.R., Valin R., Asenov A., Martinez A., Kalna K. Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors IEEE Trans. Comput.-Aided Des. Integr.Circuits Syst, 2011, 30(6), P. 841-851.
[22] Barraud S., Berthome M., Coquand R., Casse M., Ernst T., Samson M.-P., Perreau P., Bourdelle K. K., Faynot O., Poiroux T. Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm.IEEE Electron Device Letters, 2012, 33(9), P. 1225-1227.
[23] McDaid L.J., Hall S., Mellor P.H., Eccleston W., Alderman J.C. Physical origin of negative differential resistance in SOI transistors. Electron Letters, 1989, 25(13), P. 827-828.
Submitted 3 February 2022; revised 14 February 2022; accepted 15 February 2022
Information about the authors:
A. E. Atamuratov - Physics department, Urgech State University, Urgench, Kh.Olimjan,14, 220100, Uzbekistan; atabek.atamuratov@yahoo.com
B. O. Jabbarova - Physics department, Urgech State University, Urgench, Kh.Olimjan,14, 220100, Uzbekistan; bahorba-hor1989@mail.ru
M.M. Khalilloev - Physics department, Urgech State University, Urgench, Kh.Olimjan,14, 220100, Uzbekistan; x-mahkam@mail.ru
A. Yusupov - Department of Electronics and Electrical Engineering, Tashkent University of Information Technologies, Tashkent, A.Temur,108, 100200, Uzbekistan; ayus@mail.ru
K. Sivasankaran - School of Electronics Engineering, Vellore Institute of Technology, Vellore, Tamilnadu, India; ksi-vasankaran@vit.ac.in
J. C. Chedjou - University of Klagenfurt, Klagenfurt, 9020, Austria; jean.chedjou@aau.at Conflict of interest: the authors declare no conflict of interest.
