CC BY
73
DEFECT-ORIENTED TEST PATTERN GENERATION FOR DIGITAL CIRCUITS
ELENA GRAMATOVA
Institute of Informatics of the Slovak Academy of Sciences Dubravska cesta 9, 845 07 Bratislava, Slovakia E-mail: elena.gramatova@savba.sk
Abstract. Since some conventional automatic test pattern generation systems stop at 100 % stuck-at fault coverage, not all fault sites are observable enough times to ensure sufficient detection of nontargeted defects. Defect-oriented testing is a current topic in the testing field ofmanufactured designs. Defects vary with technology, and test generation has to consider their detection. The paper is focused on test generation techniques for receiving tests of higher quality and supports the tutorial “Advanced method for defect-oriented testing of digital circuits”.
Key words: defect, fault model, test, fault coverage, probabilistic evaluation of defects, test generation
1. Introduction
The objective of testing is filtering defective chips from manufactured ones to reduce the fraction of defective parts which are evaluated as defect-free parts. Some defects, mainly in CMOS technology, are not detectable with standard test approaches and using the classical stuck-at fault (SAF) models. Quality of testing depends also on quality of test pattern generation techniques used for a circuit under test (CUT). Historically, functional and structural test patterns were used in testing. Functional testing is targeted only to function and evaluation if CUT does what it is supposed to. The functional tests are expensive for a complex circuit and not sufficient because they do not cover defects which cannot be manifested logically. The next test approach -structural testing - is used with coverage metrics based on SAF coverage. In fact, real defect coverage cannot be 100 % if the test set with 100 % SAF coverage is used. The need of high chip quality starts the progress towards defect-oriented testing. Nowadays, defect-oriented testing is the next step after structural and functional testing. Test challenge in defect-oriented testing is a current topic [1-4].
Defect-oriented testing is targeted to real wrong points of CUT developed in a specified technology. Defects can change circuit behaviour in a variety ofways. Therefore any circuit’s behavior has to be tested by an effective combination of multiple test types oriented to function, timing, current, voltage and temperature measurements.
One of the key points of defect-oriented testing is defect specification, classification and modelling. Each defect must be abstracted into faults.
The second one is generation of an efficient and optimum test set for the specified faults. It is not sufficient to generate test patterns by random or pseudo-random algorithms. Test patterns have to be generated by sophisticated deterministic algorithms and fault simulation techniques.
The objective of the paper is focused to some ideas and approaches how to improve test generation process for
R&I, 2003, Ns 3
receiving better quality of testing, i.e. how to generate a test set for ensuring better defect coverage for a manufactured and designed circuit. The paper is organized as follows. Section 2 presents defect classification and fault models for theirusability in test generation algorithms. Section 3 presents test pattern generation (TPG) algorithms. Description of one automatic test pattern generation (ATPG) system DefGen developed at the Institute of Informatics is introduced in Section 4.
2. Defects and Fault Models
Defects are physical problems that occur in silicon. Generally, a defect in an electronic system is the unintended difference between the implemented hardware and its intended design. A fault is defined as a representation of the defect at the abstract level (electrical, Boolean or functional). In general, a physical defect in a chip can produce multiple faults. Error is a wrong output signal produced by the defective system as a response to an input pattern. Defects can be classified into the following basic groups:
- Soft defects - defects which cause speed faults or show up at high speed, or produce a higher temperature; they need two or more test patterns for their activation, propagation and error observation.
- Hard defects - defects observable at all frequencies; testing can be applied at slow speed, and they need only one-pattern test set for detection.
Fault models and their relationships to real defects have to be defined for test generation. Obviously, the following fault models are used in TPG process:
- SAF model - it is a logical fault and affects the state of logical signal.
- Bridging faults represent shorts between two signals, or a signal group. Inter- and intra-gate shorts are recognized on the logical or transistor level. Inter-gate shorts are obviously detected by the SAF test set, but some intra-gate shorts are not observable at the logical level.
- Opens mean that a physical line in a circuit is broken. The resulting unconnected node is not tied to either VDD or Gnd. Mostly, these faults are recognised as soft faults.
- Delay faults mean differences from timing specifications; several possible causes for excess delay on a line can be arisen, e.g. by weak transistors, resisitive vias, etc.; gate and path delay or transition faults are used in TPG process.
In the context of test generation process we have to speak about defect manifestation. Defects can be observable in the following manners:
- by changing logical value on a node inside a circuit; it is covered by Boolean testing,
- by increasing the steady state supply current; it is provided by current measurement (IDDq testing),
- by changing timing specification; it is detected e.g. during speed testing.
All the above-mentioned testing approaches does not match perfectly (considering fault coverage); therefore all the 3 testing styles must be used in defect-oriented testing. All the testing styles need test vectors generated automatically based on an efficient TPG algorithm. Some basic principles ofTPG algorithms for functional and IDDq testing are described in the next part.
23
3. Test Pattern Generation Algorithms
Random and pseudo-random TPG algorithms are very effective at the beginning phase of the test generation process or for simple circuits (mainly with a small number of inputs/outputs and/or with a simple structure). In a complex circuit some faults are seen as resistant faults; the resistant fault is a fault requiring a special pattern for its detection (e.g. „1“ pattern is necessary to apply for SAF0 detection of NAND gate). Therefore a deterministic test pattern generation algorithm must be used for the resistant faults detection.
The another problem is a huge test pattern set generated by random orpseudo-random TPG algorithms in comparison with a test set generated by a deterministic test generation algorithm. Some graphs are presented in Figures 1 and 2 to show efficiency of random TPGs using the ISCAS ’ 85 benchmark circuits. The graphs in Figure 1 show that 60 000 random patterns have to be generated to cover the deterministic test sets for 6 ISCAS ’ 85 benchmark circuits. The graphs in Figure 2 confirm that the random TPG algorithms are effective only at the beginning phase of the TPG process. Random or pseudo-random TPGs obviously have to run with a fault simulator to calculate fault coverage and to obtain fault dictionary.
The basic principle of the deterministic TPG algorithms is test patterngenerationfora specifedfault. Eachdeterministic algorithm mostly uses the 5-value logic model using D notation (0, 1, X, D, Dnot), where X represents don’t care value, D and Dnot represent faulty values. Then, TPG process consists of the following basic procedures:
- fault activation,
- fault propagation,
- fault and values justification.
These basic steps are explained on circuit c17 from the ISCAS ’ 85 benchmark circuits presented in Fig. 3.
Some defects are not observable by logical values but they are manifested by increasing ofthe quiescent current (specially in CMOS ICs). Then, the testing technique, named IDDq testing is based upon the fact that defective circuits produce an abnormally high value of power supply current. As an example, defects modelled for NAND gate with 2 inputs -NAND2 (results for the 0,8m CMOS cell) and their coverage using the classical voltage and IDDq testing are presented in Table 1. Results of electrical simulation using the exhaustive test set for NAND gate are involved. The value “1” (“0”)
Fig. 1. Random and deterministic TPGs relationship
24 R&I, 2003, N 3
indicates that the fault can (cannot) be detected by the corresponding patterns. The list of investigated faults is on the top of the tables. Similar tables (defect libraries) can be created for each basic gate for the used technology as a basis for TPG algorithms.
The TPG process for IDDq testing is simpler than for the classical Boolean testing because the fault effect has not to be propagated towards primary outputs. It is sufficient to set up specified values on cell inputs inside CUT if IDDq measurement is applied. However, current testing is not meant to replace voltage based test methods; it is meant to augment them and increase quality and reliability of CMOS ICs. To be able to perform this type of testing a dedicated measurement unit (current monitor) [e.g. 5, 6] and a test set are needed [7-10, 12, 16]. Obviously, TPG algorithms for IDDq testing are based on simulation using e.g. a SAF test set or a random test set [8]. Then the following strategy can be used - IDDq measurement for:
- every test vector,
- supplementing test vectors,
- selective test vectors.
A test set can be also generated directly for IDDq testing using the pseudo-SAF model (SAF without its propagation to primary outputs) [7]. The basic steps are shown in Figure 4. Test vectors for basic cells of CUT can be received from defect analysis and named as fault conditions (e. g. for NAND gate there are: 10, 01, 11) for which the TPG algorithm is applied.
Various automatic test generation techniques for IDDq testing have been presented. Some of them run over huge tables with data from electrical simulation for a circuit under test [e.g. 7, 8]. The others run only for specific types offaults [e.g. 9, 10] or using an implicit fault model defined as a list of logic values for basic gates (a list of fault conditions) [12, 16].
Table 1. Voltage and current defect libraries for basic cell NAND2
Voltage a/SAFO a/ SAF1 b/SAF0 b/ SAF1 y / SAF0 y / SAF1 o Q. p2off nloff o CM c c o Q_ c O CM Q_ c o c c o CM c CO ■O O) Q_ CO ■O O) CM Q_ CO ■O O) c n2gds nldss n2dss
0 00/1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
1 01/1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0
2 10/1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1
3 11/0 1 0 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0
Current a/SAFO al SAF1 b/SAF0 b/ SAF1 O LL $ LL $ ploff 1 CM o_ nloff n2off p1on p2on C o c n2on CO ■o o> CO ■o O) CM Q. CO ■o O) c n2gds CO CO TD C n2dss
0 00/1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
1 01/1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0
2 10/1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1
3 11/0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0
R&I, 2003, N 3
25
The main problem in TPG process is to find an optimal fault condition list for the cells inside CUT. If the exhaustive test set is used for more complex gates, TPG process is too complicated, mainly for classical voltage testing. On the other hand IDDQ testing is a time consuming process because current has to be measured in the steady state of CUT during testing. Therefore the number of test patterns is also the crucial problem in the test pattern generation field for IDDQ testing. One approach, how to improve TPG process is to find the optimal set of patterns from the defect tables for the analysed CUT cell. As an example, a list of the optimal patterns: (0011, 1000, 0010, 0101, 1100) is received fromthe defect table (Table 2) for the complex gate AN1 with the following function [13]:
AN1=NOR (AND(A,B),AND(C,D)).
Localisation of real defects can be done from the reduced defect table by analysis of covered patterns for individual cells in CUT. The fault coverage can be calculated by the standard expression using the division of number of covered faults by number of all faults. But, if a probabilistic evaluation of defect occurrence is known for used cells in CUT, then more realistic fault coverage canbe calculated by the following expression:
k p.
FCd = (1 -Z ( E —)) • 100
j =1 ieDj n
where k is the total number of cells with uncovered fault conditions, j is the number of a cell with uncovered fault conditions, Dj is the set of uncovered defects in a cell j, and i is the index of uncovered defect, pi is the conditional probability of the defect i, and n is the total number of cells in the circuit. The parameter pi for the analysed cell is calculated for eachfault according to the following expression:
p. = Pi/( P1 + P2 + P3 +.+ Pm X
where P. is the probability of the specified defect as the results
of probabilistic analysis of the cell (e.g. Pi , P2, P25 for
complex gate AN1 and faults reported in Table 2) and m is number of faults (e.g. m=25 from Table 2).
Random and deterministic TPG algorithms have been implemented using such defect tables and fault conditions and they are parts of an automatic test generation system DefGen (defect-oriented test generation). The system[12, 16] generates tests for both functional and IDDq testing concurrently. The novelty in this ATPG system is the possibility to modify the list of fault conditions for each basic gate. The other innovation is the implementation of a localisation algorithm over the defect library, which could be modified by the user using different types of defects and patterns for their localisation. Some results were published in [17].
Besides of defects, which can be tested by classical voltage and IDDq testing, it is necessary to examine the timing operation of CUT. Application of SAF tests at higher speed can uncover some delay defects. Therefore test patterns have to be generated also for delay faults. A simpler delay fault model is known as the transition fault. It is assumed that all gates have some nominal delays in the fault-free circuit and that the delay of a single gate has changed. Possible transition faults of a gate are slow-to-rise and slow-to-fall faults. For detecting a slow-to-rise fault on a line, a test for SAF0 on that line is taken. This test vector (V2) will set the line to value 1 in the fault-free circuit and propagate the state of the line to a primary output. For justifying this value on the line, another vector (V1) has to precede the test vector V2, which set value 0 on the line. Now the vector-pair (V1, V2) is a test for the slow-to-rise fault on the line. Transition fault tests have been used in the industry. It is recommended that such test set should be extended by some path delay tests [5].
Deterministic TPG algorithms for IDDq testing are based on : fault injection into a circuit,
different mechanisms for: activation,
fault propagation to one of the primary outputs,
- values justification from the primary inputs
Y1
Y2
Fig. 4: Basic steps of a deterministic TPG algorithm for IDDq testing
26
R&I, 2003, N 3
Table 2. Defect tables for complex gate AN1
Fault d, Erroneous function /* Pi Input patterns t,
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 A/C not(A*C*(B+D)) 3.1100E-07 1 1 1 1
2 A/D not(A*D*(B+C)) 1.1940E-07 1 1 1 1
3 A/N1 not(B*(not(A)+C+D)+C*D) 4.9059E-08 1 1 1 1
4 A/Q not(not(A)+C*D) 6.9159E-08 1 1 1 1 1 1 1 1 1
5 A/GND not(C*D) 2.6895E-08 1 1 1
6 A/VDD not(B+C*D) 1.9847E-08 1 1 1
7 B/C not(B*C*(A+D)) 1.0477E-07 1 1 1 1
8 B/D not(B*D*(A+C)) 5,7931 E-08 1 1 1 1
9 B/N1 not(A+C*D) 5.2930E-08 1 1 1
10 B/Q not(not(B)+C*D) 3.3912E-08 1 1 1 1 1 1 1 1 1
11 B/GND not(C*D) 4.6466E-08 1 1 1
12 BA/DD not(A+C*D) 1.8972E-08 1 1 1
13 C/N1 not((A+B+D)*(A*B+not(C)+D)) 3.9147E-08 1 1 1 1 1
14 C/Q not(not(C)+A*B) 9.1480E-08 1 1 1 1 1 1 1 1 1
15 C/GND not(A*B) 1.9862E-08 1 1 1
16 CA/DD not(D+A’B) 1.4727E-08 1 1 1
17 D/N1 not((A+B+C)*(A*B+C+not(D))) 2.7604E-08 1 1 1 1 1
18 D/Q not(not(D)+A*B) 2.0036E-07 1 1 1 1 1 1 1 1 1
19 D/GND not(A*B) 2.1443E-08 1 1 1
20 DA/DD not(C+A*B) 9.9504E-09 1 1 1
21 N1/Q not(A+B) 1.3697E-07 1 1 1
22 N1/GND SAO for Q 8.4883E-09 1 1 1 1 1 1 1 1 1
23 N1/VDD not(C*D) 2.1532E-07 1 1 1
24 Q/GND SAO for Q 1.0145E-07 1 1 1 1 1 1 1 1 1
25 Q/VDD SA1 for Q 3,5661 E-08 1 1 1 1 1 1 1
4. DefGen ATPG System
The automatic test pattern generation system generates test sets in accordance with some user’s requirements considering the input patterns and the faults/defects for the circuit components. The test generation is based on using the functional fault model (the implicit fault model) for each component (cell) in a circuit description. A list of input
patterns is created for each cell defined as the fault condition list. It is included in the fault condition library ofDefGen. The list of fault conditions for the components can be determined by the defect analysis of each component at the low level or specified by the user with regard to the accepted fault model of the components. An example for the gate AN1 was introduced in the previous section. The TPG techniques implemented in DefGen are based on justification and
Table 3: Test results for the transition fault model to the ISCAS’85 benchmark circuits
circuit DefGen TPG SAF test set test set for transition faults
No of vectors coverage (%) No of vectors coverage (%)
c17 random 10 100 13 100
deterministic 6 100 15 100
c432 random 92 98.5 182 98.2
deterministic 80 98.5 211 98.2
c499 random 154 99,2 177 98,16
deterministic 127 99,2 198 98,16
c880 random 123 100 198 100
deterministic 70 100 281 100
c1355 random 117 99,7 303 99,38
deterministic 148 99,7 434 99,38
c1908 random 172 99,65 479 99,41
deterministic 168 99,66 540 99,41
c2670 random 182 95.26 372 92.73
deterministic 147 95,26 643 92,73
c3540 random 238 94.69 632 93,36
deterministic 185 94.68 827 93,33
c5315 random 202 99,4 539 98,8
deterministic 230 99,28 995 98,56
c6288 random 50 99,32 136 99,16
deterministic 139 98.08 229 98.06
c7552 random 308 94.66 684 93.86
deterministic 354 97.99 818 97.07
R&I, 2003, N 3
27
propagation of such predefined input patterns for each cell (fault conditions) in a circuit description. The following notation is used:
- Test set is a list of test patterns generated for a whole circuit.
- Fault conditions are test patterns generated for components of the circuit.
The TPG techniques implemented in DefGen use random and deterministic algorithms and a genetic algorithm running together with a fault simulator. The fault simulator also runs separately for an external test set. The deterministic technique is based on the fanout oriented TPG strategies [11], and the deductive technique is implemented in the fault simulator [5]. The accepted tool input is circuit’s description in the language used for the ISCAS ’ 85 benchmark circuits or the EDIF format (EDIF-ISCAS’85 interface is included in DefGen). The DefGen system runs for combinational circuits consisting of basic cells - AND, NAND, OR, NOR, XOR, XNOR, NOT, BUFF and some complex components (like AN1 from the previous section). The implemented test pattern generation runs at two hierarchical levels, so the test generation procedure is split into two phases:
- Test generation over the fault conditions library with the following results: lists of covered and uncovered fault conditions are produced for the individual cells of the circuit, and the fault conditions coverage is reported.
- Defect localisation based on the results of the first phase using the defect tables.
A list of uncovered fault conditions for individual cells is generated if fault condition coverage is less than 100%. After finishing the first phase of the test pattern generation, the localisation algorithm can be activated for the defect localisation over the reduced defect tables for individual cells. The goal of the defect localisation algorithm is to generate the fault’s dictionary and more real fault coverage for the test set generated by DefGen with or without the probabilistic parameters used from the defect tables.
DefGen is accessible on the internet address: http:// ups.savba.sk/diag/download/DefGen/.
5. Conclusion
Defect-oriented testing should play a central role in future test strategy. New technologies bring new defects and new problems with fault modelling. Defects must be abstracted into faults. There is a gap between academic research and industry in this field. Research in this field needs commercial support (some results of chip manufacturing, new defects manifestation). The probabilistic analysis of real defects for basic or complex cells is useful for generating a set of effective test patterns with higher fault coverage. Test generation on the hierarchical level using defect knowledge is one of the promising solutions in testing complex digital systems.
Important defect-oriented facts are IDDX, timing, stress testing and using more test sets and different types of testing.
Acknowledgements
This work has been supported by the 5 FP project IST-2000-30193: Research and Training Actions for System on Chip Design (Reason).
References: 1. Sachdev M. Defect Oriented Testing for CMOS Analog and Digital Circuits // KluwerAcademic Publisher, 1998. 2. Chakravarty S., Thadkaran P.J. Introduction to IDDq Testing // Kluwer Academic Publisher, 1997. 3. ChakravartyS. Defect Based Testing // IEEE DDECS’01 (Design and Diagnostics ofElectronic Circuits and Systems) Workshop, Gynr, 2001, invited talk. 4. Maxwell P., Aitken R. Defect-Oriented Testing // The IEEE ETW’ 0 3 (European Test Workshop) tutorial, Maastricht, 2003. 5. Bushnell M.L., Agrawal V.D. Essential of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Kluwer Academic Publisher, 2000. 6. Stopjakova V., Settey V., ManhaeveH. An On-chip Dynamic Current Monitor for IDDT Testing. In: Compendium of Papers // IEEE ETW’98 (European Test Workshop), Sitges, 1998. P. 201-202. 7. Mahlstedt U., Alt J., HeinitzM. Current: A Test Generation System for IDDq Testing. In: Proc. of 13th IEEE VLSI Test Symposium, 1995. P. 317-323.8. Mahlstedt U, HeinitzM., Alt J. Test Generation for IDDq Testing and Leakage Fault Detection. In: Proc. of DAC’92 (Design Automation Conference), 1992. P. 486-491.9. Ferguson J.F., Larrabee T. Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. In: Proc. of ITC’91, (International Test Conference), 1991. P. 492-499. 10. Bollinger S. W., Midkiff, S.F. Test Generation for IDDq Testing of Bridging Faults in CMOS Circuits. In: IEEE Trans. on Computer Aided Design ofIntegrated Circuits and Systems, Vol. 13, N° 11, November 1994. P. 1413-1418. 11. Fujiwara H. Logic Testing and Design for Testability. Cambridge, Massachusetts, MIT Press, 1985. 12. Gramatov6 E., Somorovsk6 A., Ga^par J., Manhaeve H. Test Pattern Generation System for IDDQ-Voltage Test Experiments. In: Compendium. ofPapers, IEEE ETW’98 (European Test Workshop), 1998. P.193-194. 13. Pleskacz W. Principles ofProbabilistic Analysis of Physical Defects. Design for Testability of SoC - Analog Test Tutorial, BEC‘2002 (Baltic Electronic Conference), 2002, Tallinn. 14. Pleskacz W., Kasprovicz, T., Oleszczak T., Kuzmicz W. CMOS Standard Cells Characterization for Defect Based Testing. In: Proc. of IEEE International Symposium on Defect and F ault T olerance in VLSI Systems, San Francisco, California, 2001. P. 384-392. 15. Pleskacz W., Borejko T., Kuzmicz W. CMOS Standard Cells Characterization for IDDQ Testing. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, 2002. P. 390-398. 16. GramatovaE., Ga^par J., Manhaeve H. TPG for IDDQ/Voltage Testing Based on Fault Simulation for Combinational Circuits. In: Proc. of DDECS’98 (Design and Diagnostics of Electronic Circuits and Systems) Workshop. P. 265-268. 17. Cibakova T., FischerovaM., Gramatova E., Kuzmicz W., Pleskacz W., Raik J., Ubar R. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage, Journal of Microelectronics Reliability, 42 Pergamon Press, 2002. P. 1141-1149. 18. Liu X., HsiaoM., Chakravarty S., Thadikaran P.J. Techniques to Reduce Data Volume and Application Time for Transition Test. In: Proc. ofITC’02 (International Test Conference), 2002. P. 983-992.
28
R&I, 2003, N 3
