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КОМПЬЮТЕРНАЯ ИНЖЕНЕРИЯ И ТЕХНИЧЕСКАЯ ДИАГНОСТИКА Т^г
УДК 681.32
TESTING OF RE-SYNTHESIZED CORES
EDUARDAS BAREISA, VACIUS JUSAS, KESTUTIS MOTIEJUNAS,
RIMANTAS SEINA USKAS
In this paper we consider the impact of circuit realization on the fault coverage of the test set. We have performed various comprehensive experiments with combinational and sequential benchmark circuits. Our experiments with combinational circuits show that the test sets generated for a particular circuit realization fail to detect in average only less than one and a half percent of the stuck-at faults of the re-synthesized circuit but in some cases this figure is more than nine percent. The double test sets declined almost twice both the maximum and the average percent of undetected faults. The experiments exhibit that the supplement of the test set with sensitive adjacent test patterns significantly increases the fault coverage of the resynthesized core. The experiments with sequential circuits exhibit that the fault coverage’s surprisingly coincide.
1. Introduction
Many recent system-on-a-chip (SOC) ICs incorporate pre-designed and reusable circuits, variously referred to as intellectual property (IP) circuits or cores. Such circuits are frequently supplied by third-party vendors and are extremely hard to test when embedded in an SOC because their functions are specified only in high-level terms. This is done either to protect the circuits’ IP content or else to allow system designers to synthesize their own low-level (gate-level) implementations. The tests can be generated for a high level description in order to reuse them for all possible implementations [1]. However, such tests usually can not guarantee detection of all specified faults in all possible implementations. Consequently, if we consider realization-independent testing, we can only speak about such realizations that fulfil specific requirements or have a particular structure [2, 3].
In this paper we will analyze the situation when the tests are generated for a particular implementation. In this case there naturally rises a question—can a test generated for one implementation be used for another implementation? The same core can have distinct descriptions; e. g. a parallel or sequential carry can be realized in an adder. Naturally, that a test generated according to one structure may not detect all specified faults of another structure. This case is studied in [4], where it is shown that the deviation of the stuck-at fault
coverage can be up to 18% high. The employment of different synthesis tools can have an influence on the test quality as well.
In this work we will analyze such implementations that are generated by the same synthesis tool according to the same description, changing only the target library used during the synthesis. We will explore the test quality of one realization for detecting faults of other realizations. As well we will analyze how the tests for specified faults can be modified or expanded in order to enhance the fault coverage of other realizations and we will evaluate such possibilities by an experiment.
2. Related work
The possibilities of using a test obtained for one realization for testing faults of another realization are studied in [4] and [5]. In [4] H.Kim and J.P.Hayes synthesized two different gate-level implementations of the example circuits, one for low area and another for high speed. The stuck-at fault tests for the gate-level designs were generated using the conventional ATPG program Atalanta [6]. It is stated that Atalanta tests provide 100% stuck-at fault coverage only for the gate-level designs at which they were targeted and fairly poor coverage for the others. The most impressive number is provided for the ISCAS’85 benchmark circuit c880, namely 100% stuck-at fault test for high speed realization detects only 82.2% stuck-at faults of the low area realization.
The same experiments are described in [5] too. It is interesting to note that the authors of both papers for the experiments used identical tools — the Synopsys Design Compiler and ATPG program Atalanta. But in [5] it is reported that for the ISCAS’85 benchmark circuit c880 99.8 % stuck-at fault test for high speed realization detects already 99.7% stuck-at faults of the low area realization. Such inconsistence was the main inspiration for us to perform our own experiments.
The possibilities of supplementing or expanding a particular realization test having a purpose to enhance test quality for detecting of various defects are analyzed in [7-11]. The defect coverage that can be achieved with test sets for stuck-at faults may not be sufficient. In order to increase the defect coverage of a test set for stuck-at faults, in [7] and [8] и-detection test sets were considered. An и-detection stuck-at test set is one where each stuck-at fault /is detected by и different input patterns, or by the maximum number of input patterns if/has fewer than и different input patterns that detect it. Experiments with и-detection stuck at test sets reported in [7] and [8] show that it is possible to enhance the defect coverage using this approach. In various types of experiments performed in [9] and [10] и-detection test sets were shown to be useful in achieving a high defect coverage for all types of circuits and for different fault models. Another possibility called sensitivity of input patterns is proposed in [11]. Under a sensitive pattern, a change in a single input value causes a change in at least one output value. Such patterns are likely to be sensitive to the presence of faults, and are likely to result in fault detection [11]. It worth to note, that all results presented in [4-11] concern only combinational circuits.
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3. The influence of circuit re-synthesizing on the fault coverage. Combinational circuits
The core can be synthesized by different electronic design automation systems and mapped into different cell libraries and manufacturing technologies. An important issue is how the test set of the core covers the faults of new implementations, which are done by the same synthesizer. The non-redundant ISCAS’85 benchmark set has been selected for experiments. The original ISCAS’85 circuits have been re-synthesized with the Synopsys Design Compiler program by the default mode and by using the AND-NOT cell library of two inputs. The following three realizations have been analyzed: R1—the non-redundant ISCAS’85 benchmark circuit; R2 — Synopsys Design Optimization, the target library — class.db (the default mode); R3 — Synopsys Design Optimization, the target library — and_or.db
We can see the number of stuck-at faults for each realization in Table 1 (D — the difference between maximum and minimum numbers, % - the percent of the difference to the maximum number). The percent of the difference between maximum and minimum numbers of stuck-at faults to the maximum number of stuck-at faults varies from 8 to 53. It demonstrates the diversity of realizations and the impact of the target library on the design synthesis.
The test sets have been generated for each original ISCAS’ 8 5 circuit and for each re-synthesized circuit by a deterministic algorithm and by a random & deterministic algorithm. The deterministic algorithm
Table 1
The number of stuck-at faults
Circuit R1 R2 R3 D %
C432 507 426 460 81 16
C499 750 978 1246 496 40
C880 942 857 928 85 9
C1355 1566 1316 1406 250 16
C1908 1862 876 1224 986 53
C2670 1990 1500 1658 490 25
C3540 3126 2474 2520 652 21
C5315 5248 3879 4130 1369 26
C6288 7638 6680 7498 958 13
C7552 7039 4578 4798 2461 35
Total 30668 23564 25868
Table 2
The size of test sets
Circuit D R&D
R1 R2 R3 R1 R2 R3
C432 57 46 45 63 47 50
C499 54 74 80 63 78 90
C880 62 49 50 54 51 54
C1355 86 83 80 92 100 110
C1908 118 57 75 123 60 81
C2670 105 120 116 113 120 114
C3540 167 143 147 172 144 143
C5315 130 99 89 130 92 97
C6288 43 47 34 34 49 39
C7552 211 146 138 209 154 136
Total 1033 864 854 1053 895 914
has been used if the random search did not reach a 100 % fault coverage. The test size oftest sets with a 100% stuck-at fault coverage is displayed in Table 2 (D- Synopsys deterministic test patterns, R&D- Synopsys Random and deterministic test patterns).
Table 3
Undetected faults for different realizations
Circuit D R&D
R1 R2 R3 R1 R2 R3 Total
C432 R1 0 21 (4,14%) 16 (3,16%) 0 13 (2,56%) 11 (2,17%) 61
R2 11 (2,58%) 0 9 (2,11%) 4 (0,94%) 0 7 (1,64%) 31
R3 1 (0,22%) 7 (1,52%) 0 0 8 (1,74%) 0 16
C499 R1 0 6 (0,80%) 16 (2,13%) 0 8 (1,07%) 16 (2,13%) 46
R2 44 (4,50%) 0 8 (0,82%) 34 (3,48%) 0 8 (0,82%) 94
R3 116(9,31%) 22 (1,77%) 0 48 (3,85%) 12 (0,96%) 0 198
C880 R1 0 29 (3,08%) 18 (1,91%) 0 13 (1,38%) 17 (1,80%) 77
R2 0 0 2 (0,23%) 1 (0,12%) 0 1 (0,12%) 4
R3 0 7 (0,75%) 0 0 4 (0,43%) 0 11
C1355 R1 0 8 (0,51%) 12 (0,77%) 0 8 (0,51%) 16 (1,02%) 44
R2 25 (1,90%) 0 12 (0,91%) 0 0 8 (0,61%) 45
R3 20 (1,42%) 10 (0,71%) 0 0 0 0 30
C1908 R1 0 158 (8,49%) 129 (6,93%) 0 164 (8,81%) 120 (6,44%) 571
R2 3 (0,34%) 0 12 (1,37%) 2 (0,23%) 0 11 (1,26%) 28
R3 1 (0,08%) 41 (3,35%) 0 0 48 (3,92%) 0 90
C2670 R1 0 24 (1,21%) 21 (1,06%) 0 21 (1,06%) 29 (1,46%) 95
R2 36 (2,40%) 0 4 (0,27%) 39 (2,60%) 0 6 (0,40%) 85
R3 29 (1,75%) 8 (0,48%) 0 40 (2,41%) 9 (0,54%) 0 86
C3540 R1 0 24 (1,82%) 21 (1,70%) 0 21 (1,95%) 29 (1,79%) 227
R2 36 (0,24%) 0 4 (0,24%) 39 (0,16%) 0 6 (0,16%) 20
R3 29 (0,24%) 8 (0,32%) 0 40 (0,24%) 9 (0,32%) 0 28
C5315 R1 0 72 (1,37%) 77 (1,47%) 0 66 (1,26%) 96 (1,83%) 311
R2 9 (0,23%) 0 17 (0,44%) 10 (0,26%) 0 25 (0,64%) 61
R3 11 (0,27%) 10 (0,24%) 0 10 (0,24%) 13 (0,31%) 0 44
C6288 R1 0 0 0 0 0 0 0
R2 39 (0,58%) 0 21 (0,31%) 59 (0,88%) 0 28 (0,42%) 147
R3 18 (0,24%) 27 (0,36%) 0 41 (0,55%) 9 (0,12%) 0 95
C7552 R1 0 190 (2,70%) 241 (3,42%) 0 233 (3,17%) 236 (3,35%) 890
R2 24 (0,52%) 0 44 (0,96%) 12 (0,26%) 0 37 (0,81%) 117
R3 17 (0,35%) 16 (0,33%) 0 13 (0,27%) 16 (0,33%) 0 62
Total 416 721 718 323 704 732
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The random test generation increased the test size for all realizations. The test sizes for the realization of the circuits c432, c880, c2670, c6288 are very similar. These circuits have the smallest dispersal of stuck-at faults after re-synthesizing.
The number of undetected faults of each test set for each circuit realization was computed. Table 3 gives the results of the experiments. Deterministic test sets have been generated for each realization R1, R2, R3 of the benchmark circuits. The fault simulation gives the number ofundetected faults for each realization (columns R1, R2, R3). Of course, the number ofundetected faults is zero for realizations and tests, which were generated for that particular realization. The test set, generated for the realization R1 of the circuit c432 detects all faults of the realization R1. However, this test set doesn’t detect 11 faults of the realization R2 and 1 fault of the realization R3. In general, the tests reused for other realizations in most cases fail to detect all stuck-at faults. The random and deterministic generated test sets mainly detect more faults as compared to the deterministic generated test sets (the last row of Table 3). The test sets generated for re-synthesized benchmark circuits detect fewer faults on original benchmark circuits (the last column of Table 3). Only in two cases the number of undetected faults for an original benchmark circuit is smaller than the number of undetected faults after resynthesizing. The maximum percent (116/1246) = 9.3 % of undetected faults for deterministic generated test sets has been got for the original realization of the C499 circuit. The maximum percent (164/1862) = 8.8 % of undetected faults for random and deterministic generated test sets has been got for the synthesized C1908 circuit with the target library — class.db.
Each test set generated for one realization was reused for two other realizations. The average percent ofundetected faults for the deterministic generated test set and for the random and deterministic generated test set is given in Table 4 (F-Ri+Rj — the number of stuck-at faults of two realizations Ri and Rj, U_Ri+Rj — the number of
undetected faults of two realizations Ri and Rj, D_T_Ri
— the deterministic test set generated for the realization Ri, R_D_Ri — the random and deterministic test set generated for the realization Ri).
The average percent ofundetected faults doesn’t exceed 1.5 %. The maximum percent of undetected faults for two realizations reaches (160/2224)= 7.19% in case of test sets for the realization R1. It reaches (212/3086) = 6.87% in case of test sets for the realization R2 and it reaches (141/2738) = 5.15% in case of test sets for the realization R3.
4. Enhancement of the independency of the test from realizations
As it is reported in [7-10], и-detection test sets are useful in achieving higher defect coverage for all types of circuits and for different fault models. We applied merged test sets for testing as a double-detection approach. One set is a deterministic generated test set and the other set is a random and deterministic generated test set. Both test sets have different test patterns and each of them detects all faults of the target realization. The numbers ofundetected faults of double test sets are given in Table 5 (F-Ri+Rj — the number of stuck-at faults of two realizations Ri and Rj, U_Ri+Rj
— the number ofundetected faults of two realizations Ri and Rj, TRi - the size of double test sets for the realization Ri).
The average percent of undetected faults in case of double-detection test sets declined more than twice. Also the maximum percent ofundetected faults declined till 2.20 %, 4.21 % and 2.92 % for the realizations R1, R2 and R3, respectively.
Another possibility to enhance the test quality lies in using the sensitive adjacent input vectors [11].
Definition 1. Two input vectors are adjacent if they differ in the value of a single input. The Hamming distance between adjacent input vectors is one [11].
Table 4
The number of stuck-at faults and undetected faults
Circuit F_R2+R3 U R2+R3 F_R1 +R3 U R1+R3 F_R1+R2 U R1+R2
DTR1 R TR1 DT R2 R TR2 D T R3 R T R3
C432 886 12 1,35% 4 0,45% 967 28 2,90% 21 2,17% 933 25 2,68% 18 1,93%
C499 2224 160 7,19% 82 3,69% 1996 28 1,40% 20 1,00% 1728 24 1,39% 24 1,39%
C880 1785 0 1 0,06% 1870 36 1,93% 17 0,91% 1799 20 1,11% 18 1,00%
C1355 2722 45 1,65% 0 2972 18 0,61% 8 0,27% 2882 24 0,83% 24 0,83%
C1908 2100 4 0,19% 2 0,10% 3086 199 6,45% 212 6,87% 2738 141 5,15% 131 4,78%
C2670 3158 65 2,06% 79 2,50% 3648 32 0,88% 30 0,82% 3490 25 0,72% 35 1,00%
C3540 4994 12 0,24% 10 0,20% 5646 65 1,15% 69 1,22% 5600 59 1,05% 60 1,07%
C5315 8009 20 0,25% 20 0,25% 9378 82 0,87% 79 0,84% 9127 94 1,03% 121 1,33%
C6288 14178 57 0,40% 100 0,71% 15136 27 0,18% 9 0,06% 14318 21 0,15% 28 0,20%
C7552 9376 41 0,44% 25 0,27% 11837 206 1,74% 239 2,02% 11617 285 2,45% 273 2,35%
Total 49432 416 0,84% 303 0,65% 56536 721 1,28% 704 1,25% 54232 718 1,32% 732 1,35%
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Table 5
The number of undetected faults of double test sets
Circuits F R2+R3 TR1 U R2+R3 F R1+R3 TR2 U R1+R3 F R1+R2 TR3 U R1+R2
C432 886 1 20 2 0,23% 967 93 10 1,03% 933 95 9 0,96%
C499 2224 117 49 2,20% 1996 117 10 0,50% 1728 152 6 0,35%
C880 1785 116 0 1870 100 5 0,27% 1799 104 9 0,50%
C1355 2722 1 78 0 2972 183 4 0,13% 2882 190 8 0,28%
C1908 2100 241 2 0,10% 3086 117 130 4,21% 2738 156 80 2,92%
C2670 3158 218 27 0,85% 3648 240 17 0,47% 3490 230 7 0,20%
C3540 4994 339 3 0,06% 5646 287 24 0,43% 5600 290 20 0,36%
C5315 8009 260 1 0,01% 9378 191 24 0,26% 9127 186 30 0,33%
C6288 14178 77 4 0,03% 15136 96 0 14318 73 2 0,01%
C7552 9376 420 4 0,04% 11837 300 142 1,20% 11617 274 147 1,27%
Total 49432 2086 92 0,19% 56536 1724 366 0,65% 54232 1750 318 0,59%
We investigated how much sensitive adjacent input patterns of test sets increase the fault coverage of different realizations of IS CAS ’ 8 5 benchmark circuits. The test sets extended with sensitive adjacent input vectors have been minimized by means of the fault simulation.
Initial test patterns were generated using automatic test pattern generation tool for the circuit implementation R2. This implementation denotes the optimised library class.db. The data for every circuit are displayed in two lines of Table 6. Test sets, which size is presented in the first line, were generated in the deterministic mode. Test sets, which size is presented in the second line, were generated in the random mode plus the deterministic mode in order to get 100% fault coverage.
The left half of Table 6 presents the results of the test pattern generation before the application of the procedure
Table 6
Effect of application of adjacent test vectors
Circuit Test size R1 R2 R3 Test size (adjacent) R1 R2 R3
% Nr. % Nr. % Nr. % Nr. % Nr. % Nr.
C432 46 97,4 44 100 43 98,5 40 548 100 57 100 43 100 47
47 95,9 45 100 47 98,3 45 469 99,8 61 100 47 100 52
C499 74 98,9 52 100 74 99,0 73 2837 100 56 100 74 100 81
78 99,2 57 100 78 98,2 74 3105 100 60 100 78 99,8 86
C880 49 98,6 46 100 46 99,6 46 2031 100 58 100 46 100 49
51 96,9 50 100 49 99,2 49 2092 100 73 100 49 100 53
C1355 83 99,5 77 100 83 100 79 3149 100 83 100 83 100 79
100 99,5 92 100 98 99,3 97 3868 100 95 100 98 100 102
C1908 57 91,2 56 99,7 57 96,1 54 1581 99,2 128 99,8 58 99,9 82
60 91,5 59 99,8 59 96,7 58 1679 99,5 135 99,8 59 100 86
C2670 120 98,9 106 100 116 99,5 116 7911 100 124 100 116 100 122
120 98,8 109 99,9 117 99,5 118 7873 100 131 100 118 100 124
C3540 143 98,0 141 100 138 99,7 137 4301 100 188 100 138 100 144
144 98,2 143 100 144 99,7 143 4285 100 188 100 144 100 149
C5315 99 98,7 96 99,7 97 99,7 96 9314 100 150 100 106 100 106
92 98,6 91 99,8 90 99,8 88 8713 100 146 100 98 100 98
C6288 47 100 32 100 43 99,9 43 1582 100 32 100 43 100 52
49 100 49 100 49 99,6 49 1648 100 49 100 49 100 76
C7552 146 96,8 143 99,9 142 99,7 129 13197 99,2 229 100 146 100 142
154 97,3 147 99,9 149 99,7 140 13836 99,2 211 100 152 100 100
Average 88 97,70 82 99,94 86 99,09 84 4701 99,81 113 99,98 87 99,99 92
Definition 2. The adjacent input vectors V and V* are considered as sensitive adjacent input vectors if output vectors obtained in response to V and V* are different [11].
Each input vector of length n has n adjacent input vectors, from which some input vectors might be sensitive adjacent input vectors. Sensitive adjacent input vectors can be generated for each test pattern of the test set. Since a change in the value of a single input of sensitive adjacent input vectors changes the output vector, it is likely that the presence of a fault on a path from a sensitive input to a sensitive output will be detected. The generated sensitive adjacent input vectors are likely to be sensitive to the presence of a defect, and are likely to result in higher fault coverage.
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for the sensitive adjacent patterns generation. The right half of Table 6 shows the results of the application of the sensitive adjacent patterns. The selection of the test patterns was done for three implementations of every circuit. The particular implementation of the circuit is presented in two columns: the fault coverage and the number of minimized test patterns. The minimization of test patterns was based on the results of the fault simulation. The simple rule was applied: the test pattern is valuable if it detects new faults. If we rearrange initial test patterns, we would get a different number of minimized test patterns.
If we look at the right half of Table 6 (Nr. — the number of test patterns selected according to fault simulation, % - the fault coverage), we will see bigger numbers than in the left half, except numbers of the circuits, which have a 100% fault coverage initially. Such results mean that sensitive adjacent test patterns always add their value to the fault coverage. This conclusion is valid for any implementation of the circuit. Sensitive adjacent patterns are especially good for the and_or implementation (R3). As we can see from the left part of Table 6, one test sequence of the R3 implementation had full fault coverage (100 %). After the application of the procedure for the adjacent vector generation only two test sequences (circuits c449 and c 1908) didn’t have full fault coverage for circuits of the R3 implementation. Another indicator that could emphasize the value of sensitive adjacent vectors is the number of undetected faults that is on the left and right halfs of the table. So the left half has 688 undetected faults jointly, whereas the right half has only 72 undetected faults jointly.
Adding the sensitive adjacent patterns increases the test size by an order of magnitude or more (for considered circuits on average 53 times, the increase of test size ranges from 10 times for circuit c432 to 95 times for circuit c5315). Therefore naturally raises a question — how much of the improvement in coverage that is being observed is coming from the fact that sensitive adjacent patterns are being used and how much is coming simply from the fact that so many more test patterns are being used? To get an answer of that, we made next experiment. Namely, for each circuit we have generated the same number of random patterns. The data for every circuit are displayed in two lines of Table 7.
Test sets, which size is presented in the first line, were generated in the random mode. Test sets, which size is given in the second line, are deterministic tests (the same tests presented for every circuit in the first line of Table 6) plus the same random tests. The last experiment shows that the effectiveness of the sensitive adjacent test patterns is not as high as it seemed from experimental results presented in Table 6. The fault coverage after appliance of pure random test patterns is 2,29% on average lower than in the case of appliance of sensitive adjacent test patterns, but ifwe exclude the circuit c2670 that is likely hard random pattern testable, this number will be 0,53%. Further more, ifwe compare the average fault coverage numbers between random test sets plus deterministic test sets and the test sets with sensitive adjacent test patterns (reminder, they include deterministic tests too), we get the difference only 0,08% in behalf of
Table 7
Effect of application of random test vectors
Circuit Test size R1 R2 R3
% Nr. % Nr. % Nr.
C432 500 99,8 53 99,5 48 100 48
46+500 100 54 100 50 100 48
C499 3000 100 58 100 85 100 94
74+3000 100 58 100 85 100 94
C880 2000 98,9 80 99,1 65 99,1 63
49+2000 100 85 100 69 100 67
C1355 3500 100 90 100 102 100 104
83+3500 100 90 100 102 100 104
C1908 1600 97,7 125 99,3 70 98,5 82
57+1600 98,3 133 99,8 73 99,3 89
C2670 7800 84,7 78 80,0 61 80,8 64
120+7800 99,9 128 100 118 99,6 120
C3540 4200 99,6 176 99,7 147 99,7 155
143+4200 99,9 181 100 152 100 160
C5315 9200 100 156 100 121 100 117
99+9200 100 156 100 121 100 117
C6288 1600 100 33 100 43 100 46
47+1600 100 33 100 43 100 46
C7552 13700 96,8 203 97,9 153 98,0 135
146+13700 98,7 245 100 194 100 174
Average 4710 97,75 105 97,55 90 97,61 91
5246 99,68 116 99,98 101 99,89 102
sensitive adjacent test patterns. However, we argue in favour of sensitive adjacent patterns because the selecting of test patterns among sensitive adjacent test patterns allows look for the compromise between the test length and the capability to detect faults in all realizations.
5. The influence of circuit re-synthesizing on the fault coverage. Sequential circuits
In Sections 3 and 4 we have presented the experimental results that show how the test set of the core covers the faults of new implementations for combinational circuits. In this section we are going to consider the same problem for sequential circuits. The original ITC’99 benchmark circuits [12] were chosen for experiments.
The parameters of the original ITC’99 benchmark circuits are given in Table 8. The columns are denoted as follows: Gates — the number of gates, FF — the number of flip-flops, PI — the number of primary inputs, PO — the number of primary outputs, Best fault coverage % - the best published in the papers stuck-at fault coverage of the original ITC’99 benchmark circuits
Table 8
The parameters of the original ITC’99 benchmark circuits
Circ. Gates FF PI PO Best fault cov. % Number of stuck-at faults A %
R1 R2 R3
b01 40 5 4 2 100.0 268 246 278 32 12
b02 18 4 3 1 99.22 128 126 128 2 2
b03 111 30 6 4 73.24 822 782 784 40 5
b04 394 66 13 8 89.58 2640 2614 2666 52 2
b05 570 34 3 36 40.00 3362 2880 3132 482 14
b06 48 9 4 6 94.15 346 334 336 12 3
b07 321 51 3 8 50.00 2198 2302 2488 290 12
b08 154 21 11 4 88.10 800 812 828 28 3
b09 100 28 3 1 87.23 736 758 772 36 5
b10 137 17 13 6 93.59 952 964 1078 126 12
Tot. 12252 11818 12490
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reached using test generators Hitec, RAGE, TetraMAX or GATO, R1, R2, R3— the number of stuck-at faults in the circuit realizations R1, R2, R3 respectively, A — the difference the between maximum and the minimum stuck-at faults numbers, % - the percent of the difference to the maximum stuck-at faults number.
The percent of the difference between the maximum and the minimum numbers to the maximum number of stuck-at faults, which varies from 2 to 14, is not as big as for analyzed combinational ISCAS’85 benchmark circuits.
Most sequential ATPG algorithms are the direct extensions of combinational algorithms applied to the iterative logic array model [13] ofthe circuit under test. An advanced circuit description language like VHDL gives an opportunity to apply an iterative logic array model of a sequential circuit, and in the case of the use of the combinational ATPG to manage the search space flexibly.
A test generation procedure for sequential circuits based on the iterative logic array model is described in [13]. We implemented this procedure by means of the SYNOPSYS combinational ATPG for stuck-at faults. In our experiments we stopped incrementing the length ofthe iterative logic array model when the appliance of the last twenty additional combinational copies of the circuit did not increase the fault coverage or in the case when the SYNOPSYS combinational test generator was not able to deal with such enlarged circuit.
The combinational ATPG (SYNOPSYS) generates test vectors of the length k*PI, where k — the number of combinational copies, PI — the number of primary inputs in one copy. In order to apply these test vectors to initial circuits test vectors were folded in test sequences of k test vectors of the length equal to PI each. The test sets have been generated for each original ITC’99 benchmark circuit and than reused for two other
realizations. The computer Sun Ultra 5 was used for the test generation. The results of the experiment are presented in Table 9 (Nr. — the number of test sequences, % - the fault coverage, D — the number of detected faults, U — the number of undetected faults, S
— the number of test sequences that add their value to the fault coverage).
The second test generation approach used in our experiments is based on the algorithmic level of the circuit description. The basic ideas presented [14], where it is spoken about input — output paths testing in combinational circuits, were employed for sequential circuits as well.
The algorithmic description is accomplished C. It excludes clock and reset information. Such model expresses only a function carried out by a circuit. We call such a model of the circuit a black box model. In order to generate tests based on the black box model, a fault simulation is used.
The test sets have been generated for PP faults [14] and then analyzed how well they cover stuck-at faults in all three realizations. The computer Pentium 4.3 GHz HyperThreading was used for test generation. The results of the experiment are presented in Table 10.
We cannot examine the results of experiments with sequential circuits in the same way as we examined the combinational circuits in Sections 3 and 4. The reason is that for all these circuits except circuit the b01 we do not have 100% fault coverage and therefore we do not know the numbers of redundant faults in separate realizations.
However ifwe examine Tables 9 and 10 together we can see that the fault coverage’s for all realizations in both tables surprisingly coincide. There are only two exceptions
— the fault coverage numbers in the tables differ for realizations R2 and R3 of the circuit’s b02 and b09. Afterwards additionally we made the third experiment
Table 9
The iterative logic array model. Undetected stuck-at faults for realizations
Circuit Nr. Sequence Generation R1 R2 R3
name length time % D U S % D U S % D U S
b01 18 12 1 sec. 100 268 0 8 100 246 0 8 100 278 0 7
b02 10 11 <1 sec. 99,2 127 1 6 97,6 123 3 5 98,4 126 2 6
b03 33 16 7 sec. 74,8 615 207 13 72,0 563 219 12 73,9 579 205 5
b04 74 15 54 sec. 90,7 2395 245 35 90,8 2374 240 37 91,0 2425 241 36
b05 55 257 500 sec. 50,8 1708 1654 3 56,5 1627 1253 3 55,5 1739 1393 3
b06 16 11 <1 sec. 93,5 290 20 7 93,4 312 22 8 94,3 317 19 8
b07 34 289 6000 sec. 75,0 1648 550 2 72,5 1670 632 2 73,0 1816 672 2
b08 48 65 <400 sec. 98,2 786 14 23 98,6 801 11 20 98,6 816 12 20
b09 37 81 328 sec. 87,9 647 89 12 86,3 654 104 13 84,5 652 120 13
b10 39 25 377 sec. 93,6 891 61 17 93,5 901 63 18 94,3 1017 61 18
Table 10
The black box model. Undetected stuck-at faults for realizations
Circuit name Nr. Sequence length Generation time R1 R2 R3
% D U S % D U S % D U S
b01 65 12 1 sec. 100 268 0 8 100 246 0 7 100 278 0 8
b02 28 11 1 sec. 99,22 127 1 4 99,22 125 1 4 99,22 127 1 4
b03 384 16 1 sec. 74,82 615 207 12 72 563 219 11 73,9 579 205 10
b04 890 15 2 sec. 90,7 2395 245 37 90,8 2374 240 38 91 2425 241 36
b05 24 257 1 sec. 50,8 1708 1654 2 56,5 1627 1253 3 55,5 1739 1393 3
b06 187 11 1 sec. 93,5 290 20 6 93,4 312 22 6 94,3 317 19 6
b07 36 289 1 sec. 75 1648 550 1 72,5 1670 632 1 73 1816 672 1
b08 274 65 3 sec. 98,2 786 14 20 98,6 801 11 20 98,6 816 12 19
b09 1228 81 2 sec. 87,9 647 89 16 88,1 668 90 23 88,1 680 92 26
b10 1225 25 3 sec. 93,59 891 61 22 93,5 901 63 21 94,3 1017 61 22
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using adjacent input vectors for the black box model approach. The appliance of adjacent input vectors for combinational circuits was very effective. However, it was not the same case for sequential circuits. We got exactly the same results as presented in Table 10. In our opinion there is a very high probability that the obtained stuck-at fault coverages are maximal in every particular realization for the used number of copies.
We think that there is a second possible explanation of the results of all our experiments with sequential circuits. Namely that the combinational parts of all analysed sequential circuits have simple logic and therefore the tests generated for a particular realization are equally good for other circuit realizations in almost all cases.
6. Conclusions
The tests reused for re-synthesized combinational circuits detect on average more than 98% of all stuck-at faults. The double test sets declined the maximum and the average percent of undetected faults almost twice.
The extension of a test set with the sensitive adjacent patterns is a very cheap way to adopt test patterns for the re-synthesized gate level description of the IP core.
On the base of presented results we can make a recommendation concerning the combinational IP core test suites. When the IP core is supplied to the user, it is presented at the behavioural level. Its gate-level implementation details are unavailable. Therefore the user has to synthesize gate level description herself. Test suites are supplied togetherwith IP core. These test suites reflect the behavior of the IP core and are devoted only to a particular gate level implementation. The supplied test suites of the IP core are not able to detect all faults of any synthesized gate level implementation. Therefore there is a problem how to get a test for a re-synthesized gate level implementation of the IP core. We suggest complementing the existent test suites of the IP core with all sensitive adjacent patterns orwith the subset of sensitive adjacent patterns. Then the suitable test patterns for the synthesized gate level implementation have to be selected on the base of the fault simulation. Our experiment proves that such a complement would enhance the test quality for any synthesized IP core gate level description. We believe that the practice of sensitive adjacent patterns is a very cheap way to adopt test patterns for the resynthesized gate level description of IP core, because the fault simulation is not so critical task as test generation.
The experimental results with sequential circuits show that the fault coverage’s surprisingly coincide. In our opinion there is a very high probability that the obtained stuck-at fault coverages are maximal in every particular realization for the used number of copies.
We think that there is a second possible explanation of the results of our experiments with sequential circuits. Namely that the combinational parts of all analysed sequential circuits have simple logic and therefore the tests generated for a particular realization are equally good for other circuit realizations in almost all cases. The impact of complexity of combinational parts on fault coverage can be investigated in near future. In any case, the results of realization independent testing of combinational circuits are valid for full scan sequential circuits.
References: 1. Zorian Y, Dey S, and Rodgers M. Test of Future System-on-Chips. Proceedings of the 2000 International Conference on Computer-Aided Design, pp. 392-398, November, 2000. 2. Akers S.B. Universal Test Sets for Logic Networks, IEEE trans. Computers, vol. C-22, pp. 835-839, 1973. 3. BetancourtR Derivation of Minimum test sets for Unate Logic Circuits, IEEE Trans. Computers, vol. C-20, pp1264-1269, Nov. 1971. 4. Kim H. and Hayes J.P. High-Coverage ATPG for datapath circuits with unimplemented blocks, in Proc. Int. Test Conf., pp. 577-586, Oct. 1998. 5. Yi J. and Hayes J.P. A Fault Model for Function and Delay Testing, Proc. of the IEEE European Test Workshop, ETW’01, 2001, pp. 27-34. 6. Lee H.K and Ha
D. S. On the generation of test patterns for combinational circuits. Technical Report 12-93, Department of Electrical Eng., Virginia Polytechnic Institute and State University, 1993. 7. Ma S.C., Franco P. and McCluskey E.J. An experimental chip to evalueta tets teshniques. Experimental results, in Proc. 1995 Intl. Test Conf., Oct 1995, pp 663-672.
8. Reddy S.M., Pomeranz I., and Kajihara S. On the Effects of Test Compaction on Defect Coverage, in Proc. VLSI Test Symp., Apr. 1996, pp. 430—435. 9. Pomeranz I. and Reddy
S.M. On n-Detection Test Sets and Variable n- Detection Test Sets for Transition Faults, in Proc. 17 th VLSI test Symp., April 1999, pp. 173-179. 10. Takahashi H, Sulaja K.K., Takamatsu Y. An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets, In Proc. Of the 2002 Pacific Rim International Symposium on Dependable Computing (PRDC’02), 2002. 11. Pomeranz I. and Reddy S.M. Pattern Sensitivity: A Property to Guide Test Generation for Combinational circuits, in Proc. 8 th Asian Test Symposium, 1999, pp. 75-80. 12. Corno F, M. Sonza Reorda, Squillero G. RT-level ITC99 Benchmarks and First ATPG Results. IEEE Design & Test of Computers, July-August 2000, pp. 44-53. 13. BreuerM.A., Friedman A.D. Diagnosis & Reliable Design of Digital Systems, Computer Science Press, 1976. 14. Jusas V., Seinauskas R Automatic Test Patterns Generation for Simulation-based Validation. Proc. of the 8-th Biennal Baltic Electronics Conference. ISBN 9985-59-292-1. Tallinn Technical University, October 6-9, 2002, Tallinn, Estonia, pp.295-299.
Поступила в редколлегию 20.11.2004
Рецензент: д-р техн. наук, проф. Хаханов В.И.
E. Bareisa graduated from Kaunas Polytechnic Institute in 1987. Currently he is in position of assoc. Professor at Software Engineering Department, Kaunas University of Technology, Lithuania. His research interests include high-level synthesis and VLSI test generation.
e-mail:edas@soften.ktu.lt
V. Jusas graduated from Kaunas Polytechnic Institute in 1982. Currently he is in position of assoc. Professor at Software Engineering Department, Kaunas University of Technology, Lithuania. His research interests include VLSI test generation at various levels of abstraction.
e-mail:vacys@soften.ktu.lt
K. Motiejunas graduated from Kaunas Polytechnic Institute in 1981. Currently he is in position of assoc. Professor at Software Engineering Department, Kaunas University of Technology, Lithuania. His research interest is test generation for digital circuits. e-mail:kestas@soften.ktu. lt
R. Seinauskas graduated from Kaunas Polytechnic Institute in 1972. He got his Doctor habilitus from Leningrad Energetics Institute in 1982. Currently he is in position of Professor at Software Engineering Department, Kaunas University of Technology, Lithuania. His research interest is VLSI test generation. rsei@sc-uni.ktu.lt
Address: Software Engineering Department, Kaunas University of Technology Student^ 50-406., LT-51368 Kaunas, Lithuania. Phone-number: +370 37 45 42 29
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