CC BY
7
UDC 004.052.32+681.518.5
V. V. Sapozhnikov, D. Eng. Sci.,
VI. V. Sapozhnikov, D. Eng. Sci.
The Department of "Automation and Remote Control on Railways", Emperor Alexander I St. Petersburg State Transport University, Saint Petersburg, Russian Federation
D. V. Efanov, D. Eng. Sci.
"VEGA Group"LLC, Saint Petersburg, Russian Federation;
Higher School of Transport, Institute of Mechanical Engineering, Materials and Transport, Peter the Great St. Petersburg Polytechnic University, Saint Petersburg, Russian Federation; The Department of "Automation, Remote Control and Communication on Railway Transport", Russian University of Transport, Moscow, Russian Federation
THE FEATURES OF THE COMBINATIONAL LOGIC CIRCUITS CONCURRENT ERROR-DETECTION SYSTEMS BASED ON THE SEARCH FOR SYMMETRICALLY-INDEPENDENT OUTPUTS GROUPS CONSTRUCTION
The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented.
Combinational circuit, self-checking structure, unidirectional error, symmetrical error, asymmetrical error, code with the unidirectional and asymmetrical error detection, groups of symmetrically-independent outputs
DOI: 10.20295/2412-9186-2020-6-4-532-549
1. Introduction
The methods of redundant coding are widely used in the self-checking discrete devices developing. These methods are used both at the stages of automata synthesis and at the organization of test and functional diagnosis systems [1, 2]. The features of error detection by redundant codes allow developers of discrete devices to give the properties of testability and fault detection to their structures [3].
The redundant coding is also used in the testing organization of the combinational components of discrete devices, or combination logic circuits [4]. The use of redundant coding in this case implies, on the one hand, taking into account the characteristics of error detection by the certain code, and on the other hand, taking into account the structural features of the combinational circuits themselves. Among such properties of codes, it is possible to allocate possibilities of certain type's error detection (combinations of ones and zero bits distortions) and multiplicities (number of the bits distorted at an error) [5]. From the standpoint of the combinational circuit structure it is the characteristics of its implementation: ranking of logic elements (or element groups) in the structure, the relationships between them, the presence of branches, the number of paths between the poles of the circuit with odd and even number of inversions, etc. [6]. In this situation, there are two possible ways. The first way consists in choosing a code "for" a given circuit structure: searching for a code with the desired features or selecting groups of circuit outputs for separate control by one or another attribute, etc. The second way involves a special transformation of the combinational circuit structure into some structure that is controllable by the selected code. It should be such a structure that allows occurrence of errors only of a certain type or multiplicities.
The codes that are focused on the detection and not on the correction of faults are most commonly used in the synthesis of fault detection combinational circuits. This makes it possible to obtain devices with a relatively small structural redundancy (as a rule, compared to duplication and subsequent comparison of the values of the self-titled outputs [7]). Among these codes are parity codes [8], constant-weight codes [9], codes with summation (Berger codes) [10] and their various modifications [11—13]. For example, parity codes do not detect any errors with even multiplicities, but they detect any single distortions. This property of parity codes is effectively used in organizing of the control of combinational circuits by groups of independent outputs (I-groups of outputs) or after converting the circuit structure into a circuit with one I-group of outputs [14—16]. Another example is the use of constant-weight codes and classical Berger codes with the property of detecting any unidirectional errors (this property of these codes is often used). In this case, either the search for groups of uni-directionally-independent outputs (UI-groups of outputs) is performed, or the transformation of the circuit structure into a circuit with one UI-group of outputs [17, 18]. It is possible to take into account other features of redundant codes and structures of controlled combinational circuits [19, 20].
This paper is devoted to the description of the key results of the research of the development of testing methods for combinational circuits based on the properties of codes aimed at detecting errors of certain types and multiplicities. It is proposed to organize testing of combinational circuits by the property of detecting any errors, except for multidirectional errors of even multiplicity, associated with the simultaneous distortion of the same number of zero and ones bits (symmetrical errors). This property is possessed by both constant-weight codes and Berger codes and some of their modifications.
2. Types of errors and codes with the detection of certain types of errors
The classification of errors in vectors of redundant codes proposed in [5] implies their division into several types: symmetrical, unidirectional, and asymmetrical errors. Symmetrical errors are associated with the simultaneous distortion of the same number of zero and ones bits. Unidirectional errors include errors caused by distortions of only zero or only ones bits. Asymmetrical errors occur while distorting an unequal number of zero and ones bits. It should be noted that these types of errors are distributed in various proportions in the code vectors depending on their lengths. With an increase in the length of the code vector, the proportion of asymmetrical errors increases, while the proportion of unidirectional errors gradually, while symmetrical errors, slightly decreases. For example, for the case m = 10, subject to the formation of a full set of output combinations, the proportion of unidirectional errors is approximately 0.2 %, symmetrical — 24.6 %, and asymmetrical — 75.2 %.
Among the variety of codes aimed at detecting errors, special classes of codes are detected that detect any unidirectional errors or any unidirectional errors up to the established multiplicity du — the so-called UED (m, k) and du- UED (m, k) codes. Such codes, for example, include Berger codes and Bose-Lin codes (modular sum codes). Berger codes are UED (m, k)-codes, and Bose-Lin codes are d^-UED (m, k), where the du value is determined by the value of the module selected when constructing the code [21, 22].
In [23], it was shown that in self-checking devices constructing, the possibility of detecting by some codes, in addition to any unidirectional errors, also any asymmetrical errors in data vectors can also be taken into account. We introduce the class of codes with the detection of any unidirectional and asymmetrical errors — UAED (m, k)-codes, as well as the class of codes with the detection of any unidirectional and asymmetrical errors to the established values of the multiplicities du and da, respectively — du, da-UAED (m, k)-codes. Taking into account the features of UAED (m, k) and du, da- UAED (m, k)-codes allows us to reduce the structural redundancy of the synthesized discrete devices.
In organizing of combinational circuits control with using UAED (m, k) and du, da-UAED (m, k)-codes, the two approaches described above are also possible, however, the Ul-groups expand to the so-called unidirectionally/asymmetrically-independent output groups (UAI-groups). This allows us to simplify the final structures of self-checking combinational circuits.
The search for UAI-groups of outputs is similar to the search for groups of outputs that allow only symmetrical distortions. Here we describe the search conditions for such output groups of combinational circuits.
3. Search terms for checkable output groups
We introduce the following notation: fj, f2, ..., fm} is set of combinational circuit outputs; {xp x2, ..., xn} is set of combinational circuit inputs; <&atr = {fjx, fj2fj } is
a subset of combinational circuit outputs, (j1, j2,..., jq £ {1,2,...,m}), which are distorted when the output element failure with the value of the output function yt (element G) is input into the device and when the binary vector ar = (x1 x2...x^j , where aris a binary decimal equivalent, ar £ {0,1,...,2"}, q £ {2,3,...,m} receipts on the input.
Consider the combinational circuits shown in Fig. 1.
a b
The circuit shown in Fig. 1, a refers to circuits at the outputs of which a symmetrical error may occur (Table 1). For this we have:
«0 = {/2, /3, /4};
« = {/2, f4}; ®2 = {/1, f2, /3, /4 }; «3 = {/l, f2, f4}; ®14 ={/3, •/4, /5 }; ®i5 = {^ /4, /5};
Table 1.The description of the operation of circuit Fig. 1, a in the event of faults
in the logic element G*
х1 х2 x3 /1 /2 /з /4 /5 dfx df2 д/э д/4 д/5
дУ1 дУх ду ду ду1
0 0 0 1 1 1 0 0 0 1 (1^0) 1 (1^0) 1 (0^1) 0
0 0 1 1 1 1 0 0 0 1 (1^0) 0 1 (0^1) 0
0 1 0 0 1 1 0 1 1 (0^1) 1 (1^0) 1 (1^0) 1 (0^1) 0
0 1 1 1 0 1 1 0 1 (1^0) 1 (0^1) 0 1 (1^0) 0
1 0 0 1 1 1 0 0 0 0 1 (1^0) 1 (0^1) 1 (0^1)
1 0 1 1 1 1 0 0 0 0 1 (1^0) 1 (0^1) 1 (0^1)
1 1 0 1 1 1 1 0 0 0 1 (1^0) 0 1 (0^1)
1 1 1 1 1 0 1 1 0 0 1 (0^1) 1 (1^0) 1 (1^0)
®f = {/3, /5};
= {& /4, /5 }.
At the outputs of the circuit depicted in Fig. 1, b, despite the topology, the occurrence of symmetrical errors is excluded (Table 2). For this we have:
ю? = {f2, f3, f4 };
ю1 = : {f, f2 ' f4 ' f5 };
œf = {f2, f3, f4 };
œf = = {f1, f2 ' f4 'f5 };
Ю4 = {0};
Ю = {0};
œ6 = {0};
œ7 = {f1, ff, f4 }-
Table 2. The description of the operation of circuit Fig. 1, b in the event of faults
in the logic element G*
x1 x2 x3 /1 /2 /3 /4 /5 dfi 9yi df2 9yi 9yi df4 9yi 9yi
0 0 0 1 1 1 0 1 0 1 (1^0) 1 (1^0) 1 (0^1) 0
0 0 1 0 1 1 0 0 1 (0^1) 1 (1^0) 0 1 (0^1) 1 (0^1)
0 1 0 1 1 1 0 1 0 1 (1^0) 1 (1^0) 1 (0^1) 0
0 1 1 1 0 1 1 1 1 (1^0) 1 (0^1) 0 1 (1^0) 1 (1^0)
1 0 0 1 1 1 1 0 0 0 1 (1^0) 0 0
1 0 1 1 1 1 1 0 0 0 1 (1^0) 0 0
1 1 0 1 1 1 1 0 0 0 1 (1^0) 0 0
1 1 1 1 1 0 1 0 1 (1^0) 0 1 (0^1) 1 (1^0) 0
We denote by Vtthe set of different subsets <&atr with an even number of elements; if there are several identical subsets ®fr, any one of them is included in the set V.
For Fig. 1, a we have: Vi = = {fi, f2, f3, f4},= {f2, f4},tf = {f3, f5}}.
For Fig. 1, b we have: V = = f f2, fA, f5}}.
A subset of the outputs of the combinational circuit {f., f.,..., f- } (jv j2, ..., E {1,2,...,m}) is called a symmetrically-independent group (Si-group) if the failure of the output of any element Gt in the device structure does not cause a symmetrical type error on these outputs.
Theorem 1. A failure of the output of the element Gt does not cause a symmetrical type error on the set of outputs of the control unit W = {f^, f- ,..., f- }, p E {2,3,..., m}, if the following condition:
f dfki dfkd
dyt dyt dyt
dyt dyt"' dyt
p-d
Q
Rd/2 (fh, fkd }) = 0, (1)
is satisfied for each subset of = {fk , fk ,..., fk } , such that o>tr E W h tt>fr E Vt, where
d/
fh2,...,fhp_d E{fj1,fj2,...,fjp}\{fk1,fk2,...,fkd}; the function^i2(fvA^..^fkd)
is a conjunction disjunction fkfk • ...• fk , fk e{0,1}, in which the variables have
12 d 2 d
direct values, and the rest of the variables have inverse values, and the function
2
( d/ / \\ d/ Q Rd2 (fkx, fk2,..., fkd ) is a function obtained by substituting into a function R/2
instead of designating the output functions f their representations through input variables.
Proof. Consider the left side of the equality (1). We introduce the following notation:
A(yi )JA. f. ....dfk, в y df
p-d
dyt dyt dyt dyt dyt dyt
C = Q Rdd2 (/k1,/k1,...,/kd)
V y
In accordance with the this theorem, in studying the element Gt, it is necessary to consider all possible subsets of outputs C,that are distorted when one or more vectors of input variables are received at the device input. In this case, it is enough to consider only subsets with an even number of elements, because on subsets with an odd number of outputs it is impossible to generate errors of a symmetrical type. The second feature of the considered subsets cf is that when the input vector ar arrives, the values of all the outputs included in the subset are distorted, and any other outputs are not distorted.
All subsets catr with the indicated properties are included by construction in the set Vt and must be considered by the hypothesis of the theorem. There are no other subsets C other than those indicated above.
In accordance with the hypothesis of the theorem, each subset cf £ V is considered separately.
The left side of the equation (1) contains three cofactors: A(yt), B (yt) expression A (yt) defines those input vectors, upon receipt of which the values of all the outputs included in the considered subset at are distorted. The expression B (yt) captures those input vectors, upon receipt of which all the outputs of the device that are not included in the subsets rof are not distorted. The product A (yt )B (yt) allows you to calculate all those input vectors, upon receipt of which only those outputs that are part of a subset of (and all at the same time) are distorted, and not one of the outputs that do not belong to this subset is distorted. It is necessary to check the possibility of a symmetrical error especially for these input vectors.
For this purpose, the left part of expression (1) includes the cofactor C, which allows calculating the D (cDtr ) set of all input vectors, upon receipt of which, in principle, symmetrical errors may occur. A symmetrical error is possible if the half of the output functions on the input vector in a subset cf take the value 0, and the rest take the value 1. An expression Rj2 /,/^,...,/kd ), represented as a function that depends on variables /k , / ,..., /k , defines combinations of these variables that meet the specified condition. The replacing in this expression the notation of the output functions by their representations through the input variables allows us to define the set D (cotr
If A (yt )B (yt )C ^ 0, then this means that there is at least one input vector, upon receipt of which a symmetrical error occurs. If there is an expression A(yt )B (yt )C = 0 for all subsets rof £ V, then the failure of the output of the element Gt on the considered set W of the outputs of the combinational circuit does not cause symmetrical errors on any input vector.
The theorem is proved.
For the circuit of Fig. 1, a we consider the set W = {/1, /2, /3, /4, /5} and the element G*. To verify the conditions of the theorem regarding the element G* it is necessary to verify condition (1) for three subsets: {f,,f4}, f3,fj and fj,f,,f3,fj.
For the subset f, f} we have:
f df4
df df df5
Q Rd f f 4 )
dy1 dy1 dy1
We calculate the derivatives (see formula (2) and Table 1):
d/4 -w -
df1 _ - f=~ f — — _
— X Xo, — X, — X \\ Xi Xo,
r\ i 27 r\ i" o i i 37 r\
dJi dyi dyi dyi
— Xi \\ Xi X2 \\ Xi X3,
df5
dyi
We calculate the following expressions for checking the condition (1):
/ d/4_-/-w -,
4 y )
dJi dyi
Xi ( Xi \\ Xi X2 \\ XiX3 )— Xi ;
X
(2)
(3)
B ( )—f f f—= \ — _—— . B (yt ) — o 'o 'o — XiX2 ' Xi \ Xi X3 ' Xi — Xi X2 X3 '
dyi dyi dyi
(4)
Ri2 f f4 )— f2 f4 V ff
Q
d/ R/2
(f2, f4 ) — (xi \\ XiX2 )xIX2 \\ X2X3 \\ Xi \\ XiX2 (xIx2 \\ X2X3 ) — Xi \\ Xi(5)
As a result, we have:
Xi ' Xi X2 X3
(Xi \\ Xi X2 ) — Xi X2 X3 0.
Since the left side of the obtained expression is not equal to zero, the condition of the theorem is not fulfilled and the fault of the element G* causes a symmetrical error. The left side of the resulting expression defines a function that defines the input vectors for which this error occurs. In this case, it is a vector Xj x2 x3.
For the circuit, shown in Fig. 1, b, we also consider the subset fj, fj, f3, fj, f5} and the element G*. In this case, verification of condition (1) is required for only one subset
/ fv /<> /5}.
In this case
Rd/2 (fl, f2, f4, fs ) =
= /1/2 f4 /5 V /1/2/4 /5 V f f2 /4/5 V f/2/4 f5 V ff /4/5 V /J2/4/5
5'
Q
Rd (fi,f2,/4,/5)
= 0.
Therefore, condition (1) is satisfied and the failure of the element G* does not cause symmetrical errors on the set of all outputs of the circuit. The following statement is obvious.
Theorem 2. A subset of the outputs of the combinational circuit {fi, fi ,..., fi }
J1 J2 J p
j j2,..., jp E {1,2,...,m}) is a Si-group when each element in its structure satisfies the conditions of Theorem 1.
Based on Theorems 1 and 2, it is possible to construct effective algorithms for searching for Si-groups of outputs and using these groups to obtain completely verifiable structures of combinational logic circuits using UAED (m, k) and du, da- UAED (m, k) codes by analogy with how this was done in [3, 18].
4. The inputs of the logic elements fault detection
In all studies devoted to the synthesis and analysis of self-checking discrete devices, only stuck at-faults of the outputs of logic elements are considered and modeled. However, stuck at-faults also include faults in the individual inputs of the elements that are connected to the inputs of the device. For example, the previously considered circuit (Fig. 1, a) contains 13 stuck at-faults of the outputs of the logic elements and 15 stuck at-faults of the inputs of the logic elements.
Condition (1) allows us to formulate the following statement.
Theorem 3. If a fault in the output of a logic element in a combinational circuit does not cause a symmetrical type error on the set of outputs of the device {fj, fj ,..., fj } (j, j2,..., jp E {l,2,..., m}), then a stuck at-faults in the input of the same element does not cause the same error.
Proof. In fact, consider the element G at the output of which the function y is realized. Let element G have an input xi * that is connected directly to the input of the device xt. On the second input, some function Fl (x) is implemented. Consider the case when an element G implements a conjunction and enters into the system of realization of a function f given in disjunctive normal form. In general, such a scheme can be represented in the form of the device shown in Fig. 2.
^iM—
E>
F2(x)—
Figure 2. Combinational circuit
f{xU—>xi>—>xn)
The function
f (x) — (x* Fi (x))F2 (x)\ F3 (x) — yF2 (x)\ F3 (x),
(6)
where F1 (x), F2 (x) and F3 (x) are some arbitrary functions of the variables x1, ..., x,,..., xn, is implemented at the output of the circuit.
The input variable xi that is fed to the input of the element is indicated with a superscript xi *. This index means that the failure of the input of the element G corresponds to fixing the variable xi * to a constant, and the variables x. received at the inputs of other elements of the circuit are not distorted.
To calculate Boolean differences, we apply the formula
d/ (x) =
dXi (7)
= [ y (xl,..., xi xn )© y (xl,...,0,..., xn )]v^./ (xl,..., xix„ )© y (xl,...,1,..., xn ).
In this case, we have (see formulas (6) and (7)): if xi* = 0, then y = 0 and f(xv ...,0,...,xn) = F3(x); if x* =1, then y = F (x) and/(xp...,1,...,xn)= F (x)F2 (x)v VF3(x).
Then
ddXX) — [ f (x) © F3 (x)] \ [f (x) © (Fi (x)F (x) \ F3 (x)) On the other hand, we have:
^ — [ f (x)© (0 ' F2 (x)\ F3 (x))] \ [ f (x)© (i ' F2 (x)\ F3 (x)) — [ f (x)© F3 (x)] \ [ f (x)© (F2 (x)\ F3 (x))
(8)
(9)
Let's compare expressions (8) and (9).
Each of the derivatives consists of two functions enclosed in square brackets, which are interconnected by a disjunction sign. Consider the functions enclosed in second square brackets. The relations are
Fi (x)F> (x) \ F3 (x) ^ F2 (x) \ F3 (x),
(10)
f (x) © (f (x) V F (x))^ f (x)e (f2 (x) V F (x)).
(11)
Since in both expressions (8) and (9) the functions enclosed in the first square brackets are identical, it follows from (10) and (11) that
df (x) df (x) dxt dy
(12)
Thus, the Boolean difference of a variable xi * contains only those input sets that are included in the Boolean difference of the output of the element G.
The theorem is proved.
The Table 3 and 4 shows the Boolean differences for the inputs x2 and x3 of the element G* in the diagram Fig. 1, a. From a comparison of the Tables 1 and 3, 4 it follows that relation (12) holds in all cases. For example:
df _-
дУ1 (x2 )
df2 :
дУ1 (x3 )
xi x2 x~3
дУ1
xix2,
xi x2
f дУ1
_ x1 , etc.
It can be seen from expression (7) that the Boolean difference combines two checking tests. In the first square brackets, the checking test of the input (or output) of the element for the "stuck-at-0" fault is calculated, and in the second square brackets — for the "stuck-at-1" fault. Therefore, the value of the Boolean difference is determined only
Table 3. The description of the circuit Fig. 1, a in case of input x, faults
x1 x2 x3 /1 /2 /3 /4 /5 df1 дУ1 df2 дУ1 дз ду1 df4 ду1 df5 ду1
0 0 0 1 1 1 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 1 (0^1) 0 1 (0^1) 0
0 1 0 0 1 1 0 1 0 0 0 0 0
0 1 1 1 0 1 1 0 1 (1^0) 1 (0^1) 0 1 (1^0) 0
1 0 0 1 1 1 0 0 0 0 0 0 0
1 0 1 1 1 1 0 0 0 0 1 (1^0) 1 (0^1) 1 (0^1)
1 1 0 1 1 1 1 0 0 0 0 0 0
1 1 1 1 1 0 1 1 0 0 1 (0^1) 1 (1^0) 0
Table 4. The description of the circuit Fig. 1, b in case of input x3 faults
x1 X2 X3 /1 /2 /3 /4 /5 dyi dyi dyi df4 dyi dyi
0 0 0 1 1 1 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 0 0 0 0
0 1 0 0 1 1 0 1 1 (0^1) 1 (1^0) 1 (1^0) 1 (0^1) 0
0 1 1 1 0 1 1 0 1 (1^0) 1 (0^1) 0 1 (1^0) 0
1 0 0 1 1 1 0 0 0 0 0 0 0
1 0 1 1 1 1 0 0 0 0 0 0 0
1 1 0 1 1 1 1 0 0 0 1 (1^0) 0 1 (0^1)
1 1 1 1 1 0 1 0 0 0 1 (0^1) 1 (1^0) 0
by the values ofthe functions f (x1,...,0,..., xn ) and f (x1v..,1,..., xn ) and does not depend on the structure of the subcircuit, which connects the output of the element G with the output of the device, and the structure of the subcircuit that implements the function F1 (x) at the second input of the element G, because their verification tests are preserved with equivalent transformations of combinational devices. In this regard, relation (12) is satisfied for any implementation of the function f (x).
Denote by yt (xi) the input variable, which is fed to the input of the element G. Then the condition under which the input yt (xi) failure does not cause a symmetrical error on the set of outputs of the combinational circuit W = {fj, f j ,..., fj } is written as follows:
■X
X
dyt (X ) dyt (xi ) dyt (xi )
Rd2 (fkx, fkd )
h2
Q
dyt (xi) dyt (xi y dyt (xi)
Let's compare the expressions (1) and (13). It follows from (12) that
(13)
= 0.
dfj2 f
J2
dyt (xi ) dy/ f f f f
dyt (xi ) dy/ dyt (xi ) dy/ dyt (x ) dy/ dyt (x ) dyt
p-d
'p-d
dyt (xi ) dyt
Then we have:
A(yt (Xi))
B (yt (Xi ))--
f dfh
dyt (x ) dyt (xi ) dyt (x )
dfh d/h
dfh
p—d
dyt (xi ) dyt (xi ) dyt (xi )
A( yt )
B ( yt )
dyt dyt dyt
dyt dyt- dyt
p—d
(14)
(15)
From (14) and (15) it implies that
A(yt (Xi))B(yt (Xi))- A(yt)B(yt).
(16)
The validity of statement (1) follows from the fact that in expressions (1) and (13) the third factor C is the same.
For the circuit of Fig. 1, a we consider a subset of outputs {f, f4} and the fault of input x2 of the element G*. Expression (13) has the implies form
dyx (x2 ) dyx (x2 )
df f
d/5
дУ1 (X2 ) дУ1 (X2 ) дУх (X2 )
Q
Ri2 (//2, f.4 )
(17)
We calculate the derivatives (see the Table 3):
■f_— XXX _•/2 — x x _/3
дУ1 (X2 )
дУ1 (X2 )
dfs
dy, (x2)
dy, (x2 )
— X1X2 X3.
Xi X2,
df.
dy, (x2 )
—x
We calculate the following expressions for checking condition (17):
df f - -
A(yt (X2 ))
дУ1 (X2 ) дУ1 (X2 )
( X1X3 ) X3 - X1X3,
(18)
В (yt (X2 ))
dfi д/з
df5
дУ1 (x2 ) дУ1 (X2 ) дУ1 (X2 )
— (xl V x2 V x3) (xl V x3) (xl V x2 V x3) — x3 V xlx2
(19)
From a comparison of (18) and (3) it implies that (see (16))
df2 df4 ; df 2 df4
(x2) dy1 (x2) dy1
Similarly, a comparison of (19) and (4) implies that
д/1 д/3 д/s а/ д/3 д/5
Then
дУ1 (x2 ) дУ1 (x2 ) дУ1 (x2 ) дУ1 дУ1 дУ1
A (yt (x2 ))B (yt (x2 )) = (xix3 ) (x3 V xi x2 )
— x1 x2 x^ ^ A (yt )B (yt ) — (x1) (x1 x2 x^ ) — x1 x2 x^.
From (5) it follows that the fault of the input x2 of the element G* admits a symmetrical error. The Theorem 3 allows us to formulate the following statement.
Theorem 4. When organizing the testing of a combinational circuit according to the UAED (m, k) or do, da-UAED (m, k)-code, for detecting all stuck at-faults of the inputs and outputs of logic elements, it is enough to consider only faults of the outputs of logic elements.
We also note that in combinational circuits, faults may occur in the lines that connect the device input to the inputs of several logic elements. In this case, a multiple malfunction occurs, in which the input signals of several logic elements are fixed into constants. The solution to the problem of detecting faults of this type is possible due to the imposition of certain requirements on the structure of the electrical installation, taking into account the properties of the controlled device [24].
5. The combinational device structure construction
The completely self-checking structure of the combinational circuit is constructed as follows. We find Si-groups of outputs that meet the conditions of the Theorem 2. Each Si-group is controlled using a separate checking based on the UAED (m, к) или du, da-UAED (m, k)-code. The control outputs of all control circuits are combined at the inputs of a self-checking two-rail signal compression circuit to obtain one control output.
The obtaining the required set of Si-groups of outputs, it is advisable to conduct one of the following methods.
The first method is as follows. First, by analyzing all possible subsets of the outputs of the combinational circuit, a complete set of the Si-groups of outputs is found. Then, the minimal subset of the Si-groups is determined, which includes all outputs of the circuit.
In the second method, a set containing all m outputs is considered first. If it does not satisfy the condition of Theorem 2, then all possible subsets with the number of outputs m—1, etc., are considered. When the SI-group is found, all the outputs included in it are excluded from further consideration. The process ends when all the outputs of the combinational circuit are included in any SI-group.
The alternative option to search for SI-groups of outputs is a special transformation of the structure of the combinational circuit into a structure whose outputs form a single SI-group. The method for converting circuits into circuits with the SI-groups is similar to that described in [25] for obtaining UI- and UAI-groups.
6. Conclusion
The article revealed and formalized simple conditions under which the selected set of outputs of the combinational circuit forms the SI-group. The search for the SI-groups of outputs on the set of outputs of the circuit, in turn, allows to determine all possible options for splitting into groups of outputs for effective control based on UAED (m, k) or d , d - UAED (m, k)-codes.
u' a v ' '
As shown in [18] by the example of searching for UI-groups of outputs, the use of one of the UAED (m, k)-codes, the Berger code, makes it possible in practice to organize self-checking discrete devices with redundancy less than when duplicating. In some cases, more than a 50 % reduction in redundancy can be achieved. Expanding the set of outputs to the UAI-group allows to further reduce the redundancy of the self-checking circuit. The same can be concluded for the method of converting circuits into circuits with UAI-outputs, because the conversion will require reservation of a smaller number of internal logic elements than by the method proposed in [18]. As shown in the last source, the complexity of the technical implementation of the original circuit when converted into a device with a controllable structure increases on average by 16 %. The use of UAI-groups in the combinational circuits synthesis can reduce this estimate. The search for the SI-groups of outputs is, in a sense, identical to the search for UAI-groups of outputs, but it is much simpler.
It should be noted that, because the conditions formed are based on the functional principle of describing the operation of a combinational circuit, the results obtained are not oriented only to circuits implemented on logic elements. The field of their application is much wider: the results can be applied to the construction of self-checking combinational circuits on a modern programmable element base.
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The paper is submitted for publication by Raimund Ubar,
a member of the editorial board. Received: May 19, 2020, accepted: June 01,2020
В. В. Сапожников, д-р техн. наук Вл. В. Сапожников, д-р техн. наук
Кафедра «Автоматика и телемеханика на железных дорогах» Петербургский государственный университет путей сообщения Императора Александра I, Санкт-Петербург
Д. В. Ефанов, д-р техн. наук
ООО «ВЕГА Групп», Санкт-Петербург
Высшая школа транспорта Института машиностроения, материалов и транспорта Санкт-Петербургский политехнический университет Петра Великого, Санкт-Петербург Кафедра «Автоматика, телемеханика и связь на железнодорожном транспорте» Российский университет транспорта, Москва
ОСОБЕННОСТИ ПОСТРОЕНИЯ СИСТЕМ ФУНКЦИОНАЛЬНОГО КОНТРОЛЯ КОМБИНАЦИОННЫХ ЛОГИЧЕСКИХ СХЕМ НА ОСНОВЕ ПОИСКА ГРУПП СИММЕТРИЧНО-НЕЗАВИСИМЫХ ВЫХОДОВ
В статье установлено, что при применении классических кодов с суммированием (кодов Бергера) и ряда их модификаций при организации контроля комбинационных схем можно использовать их особенности обнаружения как монотонных, так и части немонотонных ошибок в информационных векторах. Показано, что возможен поиск групп выходов комбинационных схем, на которых могут возникать только симметричные ошибки вследствие одиночных неисправностей элементов внутренней структуры схем. Такие группы выходов обозначены как группы симметрично-независимых выходов. Определены условия принадлежности группы выходов комбинационной схемы к группам симметрично-независимых выходов. Показано, что каждая симметрично-независимая группа выходов может контролироваться при помощи отдельной подсистемы контроля на основе кода с обнаружением любых несимметричных ошибок (в частности, и любых несимметричных ошибок до определенных кратностей). Представлены пути поиска групп симметрично-независимых выходов при организации контроля комбинационных схем.
Комбинационная схема, самопроверяемая структура, монотонная ошибка, симметричная ошибка, асимметричная ошибка, код с обнаружением монотонных и асимметричных ошибок, группы симметрично-независимых выходов
DOI: 10.20295/2412-9186-2020-6-4-532-549
САПОЖНИКОВ Валерий Владимирович — доктор технических наук, профессор кафедры «Автоматика и телемеханика на железных дорогах» Петербургского государственного университета путей сообщения Императора Александра I
e-mail: port.at.pgups1@gmail.com
САПОЖНИКОВ Владимир Владимирович — доктор технических наук, профессор кафедры «Автоматика и телемеханика на железных дорогах» Петербургского государственного университета путей сообщения Императора Александра I
e-mail: sapozhnikov-at@yandex.ru
ЕФАНОВ Дмитрий Викторович — доктор технических наук, доцент, первый заместитель генерального директора — главный инженер ООО «ВЕГА Групп», профессор Высшей школы транспорта Института машиностроения, материалов и транспорта Санкт-Петербургского политехнического университета Петра Великого, профессор кафедры «Автоматика, телемеханика и связь на железнодорожном транспорте» Российского университета транспорта
e-mail: TrES-4b@yandex.ru
© Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V., 2020
