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TEST GENERATION FOR HIERARCHICAL FUNCTIONALSWITCHING STRUCTURES
LYULKINA., LINNIKI.
Belarusian State University, e-mail: [email protected]
Abstract. A problem of test generation for logic CMOS circuits is solved with regard to an extended class of faults. The well-known D-algorithm for test generation for stuck-at faults is extended for transistor stuck-open faults. It is shown that a test for transistor stuck-open faults may be constructed on the base of the test for stuck-at faults. A problem of length minimization of constructed test is discussed.
1 Introduction
As is well known [1-3] that it is impossible to represent physical defects typical for CMOS-circuits by means of stuck-at fault model. Another variant is modification of original circuit. But it requires definite skills in circuit design. Second disadvantage of circuit modification it leads to modification of original circuit to more complicated i.e. it is ineffectively. It restricts using well-known test generation methods, oriented on stuck-at faults in circuits based on functional elements. Specifically, there are stuck-open faults in CMOS- circuit which can not be detected by the only test vector, but can be detected by ordered pair of vectors (u, t), T = (u, t). Input vector t referred to as sensitization vector switches output of fault-free circuit to known state 0 or 1, and output of circuit with fault becomes disconnected from signal source, i.e. be in the high-impedance state. Test vector u is used to set output of the circuit to the opposite state received on vector t. Test sequence Tallows checking a fault, because specified signal value on the outputs of circuit remains a long time, enough to check it.
By now a lot of effective deterministic test generation methods are developed for stuck-open faults in the full complementary CMOS-circuits including only p- and n-cascades [3, 4-6]. At the same time representation of logical CMOS-circuit on the gate level race up dimension of different tasks which necessary to solve during test generation process. The mentioned problem canbe overcome using hierarchical approach for the test generation method. This approach assumes representation of the CMOS-circuit on switch level. At the same time, representation of functional elements at gate level is used to find test vectors for stuck-open faults. In this case joint using of test generation methods is possible for both stuck-open faults in functional circuits represented on gate level and for the stuck-at faults in circuits represented on the level of functional elements (specifically well-known D-algorithm [7,8]). In this work termD-cube offaults used in the D-algorithm is extended on stuck-open faults. Possibility of applying basic operations used in the D-algorithm (fault activation, fault propagation) to generate initialization and sensitization vectors for stuck-open faults is shown. Possibility to detect stuck-open faults by the tests for stuck-at faults on the inputs and outputs of the functional elements represented as full complementary CMOS-circuits is investigated. By the example of circuits designed in the basis AND, OR, NOT, NOR, NAND, possibility to generate test for
the stuck-open faults from the test for the stuck-at faults of the functional elements is shown. In conclusion, the problem of generating test minimization by means of fault simulation and properties of test vectors for the stuck-open faults is discussed.
2 Modification of D-algorithm for the CMOS-circuits
Generating oftest vectors for the logic faults with D-algorithm assumes sequential decision of three questions:
1. Fault activation: force tested node to opposite of fault value;
2. Fault propagation: propagate the effect to one or more primary outputs;
3. Line justification: justify internal signal assignments made to activate and sensitize faults.
Above tasks will be considered during generating test vector for the stuck-open faults in logic CMOS-circuit represented as hierarchical structure.
As is well known, D-cube of fault of the functional element with the only output is the vector (ai,.. .,an,D), where ai - signal value on the element inputxi, ai e {0,1, x}, x - don’t care value. D = D, ifonthe inputvector(a1,...,an) outputofthe element in fault-free state possesses the value 1, and inthe circuit with fault output possesses the value 0. D = D if in the fault-free state output possesses the value 0 and inthe circuit with fault output possesses the value 1. Thus, D-cube of failure represents formal representation ofthe initial test which ensures that failure will appear at the output of the element.
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Fig. 1. Example of circuit
Term D-cube of failure extends on the stuck-open faults. Taking into account that stuck-open faults are detected by the sequence T = (u,t) = ((u1, ...un),(t1,...t^)), pair of vectors (u1,... un),(t1,... tn,D) is understood as D-cube of failure. Methods described in [6] can be applied for creating the D-cubes of failures for the stuck-open faults in the functional elements. Circuit depicted on Fig. 1 will be used as an example. Representation of one of its element (2 input NOR) on the gate level is shown on Fig. 2. Consider stuck-open fault f of transistor t3 (see Fig.2).
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Sequence T = (u, t) = ((0,0), (0,1)) can be used as a test sequence for the fault f [6]. Output of fault free-element possesses the value 0 on test vector t = 0, and possesses the value 1 in the faulty element. D-cube offailure (00), (01D) corresponds to current test sequence.
In order to find test vector for some fault by means of D-algorithm two operations must be done after choosing D-cube of failure:
1. To find fault propagation conditions (this operation also called fault sensitization);
2. To provide found conditions, i.e. perform linejustification.
In the case of stuck-open faults the procedure of calculation test sequence S = (U, T) for the initial circuit by D-cube of failure (u1;...un),(t1,...tn,D) is reduced to the sequential decision of following tasks by using D-algorithm formal operations:
1. Initialization vector U of initial circuit is calculated by vector (t1,...tn, D) (this can be done by means of line j ustification of D-algorithm);
2. Test vector T of the initial circuit is created by vector
(tp...tn, D) (values fromvector (t1,___tn, D) are assumed
to circuit nodes at the beginning and then formal operations of D-algorithm for the conditions of fault propagation and line justification are applied)
Stuck-open fault f in the element number 5 on the Fig. 1 is considered as an example. Numbers of elements specified above elements; number ofcircuit node definedby the number of circuit primary input orby the output offunctional elementwhich define signal value at the current node. Process of calculation test sequence for the entire circuit on the base of D-algorithm is shown at the Table. Thus test sequence S = (U,T) = ((01 —),(0000)) was found. Don’t care signal values on the primary inputs x3 and X4 are denoted here by dash.
3 Stuck-at test application
It will be shown that test vectors for the stuck-at faults on the inputs and outputs of the functional elements can be used as the initialization and sensitization vectors for the stuck-open
faults. In the future it will allow not to calculate test sequences for the stuck-open faults, but to form them from the test vectors for the stuck-at faults.
Consider 2 input NOR element (Fig. 2). Stuck-at faults f1 = X1|1, f2 = X1|0,f3 = X2|0 will be eliminated. Here Xi | a denotes fault “constant a ” on the input xi (a e {0,1}). Tf1 = (00), Tf2 = (10),Tf3 = (01) are the test vectors for the mentioned fault, respectively. Tf1 is the initialization vector for all stuck-open faults in the n-cascade and sensitization vector for the stuck-open faults in the p-cascade. Similarly, any fromTf2 orTf3 is the initialization vector for the stuck-open faults in the p-cascade. In addition, Tf2 is the sensitization vector for the stuck-open fault of transistor t4 and Tf3 is the sensitization vector for the stuck-open fault of transistor t3 . Thus, sequence T = (Tf1, Tf2, Tf1, Tf3) can be chosen as the test sequence for all stuck-open faults in the considered element. So, ifvectors Tf1,Tf2,Tf3 are generated for the circuit in the large, i.e. by means of signal values on the primary inputs of circuit (what performed due test generation on the base of D-algorithm), then this vectors save their properties and for the stuck-open faults, i.e. sensitize paths from output of element to the output of the circuit. Last assertion implies from the procedure of test vector generation in the D-algorithm.
Analogous test sequences can be created for other CMOS-circuits: NAND, And, OR, NOT and others. It allows to reduce test generation task for the stuck-open faults for the circuits at whole to generating test from the set oftest vectors for the stuck-at faults of functional elements, which can be created using D-algorithm.
4. Test minimization
From the aforesaid it follows, that test generation procedure for the hierarchical CMOS-circuit can be reduced to the sequential decision of the following tasks:
1. Creating of vector T1 for the stuck-at faults on the level of the functional elements;
2. Generating vector T2 for the stuck-open fault on the base of test T1 ;
3. Generating test, which verify stuck-at and stuck-open faults: T3 = T2 u T{, where T{ - set of input vectors from the T1 , which not included in the test T2 ;
4. All faults simulating on the test T3 and number of detected faults determination. Here only the faults, which are not detected by the previous vectors are simulated on the next vector.
It should be noted, that vectors, which belongs to the part of test T{, which didn’t detect the faults (it is determined after simulation) can be removed from the test T3. Besides, test vector t1 can be removed, as it isn’t initialization or sensitization vector for the not yet detected stuck-open faults, if on the section T2 of testT3 there are existed adjoined pair of vectors t1 andt2 each of them doesn’t detect faults. Procedure of removing mentioned vectors continue until such pairs of vectors exist. Application of simulation of faults on the generated test and removing redundant vectors allows to minimize test length.
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Process of test sequence calculation
K° Circuit node status List of nodes for Line Justification Comments
1 2 3 4 5 6 7 8 9 10 11 12
1 0 0 6 Generating initialization vector. Nodes initial initialization
2 0 1 0 0 Supplying value 0 at node 6. Initialization vector generated u= (01--).
3 0 1 D 6 Generating sensitization vector. Select second vector from D-cube
4 0 1 0 D 0 0 D 11,10,8,6 Transition fault through element 8. Conditions for transmission faults to the primary outputs provided.. Change over providing conditions
5 0 1 1 0 D 0 0 10,8,7,6 Providing value 0 in node 11
6 0 1 1 0 D 0 0 D 8,7,6 Providing value 0 in node 10. Condition hold
7 0 1 1 1 0 D 0 0 D 7,6,5 Providing value 0 in node 8
8 0 0 0 1 1 1 0 D 0 0 D 6,5 Providing value 1 in node 7
9 0 0 0 0 1 1 1 0 D 0 0 D 5 Providing value 1 in node 6
10 0 0 0 0 1 1 1 0 D 0 0 D 0 Providing value 1 in node 5. Condition hold. Sensitization test generated: t=(0000)
5. Conclusion
Proposed modification of D-algorithm allows to generate tests for the stuck-open faults in the hierarchical CMOS-circuits, represented on the functional-switching level. Test for the extended class of faults for the CMOS-circuits can be generated on the base of the test for the stuck-at faults of functional elements of circuit is shown. Procedure for creating minimized test which is oriented on the stuck-open faults is provided. Application of proposed approach allows to generate high quality tests with relatively small labor intensiveness, using well-known approaches to build tests for stuck-open faults.
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