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УДК 62-529
doi:10.18720/SPBPU/2/id21 -365
Амосов Владимир Владимирович \
доцент, канд. техн. наук, доцент;
Петров Александр Владимирович1, старший преподаватель;
Тышкевич Антон Игоревич3,
доцент, канд. техн. наук, доцент
РЕШЕНИЕ ЗАДАЧИ ПРОГРАММНО-АППАРАТНОЙ РЕАЛИЗАЦИИ АЛГОРИТМОВ УПРАВЛЕНИЯ РОБОТОМ
12 3
' ' Россия, Санкт-Петербург, Санкт-Петербургский политехнический
университет Петра Великого, 1 amosov_vv@spbstu.ru
Аннотация. В данной статье предлагается решение проблемы программной и аппаратной реализации алгоритмов управления роботом. В качестве примера рассматриваются различные методы аппаратной и программной реализации одних и тех же алгоритмов, алгоритмами которых являются контроллер лифта и сортировка пузырьков. Предложены языки их описания: программная реализация выполнена на языке высокого уровня SystemC и на сборке 32-разрядного цифрового процессора (DP32), аппаратная реализация выполнена на языках описания цифрового оборудования VHDL и Verilog HDL. Каждая реализация подразумевает написание тестового сценария (TestBench). Тестирование для SystemC, а также версий алгоритмов VHDL и Verilog HDL проводилось с использованием моделирования, в то время как для алгоритма в процессорной сборке DP32 использовалось совместное моделирование. В программной реализации алгоритмов тестирования использовалась среда Aldec Active CAD с VHDL-моделями процессора, памяти и генератора тактовых импульсов, а также среда Microsoft Visual Studio со средством просмотра временных диаграмм GTKWave. В аппаратной реализации для тестирования и оценки синтезируемости использовалась CAD-система Quartus II, а также переводчик "sc2v" с языка System C на язык Verilog HDL. Фрагменты результатов моделирования, совместного моделирования и тестирования на синтезируемость представлены в виде отчета о размещении алгоритма в
программируемой логической интегральной схеме (ПЛИС), схемы алгоритма в ПЛИС на уровне передачи регистров (RTL) и технологической схемы из логических ячеек этой ПЛИС.
Ключевые слова: система на кристалле, программная реализация, аппаратная реализация, SystemC, Verilog HDL, VHDL.
Vladimir V. Amosov \
Associate Professor, Candidate of Technical Sciences;
Alexander V. Petrov2, Senior Lecturer;
Anton I. Tyshkevich 3, Associate Professor, Candidate of Technical Sciences
SOLVING THE PROBLEM OF SOFTWARE AND HARDWARE IMPLEMENTATION OF A ROBOT CONTROL ALGORITHMS
12 3
' ' Peter the Great St.Petersburg Polytechnic University, St. Petersburg, Russia, 1 amosov_vv@spbstu.ru
Abstract. In the following article a solution to the problem of software and hardware implementations of robot control algorithms is proposed. Various methods of hardware and software implementations of the same algorithms are reviewed by way of example, the algorithms being the elevator controller and the bubble sorting. The languages of their description are proposed: the software implementation was carried out in the high-level SystemC language and in assembly of the 32-bit Digital Processor (DP32), the hardware implementation was carried out in the VHDL and Verilog HDL digital equipment description languages. Each implementation implies writing a test script (TestBench). Testing for the SystemC as well the VHDL and Verilog HDL algorithm versions was carried out using simulation, while for the algorithm in DP32 processor assembly a co-simulation was used. In the software implementation of the test algorithms, we used the Aldec Active CAD environment with VHDL models of the processor, memory and clock pulse generator, and the Microsoft Visual Studio environment with the GTKWave timing diagram viewer. In the hardware implementation, for tests and synthesizability estimation the Quartus II CAD system was used, as well as the "sc2v" translator from the System C language to the Verilog HDL language. Fragments of the results of simulation, co-simulation and testing for synthesizability are presented in the form of a report on the placement of the algorithm in a programmable logic integrated circuit (FPGA), an algorithm diagram in an FPGA at the register transfer level (RTL) and a technological scheme from logical cells of this FPGA.
Keywords: System-On-Chip, software implementation, hardware implementation, SystemC, Verilog HDL, VHDL.
Introduction
The most important part of robot of any kind is its programmable control unit, which operates according to the algorithms that correspond to robot's target application [2].
With the introduction of System-On-Chip technology and very large scale CPLD integrated circuits which contain both central processing unit with
on-chip memory [1, 9] and a configurable part the system programmers were faced with a problem of hardware and software implementation of a robot control algorithms.
In the design of the System-On-Chip based robot control application a certain problem arises concerning deciding which algorithms are to be implemented in hardware [4] and which ones in software and how those algorithms are to be put together for best performance [5].
Software implementation of algorithms here is understood as their coding in programming languages from assembly level to high level ones, placement the image in memory and execution of instructions by the processor [6].
Hardware implementation is understood as coding of algorithms in hardware design languages such as VHDL, Verilog HDL and others, verifying the code for being synthesizable, assigning input and output pins and compiling and synthesizing the design into the programmable integrated circuit [1]. One more way of hardware implementation is coding of algorithm as a program in high level language with linking against corresponding libraries [8, 9], for example, in SystemC, and this is a software implementation in itself while this program later being translated into one of hardware design languages.
This article deals with consideration of both software (in SystemC) and hardware (in Verilog HDL) implementation of elevator controller algorithm and an example of hardware (in VHDL) and software (in assembly language) implementation of bubble sort algorithm.
Particular stress is put on verifying both software and hardware implementation [7, 10] in the course of each design approach. Each implementation implies providing a test bench.
The article also considers software tools [3] and their usage in software and hardware implementation of the algorithms.
Software implementation has been carried out with the use of Aldec Active CAD development environment with VHDL models of the processor, memory unit and clock generator and also with Microsoft Visual Studio and GTKWave waveform viewer.
For verifying the design for being synthesizable and for its testing CAD software Quartus II and "sc2v" convertor from SystemC into Verilog HDL have been used.
1. Examples of software (in System C) and hardware (in Verilog HDL) implementations of an elevator controller
1.1. Specification of algorithm operation
There is an eight-storey building. The controller is being informed of whether any button inside an elevator cabin or on some of the floors has been pressed. We assume that no more than a single button from inside and no more than a single button from outside could have been pressed. The controller gen-
erates up and down signals for the driving motor, the door opening signal and a floor number to be shown on the display device. It is assumed that the elevator moves a single floor distance per cycle and is located at the ground floor after reset, that is floor number zero (0). In case there are signals from both inside and outside buttons the inside one's signal should be processed first. The request validity signals (request_internal_valid and re-quest_external_valid) are reset automatically by the test module when the door opens on the requested floor. Inputs.
sc uint<3> request internal, request external; bool request internal valid, request external valid;
Outputs.
bool up, down; bool open; sc_uint<3> floor;
Logic.
Sequential and combinational logic
1.2. Software implementation of elevator controller algorithm.
Software implementation provides the description of elevator controller behavior and the description of the test that corresponds to the algorithm of its operation.
Parts of code in SystemC language.
if (request internal.read()) {
if (request internal.read() < floor.read())
floor left = floor.read() - req internal.read(); down = 1;
else if (request internal.read() > floor.read())
floor left = req internal.read() - floor.read(); up = 1;
else
open = !open;
}
Testing by the simulation.
The following operation of elevator controller has been tested:
• The clocking signal (CLK) starts and inside and outside request buttons have not been pressed (req_in=req_ex=0).
• On the edge of CLK signal the buttons requesting upside motion (up=1) both from inside to the floor number 6 and from outside to the floor number 1 are pressed simultaneously (req_in=6, req_ex=1) along with the val-
id condition being checked with the signals req_in_val=req_ex_val=1; the elevator moves upwards (up=1) until it reaches the floor number 6 where the door has been opened (open=1); signals req_in, req_in_val, up, open are reset to zero on the next edge of CLK signal;
• Outside button (signal req_ex_val=1) remains being pressed and downward motion control signal (down=1) is generated, elevator moves to the floor number 1, the door opens, and the signals are reset.
• Outside button (signal req_ex_val=1) remains being pressed and downward motion control signal is generated, elevator moves to floor number 1, door opens, and the signal are reset.
• Next outside request for floor number 3 comes, the elevator moves, the door opens.
• Finally, button for the floor number 2 is pressed from inside, the elevator moves downward to the floor number 2 and the door opens.
Below (see Fig. 1) the waveforms obtained with the Gtk Wave viewer software are presented. They fit to the specification of the elevator controller algorithm.
Time
reset
1 100 ns
l ruuiji n n iin n_rm_n n nJUUlJUl n n rULTULn n n
8 p p
1 1
la U
9 1 2 3 4 5 6 5 4 3 2 ;1
f
1 1 i
n n
req_in[2:0] req_in_val req_ex[2:Q) reqex_va\ f\oor[2:0) down up open
Fig. 1. Parts of the waveform (SystemC)
1.3. Hardware implementation of elevator controller algorithm Parts of the code in Verilog HDL obtained by translation of the program in System C language with sc2V tool.
if (req external) begin
if (req external <floor) begin
new floor left = (floor - req external); new down = (1); end
else if (req external > floor) begin
new floor left = (req external - floor); new up = (1); end
Testing by simulation.
Testing has been carried out with CAD Quartus II [11]. The test is identical (see Fig. 2) with the test for the program in SystemC.
Narine V; 31 280.0 ns 320.0 ns 1 1 360.0 ns 400.0 ns 440. 1 1 1
elk reset 0 requestjnternal requestjnternal... 0 request_external request_external... □ floor down up nnnnnnnon LRnmnmn LTLTI LTLTI LTLTI LTLTI LTI_n LTLTI LTLTI \J\R
0 X X
I :
o X - X
o Iflffl Î4Wf G ) i i
1
1
open n n
Fig. 2. Parts of waveform (Verilog)
Verifying code for being synthesizable.
The ability of the code of the algorithm to be programmed (configured) into Altera PLD is verified. In case of success the CAD software generates a report (see Fig. 5) on fitting the design into PLD, view of the design (see Fig. 3) at a register transfer level (RTL) and a technology map (see Fig. 4) view of logic cells of that PLD.
Fig. 3. Part of RTL view of the design
Fig. 4. Part of technology map of the design
Revision Name Ut
Top-level Entity Name tft
Family Strati*
Met timing requirements Yes
Total logic elements 3m570(<l %)
Total pins 1G / 33G( 4 ^ )
Total virtual pins 0
Total memory bits 0 / 920,446 (0 aS
DSP block 3-bit element? 0/43103)
Total PLLs 0/6(CU|
Total DLLs 0/2(0£)
Device EP1S1QF4S4C5
Timing Models Final
Fig. 5. Compilation report
2. Example of software (in assembly language) and of hardware (in VHDL) implementation of bubble sort algorithm
2.1. The specification of algorithm operation
At input there is a sequence of n numbers. The algorithm in essence is a repetition of traverses through an array being sorted. In each iteration array adjacent elements are sequentially compared in pairs and in case of wrong order their values are swapped.
Traversing an array is performed n-1 times which mean that an array has been sorted out. During each iteration of inner loop, the "next biggest element" takes its place at an end of array near the "previous biggest" element while the smallest moves by one position to the beginning.
2.2. Hardware implementation in VHDL
process(clk,reset)
variable temp:std logic vector(7 downto 0);
variable memory:arr;
begin
if (reset = '1') then memory := data_in; iterations <= 0; counter <= 0; elsif (counter < 7 - iterations) then if (clk'event and clk = '1') then
if (memory(counter+1) < memory(counter)) then temp := memory(counter); memory(counter) := memory(counter+1); memory(counter+1) := temp; end if;
counter <= counter + 1; end if;
else
iterations <= iterations + 1; counter <= 0; end if;
tempMemory <= memory;end process;
Testing by simulation.
The testing (Fig. 6) has been carried out with Quartus II CAD software.
Name 1 . SO . 1 100 1 150 1 200 t 250 i 300 t 350 i 400
+ datajn {(6,5,3,1,8,7,2,4)
elk I I
reset
+ data_out {(6,5,3,1.8,7,2,4) X(5,6,3,1,8,7,2,4) X(5,3,6,1,8,7,2,4) X(5,3,1,6,8,7.2,4)
Fig. 6. Simulation Verifying the code for being synthesizable (Fig. 7, Fig. 8)
Fig. 7. Part of technology map
Fig. 8. Part of RTL view
2.3. Part of software implementation in assembly language of DP32 processor
10 =>X"3105_
11 =>X"3104_
12 =>X"1002_
13 =>X"1106_
14 =>X"500A_
15 =>X"1106_
16 =>X"500E_
17 =>X"5000
0200", 0300", 0201", 021E", 00F6", 0709", 00F1", 0020",
M[r2] M[r3]
<= r5; <= r4
-- r2 <= r2 + 1
r6 <= r2 -if r6 < 0? r6 <= r7 -if r6 < 0? exit
29 check last
in counter 9 cur - next out counter
Testing by co-simulation.
Testing has been carried out by simulating execution (Fig. 9) of the program (co-simulation) using behavioral and structured VHDL model of DP32 processor and VHDL models of memory unit and clock generator.
Name
Type
Value
+ mem/line_l4/mem(i9) b
± mem/line_14/mem(20) b
+ mem/line_14/mem(21) b
* mem/line_14/menn(22) b
± mem/line_14/mem(23) b
± mem/line_14/mem(24) b
+ mem/line_14/mem(25) b
+ mem/line_14/mem(26) b
i proc/line_20/curren... b
+ p roc/line_20/PC b
± proc/line_20/reg(5) b + p roc/I me_20/reg(4) b + pruc/line_20j'reg(3) b
+ proc/iine_20/req(2) b
± proc/line_20/reg(l) b
± proc/line_20/reg(0)
t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t_32 t 32
00000001
00000002
00000003
00000004
00000005
00000006 00000007 00000003 50Û00QFF 00000012 00000002 00000001 FFFFFFFF 00000014 00000012 00000013
Fig. 9. Testing by co-simulation
Conclusion
The article raises a question of implementation of algorithms. It shows that in addition to software-oriented approach any algorithm can be implemented in hardware. Examples are given for consideration of different ways of implementing the same algorithms both in hardware and in software. Different languages are suggested for the purpose of algorithm description and different means of testing the design are proposed using different tools for the implementation. Hardware implementation has been carried out in VHDL and Veri-log HDL. Software implementation has been carried out in SystemC and in
assembly language of DP32 processor. Testing has been carried out by simulation and co-simulation.
Acknowledgment
The reported study was funded as the part of the State Task for Basic Research 075-01018-21-04.
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