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Научни трудове на Съюза на учените в България - Пловдив. Серия В. Техника и технологии, т. XIV, ISSN 1311-9419 (Print), ISSN 2534-9384 (On- line), 2017. Scientific Works of the Union of Scientists in Bulgaria-Plovdiv, series C. Technics and Technologies, Vol. XIV., ISSN 1311-9419 (Print), ISSN 2534-9384 (On- line), 2017.
ИЗСЛЕДВАНЕ НА CMOS БУФЕРНИ СТЪПАЛА С ТРЕТО ВИСОКОИМПЕДАНСНО СЪСТОЯИИЕСЪССИМУЛАТОР
LTSPICE Валентин М. Моллов Технически Университет - София, катедра „Компютърни системи"
INVESTIGATION OFCMOSTHREE-STATE BUFFER STAGES WITH LTOPFCE SEMULATER Valentin E.Mollsv Technical University of Sofia, Bulgaria, Department of Computer Systems
Abstract: Shis paper presents a simple and efficient approach for simulation of OMAE three-state stages using the free and easy to apply TOspice simulator proposed by the of Linear Technology Corporation. Ghree main buffer stages are shortly discussed and further simulated using a DO sweep analysis. We apply general purpose transistor models and simple transistor layout scaling, where necessary. Here, we demonstrate simulation technique for both checking the proper logical function and the high impedance (three-state) condition at the output. We also show both the output voltage and the load current waveforms to detect the high impedance state.
Keywords: Simulation, buffers, OMAE, DO sweep analysis, high impedance
1. Introduction. Simulation tool.
It is a common and frequent task to check the logic functionality and the signal waveform at the output of a transistor circuit. This task becomes some more complicated when the logic circuit should possess a three-state (high impedance) feature which is obligatory for any buffer stage, for example. The high impedance means that all transistors at the output stage of the circuit should be simultaneously switched off in contrast to its normal functional condition. The switching from logical to high impedance (often called z-state) must be controlled by additional signal, which suppose some extra circuitry in excess to conventional logical circuit.
CMOS circuits, as it is well known, are resistor-less, so the extra three-state controlling circuitry usually does not present a layout problem itself. Normally, this circuitry is quite simple, consisting of four transistors presenting an inverter and two separate transistors or a simple logic circuit, embedded into the overall logic stage. There are numerous application of CMOS three state circuits in engineering practice, incl. for VLSI applications (Z.V.Bundalo, 1995), for bioimpedance measurements (H.Hong, 2010), or to perform interconnection for signal conversion from ternary to binary CMOS digital systems (D.Bundalo, 2012).
We apply LTSpiceIV environment, provided by (Linear Technology Corp., 2016), as software tool to prepare simulations for all three-state circuits discussed here. This software is completely cost-free and ready to download and use along with variety of examples to support the prospective users. Although the software is tailored mostly to be used by engineers in high voltage electronics, the products of the company and the correspondent model libraries permit application in classical digital logic design and analysis. Here, we use general purpose four-terminal transistor models for
our NMOS and PMOS devices. Application of the four-terminal schematics for MOS transistors allows their serial connection to be done properly in respect to the substrate terminals.
Below, the simulation waveforms of the output voltage and the load current for the circuits under investigation are shown and discussed shortly.
2. Basic three-state CMOS buffer stages
2.1. CMOS three-state inverter with serial transistors
The schematic of CMOS inverter with high impedance feature at the output with serially connected transistors is shown in Fig. 1. The three-state capability is achieve with adding two extra transistors MN_S and MP_S, serially connected to the main inverter which state is controlled with one additional inverter composed by MN_inv and MP_inv transistors. While the V_TS is low, the circuits accomplish its normal logical function. With V_TS high, the output remains in high impedance, as the extra serial transistors are simultaneously off.
Fig.2 demonstrates the normal operation mode of the circuit, i.e. its inverter transfer function. It is done with V_TS set to low level, so, the serial linked transistors MN_S,MP_S are switched on and does not affect the logical operation of the stage. The threshold voltages for all transistors are equal. Below, Fig.3 presents the waveform of the output voltage over the load capacitor CL (the load in such circuits is almost completely capacitive) for V_TS voltage varying from low (enable logical operation) to high (disable logical function, i.e. high impedance) while the logical input
voltage Vin is either low or high. Also, the load current waveform and magnitude is shown to confirm the three-state condition at the output. LTSpice allows quite simple and convenient way to plot the waveforms using voltage and/or current probes. Here, V[n002] plot represents the V_TS signal waveform, V[n004] is the output voltage which drops upon disabling the V_TS below the high state (app. at V_TS=3V), and I[Cl] shows the current on the load capacitance. Before going to high impedance, the output voltage is high, i.e. the circuit operates as inverter.
l(CI]
V|n002] V(n004]
ov-ov-ov-ov-ov-0.
IV 1 1 1 1 1 1 1 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V Fig.3 Load current and output voltage waveforms during normal operation and highimpedance state .0
Fig. 1 CMOS three-state inverter with serially connectedtransistors
Fig.2 Transfer function of the circuit from Fig. 1 in enabled mode, VT0=0.5V
2.2. Transmission gate based three-state CMOS inverter
Three-state condition at the output is also possible to be achieved by means of a simple circuitry, applied at the output of the basic stage, thus not affecting its general structure. One way to do this is to connect single transmission gate (pass-transistor) logic between the basic CMOS inverter and the load. The number of extra transistors is again four which is the same as in previous case. MN_T and MP_T, along with the MN_inv, MP_inv form the transmission-gate circuit and control the link between the inverter and load -Fig.4. We check the functionality trough DC sweep analysis (linear or with list of values) of the voltage V_TS applied at the three-state controlling input. The normal operation mode with V_TS at low level gives the same DC transfer function as for single inverter, equal to this from Fig.2. If the normal logic function at the output must be obtained with V_TS set high, we should simply reconnect the gate links of the pass transistors in respect to the inverter input/output. We check again the three-state condition at the output when the V_TS is high, so both pass transistors are switched off.
Fig.5 presents the correspondent output waveforms and the load current in respect to change of V_TS high impedance controlling voltage source. We observe a rapid entering into high impedance state at the circuit output when V_TS goes high, then the correspondent output voltage
Fig.5Output voltage V[n004] and load current I[Cl] waveforms vs V_TS three state controlling signal for transmission gate based inverter circuit
drops below logic one level (indication of non-operating condition, i.e. third state) as well as the load current slowly decreases due to discharge of the CL load capacitance. To achieve better speed performance, and also to reduce the overall transmission gate impedance, it is recommended to scale up the layout of MN_T and MP_T transistors at least two or three times.
2.3. CMOS three-state circuit with push-pull output stage
Finally, we simulate the well known circuit, shown in Fig.6 which,in fact, presents the essential part of the output stage of 74HC/HCT244 3-state octal buffers/line drivers produced firstly by Texas Instruments. When enabled (V_TS low), the circuit operates as follower in contrast to previously discussed two stages, which are inverters. Also, as an advantage, this circuit has a push-pull output stage to make easier the scaling process independently in respect to the logical part of the circuit (two invertersINV_1 ,INV_2 and 2-port NAND and NOR elements). Properly scaled
pull-up MN_U and pull-down MP_D transistors guarantee equal charging and discharging times of the load capacitance. When V_TS is high, the stage shows high impedance feature at the output, disabling the link to the load. Fig.7 demonstrates the high impedance feature at the circuit output obtained with LTspice simulation when V_TS is going from low (enabled) to high (disabled)
level. During the 3-state, the output level is intermediate, while the load current (lowest plot in Fig.7) drops to zero.
3. Final remarks. Application notes
As could be observed by the above simulation results, it is recommended to check the high impedance feature of all CMOS circuits by applying firstly a DC sweep analysis in normal operation mode (enabled logical operation) getting the expected transfer function. Later, we can gradually disable the output of the circuit trough changing the three-state controlling
Fig.6 CMOS three-state circuit with push-pull output stage
input, so the output voltage become neither high nor low, but some intermediate value. It is the simplest possible and reliable way for fast and secure demonstration of logic and three-state functionality of the circuit. It is also advisable to measure the load current at the output to guarantee that during transition from one logical state to another and vice versa, there is no current charging/dischargingthe load capacitance.
References
(Z.V.Bundalo, 1995),G.M.Ninkovic, Design of three-state logic for CMOS VLSI digital systems, Proceedings of the 20th International Conference on Microelectronics, 1995, v.2, pp.513-516 (H.Hong, 2010),A.Demosthenous, et al, A high output impedance CMOS current driver for bioimpedance measurements, Proceedings of the IEEE Biomedical Circuits and Systems Conference (BioCAS), 2010, pp.230-233.
(D.Bundalo, 2012), Z.Bundalo, F.Softic et al, Logic circuits with high-impedance output state for interconnection of ternary and binary CMOS digital circuits and systems, Proceedings of the 35th International Convention, MIPRO, 2012, pp.97-102. (Linear Technology Corp., 2016): http://www.linear.com - official web site.
За автора
Доц. д-р инж. Валентин С. Моллов, Технически Университет-София, катедра "Компютърни системи", ФКСУ, бул.Кл.Охридски 8, email: mollov@tu-sofia.bg
