Combined approach for evaluation and calculation of cmos logic circuits timing capabilities Текст научной статьи по специальности «Электротехника, электронная техника, информационные технологии»

Научни трудове на Съюза на учените в България-Пловдив, серия Б. Естествени и хуманитарни науки, т. XVIII, ISSN 1311-9192 (Print), ISSN 2534-9376 (On-line), 2018. Scientific researches of the Union of Scientists in Bulgaria-Plovdiv, series B. Natural Sciences and the Humanities, Vol. XVIII, ISSN 1311-9192 (Print), ISSN 2534-9376 (On-line), 2018.

COMBINED APPROACH FOR EVALUATION AND CALCULATION OF CMOS LOGIC CIRCUITS TIMING CAPABILITIES Valentin S. Mollov TechcicalUniversity of Tofia, Bulgaria

Abstract: Here, a comprehensive and easy to apply engineering approach is presented which allows the timing capabilities of CMOS gates to be evaluated by measurements and simple calculations. The focus is on the values of the propagation delays of a single inverter stage and the origin of its load and parasitic capacitances. Based on the measured values of propagation delays for a single inverter stage, we can calculate the parasitic capacitances of any fabrication process. Keywords: CMOS, measurement, timing parameters, parasitic capacitances

I. Introduction

The advance of microelectronic fabrication technology during the last two decades, together with application of new materials and design techniques, has led to extreme improvement of the overall timing performance of the MOS/CMOS circuits. Formerly being known as arbitrary slow and inappropriate for fast processing applications, now these circuits show much better speed capabilities into monolithic digital blocks of complex systems. The channel length of transistors dropped dramatically from above 2^m in the early 1980s down to 12-10nm nowadays' (2017) technologies, applied mostly in programmable logic devices [1] and DRAMs.

Although the rapid improvement in CMOS technologies, the shrunk of the channel length, and overall ultra-VLSI miniaturization, the general problem of substantial in-chip load capacitances still exists. This problem become greater, especially in traditional 2-D chip fabrication process, as the length of interconnections becomes higher and introduces greater to the load, and therefore - to worsened timing performance. So, it is sometimes useful to get fast and simple measurement-based approach to calculate and/or get impression on timing capabilities of the MOS/CMOS technology of different manufacturers and various technologies. Here, we discuss the origin of the in-chip load capacitance CL at the output of a single inverter - Fig. 1, and make measurements of timing parameters - the propagation delays as a merit of its speed performance.

II. Timing parameters of digital circuits. CMOS parasitic capacitances 2.1. Propagation delays

Usually, the timing capability of any circuit technology is evaluated by the delay at the output of a single inverter in respect to input square shaped input signal. There are two types of delay - rising and falling time of the output signal from/to 10% to 90% of the amplitude and as called propagation delays which are measured at 50%.UM level - Fig.2. The values of propagation

Vdd

Tp

Uin

Uout

Tn

Cl

Fig. 1 CMOS inverter stage with load capacitance

delays: high-to-low tPHL and low-to-high tPLH are more representative as a merit of the overall timing capabilities of the circuit.

The average delay (or also called average propagation delay) is defined as:

t _ Win + tpHL

Lfl\/ _

(1)

2.2. CMOS parasitic capacitances

The load capacitance at the output of CMOS stages [3,4] has different origin, as the microelectronic structure and layout of the chip highly introduces of its value. We can say that components of the load capacitance are:

- gate capacitances at the output which consists of all input Cg=Cg/ (i=1... n) of connected n stages;

- parasitic drain-bulk capacitance CPAR;

- wiring (poly-Si interconnection lines) capacitance Cint [3].

So, the expression for CL could be written as:

CL - CGi + CPAR

+ C|N

(2)

The overall gate capacitance is layout dominant and is presented as:

Utn

uout2

0.5Um

tpHL

tpLH

Fig.2. Propagation delays definition and measurement

Cg -(W.L)t -Cox + (W.L)T Cox +......+ (W.L)^.C0X + (W.L)^.Cc

(3)

Where, COX is the thin layer capacitance below the gate, W and L are the width and length of the channel of each connected i-th load stage for both Tn and TP transistor. Note that the P-type transistors introduce 2.5 times higher to the overall area, as ^N«2.5^P.

Parasitic drain-bulk CPAR capacitances are depletion "bottom" side drain diffusion and the correspondent "side-wall" depletion regions with typical values of 0.2 fF/^m and 0.5 fF/^m [3]. Wiring capacitance or as called interconnection capacitance CTNT is proportional to the length (total area WTNT.LTNT) of interconnects and the specific capacitance of thick oxide layer CTHTCK below:

CINT - CTHICK(WNT.LINT

(4)

t

t

)

III. Experimental integrated circuit. DC transfer function and average delay measurement 3.1. HEF4007 construction and technology issues

We use integrated circuit (IC) HEF4007UB [1] from NXP Semiconductors (dual complementary pairs plus inverter) with three n-channel and three p-channel enhancement mode MOS transistors (dual-in-line ceramic package) to illustrate the timing capabilities of an on chip implemented single inverter stage. The same circuit is also available as CD4007 by Fairchild, Texas Instruments, National Semiconductor, etc. Despite the arbitrary old technology of its fabrication, the 4007 IC is the only one available low-scale integration (LSI) monolithic die to be used for our experimental setup and following measurements. We will show that our approach is applicable towards every type of technology as we can make some calculations upon measurements, not by technology available data, e.g. parasitic capacitances per area, the length of interconnections, etc. Designated propagation delays, given by the manufacturer for 5V supply voltage are as follows: tPHL from 40ns to 80ns and tPLH from 40ns to 75ns. Simplified formulae for fast calculations of the above parameters is also available for both parameters as: 9 ns + (0,23 ns/pF) CL.

The DC transfer function and average delay of a single inverter from HEF4007 are given in Fig.3 and Fig.4, respectively.

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Paul Euttoft

let JL B '•'■*)'$ *

HJffiift

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Afcj.1 ^vbM

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Fig.3 DC transfer function of a single CMOS inverter from HEF4007

Ofl 1.C

HiSiw

Fig.4 Average delay tAV measure for single inverter from HEF4007 - app. 24 ns

3.2. CMOS process parasitic and load capacitances. Propagation delays calculations.

High-to-low propagation delay could be derived when a high level input voltage is applied instantly to inverter, so at the output we have transition to low with CL discharge. TN switches from cutoff to saturation, while TP switches from linear mode to cutoff. So, the current id is:

i -lfox_W (ui V )

'd -—2— OUT -V™''

Here U1=Ugs for TN. Propagation delay, being the time UOUT to reach 50% of UM is therefore:

dU,

dQL _ - ld

out _ "six __d _

dt

dC, C .

C + C

^ ^ PAR

(5)

(6)

where id is the drain current of TN pull-down transistor under saturation, CG and CPAR are the overall gate and parasitic load capacitances. Finally, the high-to-low expression could be given as:

CL (U 1out /2)

!/2(^.Cox)(W /L)„(U1out - vtn)2

(7)

The propagation low-to-high is derived by analogy, using the same model, but for the TP pull-up driving transistor. So, the value of tPLH could be given as:

CL (U 1out /2)

1/2(^P .COX )(W / L)P (U1out - VTP )2

(8)

3.3 Measurements of propagation delays

Fig.5 and Fig.6 presents the measured values of propagation delay tPHL and tPLH, respectively. The slightly difference in their values could be explained with some asymmetry of the layout of TP which area is not exactly resized to 2.5 times in respect to that of TN.

Having measured the values for both propagation delays and the presumed values of W/L for TN and TP transistors, as well as the mobility values for [iN and |iP for the silicon, we are able to obtain the value for the overall load capacitance CL. We suppose that the high-level voltage U1 is equal to the voltage supply vDD. The values of the threshold voltages could be measured from the DC transfer function (Fig. 1) and are close to 1.8V for HEF4007.

i

d

Finally, we can gain the value for the parasitic capacitance for the given technology by measurement propagation delays with no load at the output of the inverter stage. It is very simple and straight forward approach to get impression about the level of any manufacturing technology.

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Fig.5 Propagation delay high-to-low tPHL measured value (26 ns) Fig.6 Propagation delay low-to-high tPLH measured value (25 ns)

IV. Concluding remarks

This material presents a very simple and easy applicable approach for calculation some CMOS technology parameters, the parasitic capacitance in particular, based on measurement of the values of propagation delays of a single inverter. It could be useful for the purposes of comparative analysis between two or several technologies having access just to one inverter stage accessible through the pins of input-output buffer stages of large-scale integration chips or from some in-chip located test structure.

V. References

[1] Xilinx Corporation - http://xiinx.com

[2] HEF4007UB datasheets: http://pdf1.alldatasheet.com/datasheet-pdf/ view/17668/PHILIPS/ HEF4007UBP.html

[3] http://web.mit.edu/course/6/6.012/SPR98/www/lectures/S98_Lecture 13 .pdf

[4] http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf