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EVOLUTIONARY APPROACH TO THE TEST PATTERN GENERATION FOR THE SEQUENTIAL CIRCUITS
SKOBTSOV Y.A.\ SKOBTSOVV.Y.* 2,
IVANOVD.E?___________________________________________
'Department of Automated Control Systems, DNTU, Artema Str. 58, 83000 Donetsk, Ukraine,
E-mail: [email protected]
2Institute of Applied Mathematics and Mechanics of NAS of Ukraine, R.Luxemburg Str. 74, 83114 Donetsk, Ukraine
E-mail: [email protected]
Absrtact. This paper presents the survey of new evolutionary approach to test pattern generation problem for the sequential circuits. In the past decade, this approach has been deeply investigated and significant improvements have been reached with respect to the classical topological approach. It is discussed the advantages and disadvantages and state-of-the-art ofthe evolutionary based test generation for the sequential circuits.
1. Introduction
Test generation using deterministic algorithms is highly complex and time consuming for both descriptions of digital devices (DD) - structural (logical circuit) and functional (finite state machine). Especially it is concerned to automated test pattern generation (ATPG) methods for the devices with memory, namely, sequential circuits for structural level description. So, in the past years, new test generation methods have been proposed: symbolic approach, simulation-based algorithms and evolutionary techniques. The last approach provides good results for large sequential circuits, where other methods fail.
2. Genetic algorithms
Genetic algorithms (GA) are one of the most investigated paradigms and promising fields of modern computer science. GA are search algorithms based on the principles of natural selection. This algorithms use random directed search, which emulates natural evolution process, to construct (sub)optimal decision of given problem. Any decision is represented with a chromosome - string of elements (genes). Classical “simple” GA [1] uses binary strings that consist of binary elements {0,1} (for example, 0011101). In ATPG problem solutions are represented as binary patterns or sequences of patterns also. Therefore it looks very attractive to use GA techniques for a decision of ATPG problems.
A structure of classical GA is enough simple and represented on the figure 1. Some set of individuals (strings) is randomly selected from solutions space. This set forms population of individuals, which are potential solutions of given problem. A fitness function is determined and computed for each individual, which is a measure of its goodness as a solution of the search problem. The population evolves through generations with the help these three basic operators:
reproduction, crossover, and mutation. General flow chart of such artificial evolution is represented on Fig.1.
Fig. 1
Reproduction operator (RO) consists in a transportation of chromosomes from current generation to next one accordingly to their fitness values. The chromosomes, having greater fitness values, have greater probabilities to be propagated to next generation. Reproduction operator realizes the Darwin’s principle of the most “strongest” individual survival.
Usually crossover operator (CO) is implemented intwo steps:
1) the point of crossover k (1 < k <n) is selected for chosen two strings A = a1a2...an and B = b1b2...bn ;
2) the individuals A and B are exchanged with substrings after position k and produce two new individuals A' = a1a2...akbk+1...bn and B' = b^^ka^..^.
Mutation operator (MO) randomly changes (with small probability) some genes of population individual.
Thus it is necessary to determine individual, population, recombination, crossover and mutation operators, fitness function to GA definition. Initial population must be selected from search space for initialization of GA processing. Effectiveness of GA depends of several parameters: population size, recombination scheme, crossover and its probability, mutation and its probability, and fitness function. In next section we consider GA based approach to decision of ATPG problem for sequential circuits.
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3. Fitness functions and basic parameters to GA based ATPG
The fitness function type plays key role in the solution search process. Therefore it is important to consider different types of fitness and evaluation functions, which are used in GA based ATPG methods.
The goal of testing process is to obtain different output values of good and faulty devices. Therefore the fitness function may be defined as measure of signal value changes in the simplest case [2]. In this case a fault free logical simulation may be used. Another and more accurate approach is to define fitness function as measure of detected faults. In this case more complex fault simulation is used, but such approach allows obtaining quite good results. Obviously, that the number of signal value changes and the number of detected faults are important parameters having influence on the effectiveness of test generation process. There are certain parameters, which are important to the evaluation function definition and to the effectiveness of test generation for sequential circuits:
1) the number of gates with different values in the fault free and in faulty circuits;
2) the total number of flip-flops
3) the number of flip-flops with different values in the fault free and in faulty circuits;
4) the total fault number;
5) the number of detected faults;
6) the number of faults propagated to flip-flops;
7) the length of test sequence;
8) the population size;
9) the number of generations etc.
Below some evaluation functions of well-known GA based ATPG systems are described:
1) GATEST ATPG system [3 ]
, p2
- hi = pi H-------, where pi - the total flip-flop number,
pi
p2 - flip-flop number with different signal values in good and fault circuits and evaluation uses only the good logical simulation;
i p4
- h2 = p3 h------, where p3 - number of detected faults,
p5pi
p4 - number faults propagated to flip-flops, p5 - the total fault number;
, p4 2p6
- h3 = p3 H----------1------, where p6 - the event
p5pi p7p5
number in good and fault circuits, p7 - the node number; p4
- h4 = p3 H------, where l - sequence length;
p5pil
2) DIGATE ATPG system [4]:
- hi = 0.2pi + 0.7(p2 + p3) + 0.1(p4 + p5 + p6)
- h2 = 0.8pi + 0.i(p2 + p3 ) + 0.i(p4 + p5 + p6),
where pi - fault detectability of individual; p2 - the power sum of the distinguishing sequences (the power is determined with the number of flip-flops that must be set to propagate the fault to primary outputs); p3 - the flip-flop observability sum relatively of fault influence; p4 - weighted activity of the faulty circuit; p5 - the number of hard to set flip-flops; p6 - the number of new passed states;
3) GATTO ATPG system [5]:
- evaluation function for a single input pattern h = cipi + c2p2, where pi - the number of gates with different signal values in good and fault circuits, p2 - the number offlip-flops with different signal values in good and faulty circuits, ci and c2 are normalization constants;
- evaluation function for the entire sequence s H = max(LHi * hi), where constant LH e (0;i), i is a
vies
position of the pattern vi in the sequence s.
4. Genetic approach to sequential circuit test generation in ASMID-E system
ASMID-E is automated simulation and diagnosis system of interpretative type for digital circuits [6]. The main functions of this system are:
- text input of circuit description;
- syntactical analysis of text description;
- circuit description translation into internal data structure;
- fault-free circuit simulation;
- automatic test pattern generation;
- fault circuit simulation to determine fault coverage of generated test sequences;
- visual timing diagram observation.
The main features of ASMID-E system are:
- the system of interpretative type;
- unified approach to logical device models generation that is based on the universal system of multivalued logics;
- ability for extension of system functional possibilities without rebuilding library of logical elements;
- implementation of new fault simulation methods;
- implementation ofnew GA based test generation methods.
ASMID-E program package operates under Windows operating system family. It consists of the set of independent program components joined by head module. The interconnection of main modules is presented on the figure
2.
As mentioned above the new GA based test pattern generation method was developed and implemented in ASMID-E system. The main features of this method are as follows.
The GA based ATPG method of ASMID-E system [6] is oriented to test generation for sequential circuits. Therefore the input pattern sequence of arbitrary length is used as an individual and the set of sequences is population. For such
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kind of individual and population representation the special problem-oriented genetic operators were developed, which allows work with test sequences but not binary patterns [5].
The pseudocode of test pattern generation process with using GA for sequential circuits is bellow.
Test_ generation(sequential circuit)
{
fault set generation();
while(fault coverage < given threshold)
{
//Phase1
goal = fault sensitization(); if (goal == empty set) exit;
//Phase2
sequence = GA test sequence generation(goal);
// Phase3
if (sequence != empty)
fault simulation(sequence)
else // test sequence for goal fault not found
mark fault as untested();
}
}
The GA based ATPG method of ASMID-E system uses evaluation functions that look similar to the functions used above. But the universal multivalued alphabet is used in good and fault simulation for improving their accuracy.
Two fault simulation algorithms were integrated in order to accelerate test generation. The first one is single pattern parallel fault propagation (SPPFP) method that is used in phase 1 for checking activation of any given faultby randomly generated sequence. The evaluation function is computed with the help of second fault simulation algorithmthat belongs
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to the group of parallel pattern single fault propagation (PPSFP) methods. The second one was developed especially to using in GA based test generation algorithm.
For each simulated test pattern an evaluation function is computed by following way: h = pi + c*p2, where pi -weighted number of lines with different values in good and faulty circuits; p2 - weighted number of flip-flops with different values in good and faulty circuits, c - normalization constant that is equal to the ratio of gates number to flip-flops number. Weight is determined as observability measure and is computed at preprocessing phase.
After reaching effective length of the sequence, simulated in certain bit, or last pattern in sequence, evaluation function of whole sequence is computed:
sequence length .
H = ^ LH *hi
i=1
where i - position ofthe pattern vt in sequence; LH e (0;1] is a constant, that helps to receive shorter sequences.
The computing of evaluation functions is essentially accelerated due to the application of given algorithm. Consequently a time of test generation process is reduced too.
5. Hybrid ATPG methods
In considered methods ATPG process was represented as a GA based search process in some search space. However, there have been developed several hybrid methods that contain the advantages of GA based and deterministic ATPG algorithms. They allow to overcome the restrictions of pure GA based ATPG methods. Let consider two main approaches of these investigations in ATPG problem.
The system Hybrid CRIS was suggested in [7]. It combines structural ATPG method and CRIS algorithm [2]. The basic idea of given approach consists in overcoming of local extremum problem of GA based search algorithms with the help of application of deterministic ATPG method. This approach may be applied, for example, when fault coverage does not increase for given number of generations. In this case the deterministic algorithm is activated for improving
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fault coverage. The test sequences, generated by this method, are added in population. The processing of CRIS is renewed after overcoming critical point with the help of deterministic method.
Another example of hybrid approach is the method GA-HITEC [8] that is a result of combining GATEST and HITEC [9]. In given method the deterministic algorithm HITEC is used at the phase of fault excitation and propagation to primary outputs. GA based algorithm GATEST is applied at the phase of generation of adjusting sequence for the circuit state received as result of fault excitation and propagation. The experimental results show that hybrid method GA-HITEC exceeds deterministic method HITEC in order of test generation speed and fault coverage of generated test.
6. Adaptive genetic algorithms
In order to overcome the restrictions of pure GA based ATPG methods, like local extremum problem, there are another approach. This approach is adaptive genetic algorithms.
The classical GA based search can be considered like balanced combination of expansion to new areas of search space and processing old inspected areas of search space. This balance essentially affects on the GA performance and is defined by the probabilities of crossover and mutation operators, and cardinality of population (number of individuals). The crossover and mutations probabilities define the execution frequency of corresponding GA operators. In considered GA based methods these control parameters are constant during test generation process. In last few years, several researchers have experimented with adaptive mechanisms to dynamically vary the control parameters to improve the performance of GA.
Beyond doubt, optimal control parameters depend on the basic GA operators’ interaction and the evaluation function.
Above there have been represented GA based ATPG method [6] offollowing structure. The population of individuals - set of input sequences.
Two crossover operators:
1) vertical crossover, along primary inputs - exchanging with subsequences of input patterns with probability pci;
2) horizontal crossover, along clock cycles, with probability
pc2 ;
Three mutation operators - inversion of selected bits with probability pmi, adding input pattern to a sequence with probability pm2 , removing input pattern from a sequence withprobability pm3, are applied. All ofthese parameters are constant during test generation process.
improved the quality of the test sequences in population. Therefore search space coverage must be increased with the help of increasing mutation probabilities pmi, pm2. If Afk > 0 then mutation probabilities pmi,pm2 must not be increased. In this case mutation probability pm3 must be increased to receive shorter test sequences.
The suggested adaptation mechanism allows GA based ATPG method to operate more affective at all execution steps, in particular, more rarely to fall into the local extremum. Experimental results showed that test length was decreased on average on 5% and time of test generation was reduced on 15-25%.
7. The perspectives of test generation for highly sequential circuits
Usually sequential circuits have reset to setting circuit to initial state. In this case test generation procedure essentially becomes simpler and structural topological test pattern generation methods are used usually. Often, this condition does not take place for highly sequential circuits. Therefore the another approaches and device models are applied in this case.
Such digital device model like finite state machine (FSM) is used often. Noninitial FSM is defined with a set of five items M= (S, 1,0,5, X), where S - a set of DD states, I - an input alphabet, O - an output alphabet, X :S x I ^ S - a transition function, 5 :S x I ^ O - a output function.
Under verification approach a decision of the test generation problem is reduced to a decision ofthe identification problem of given FSM within the fault F SM class. In this case a fault model is not considered explicitly. A fault device is represented by a FSM that is different from the given one.
Note that the single transition fault model is used often under such approach [10]. FSM transition is represented with four items (s,X,Y, ~), where s - initial transition state, ~ - final transition state, i - input exciting transition symbol, o -output reaction transition symbol. The transition is incorrect if: 1) output signal is incorrect, 2) final state is incorrect, 3) both output signal and final state is incorrect. The single transition fault is represented by second case.
As a rule, at the test generation for highly sequential circuits the special characteristic sequences are used: 1) synchronizing (or initialization) sequence, 2) homing sequence, 3) distinguishing sequence, 4) unique sequence.
Let us remind the definitions of these very useful sequences.
Def.1. A synchronizing sequence of a FSM M is a sequence which takes M to a specified final state, regardless of the output or the initial state. Some FSM posses such sequences; others do not.
In order to avoid the restrictions of pure GA based ATPG methods we suggest to embed the adaptation mechanism. It
will tune GA parameters pmi (i = 1,3) during test generation process according to following rules. Let
fk
population size
I Hi
i=1
/ < population size > is average
fitness function of population for k-th generation and Af k - its growthunder transitionfrom step k to k +1. If Afk = 0 then probabilities pm1 ,pm2 must be increased. This case describes the situation when genetic operators have not
Def.2. An input sequence is said to be a homing sequence if the final state of the M can be determined uniquely from the machine’s response regardless of the initial state.
Def.3. An input sequence is said to be a distinguishing sequence if the output sequence produced M is different for each initial state.
Def.4. An input sequence is said to be a unique sequence for given initial state S if the output sequence produced M is different for given initial state S.
We should note, that in this case checking sequence definition is essentially differed from the definition using in structural topological test generation approach.
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Def.5. An input sequence is said to be a checking sequence if the output sequences produced good M and faulty Mf FSM are different for any M and M initial states.
Different models and methods are used for the characteristic sequences generation also.
1) The FSM model and the successor tree based methods are used mostly. Here at the first low level GA may be used to characteristic sequences generation. In this case individuals are input binary sequences. The genetic operators are similar to the genetic operators using in structural methods in section 6. The functions, based on computing the number of distinguished states, may be used as fitness.
2) The structural topological models may be used under the characteristic sequences generation also. U sually multivalued models and alphabets are applied in such approach. The synchronizing (or initialization) sequence generation is the most well-known and applicable in practice. In the simplest case the 3-valued alphabet is used here. The input sequence that takes a circuit from unspecified state (all state variables have undefined values) to some specified state (all state variables are set to specified binary values). The initialization sequence generation method using 3-valued alphabet and GA [11] is an example of such approach. Let us note, that this approach does not guarantee synchronizing sequence generation, though it can be obtained by successor tree based methods. It is explained by that topological methods use local transformations in contrast to the successor tree based methods using global transformations.
The capability of this approach can be increased by alphabet cardinality extension. For example, in [12] the 256-valued alphabet is used for synchronizing sequence generation. Another characteristic sequences can be generated by the both approaches - successor tree based and topological (with multivalued models application) methods . But the multiple observation time strategy must be applied [13,14]. The essence of the multiple observation time strategy is in that fact that different initial state pairs can be distinguished by input sequence on different time units and primary outputs.
Thus effectually to use two -level GA for the highly sequential circuits. Here the first level GA generates the characteristic sequences. The characteristic sequences may be generated in two ways:
1) using logical circuit representation of digital device;
2) using FSM representation of digital device.
In both cases the evolutionary approach may be used. In the first approach characteristic sequences are generated with using multivalued models and fitness functions based on computing the number of distinguishing signals on the gate and flip-flops outputs with the help of logical simulation. In
the second approach the state tables are used. The number of distinguishing states in state tables is evaluated.
At the second level the evolutionary algorithm uses for test generation together with arbitrary binary sequences and characteristic sequences generated at the first level. It makes evolutionary search more directed and increased its effectiveness.
8. Conclusion
This paper presents the survey of new approaches to test generation for digital devices with memory that are based on evolutionary techniques. The modern ATPG use integrated approach where it is combined the powerful genetic technique with traditional topological and simulation-based test generation. The advanced methods use adaptive genetic algorithms where GA parameters and basic (problem directed) operators vary during test generation.
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