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DEFECT-ORIENTED TEST PATTERN GENERATION FOR DIGITAL CIRCUITS
ELENA GRAMATOVA_____________________________
Institute of Informatics of the Slovak Academy of Sciences Dtbravsk6 cesta 9, 845 07 Bratislava, Slovakia E-mail: elena.gramatova@savba.sk Abstract
Quality of testing depends also on quality of test pattern generation techniques used for a circuit under test (CUT). Defects vary with each technology, and test pattern generation has to consider their detection. New technologies bring new defects and new problems with fault modelling. Historically, functional and structural test patterns were used in testing. Functional testing is targeted only to function and evaluation if CUT does what it is supposed to. The functional tests are expensive for a complex circuit and not sufficient because they do not cover defects which cannot be manifested logically. The next test approach - structural testing - is used with coverage metrics based on stuck-at fault (S AF) coverage. In fact, real defect coverage cannot be 100 % if the test set with 100 % SAF coverage is used. The need of high chip quality has started the progress towards defect-oriented testing. Nowadays, defect-oriented testing is the next step after structural and functional testing, and test challenge in defect-oriented test generation is a current topic. Defect-oriented testing is aimed to real wrong points of CUT developed in a specified technology. Defects can change circuit behaviour in a variety of ways therefore its behaviour has to be tested by an effective combination of multiple test types oriented to function, timing, current, voltage and temperature measurements.
One of the key points of defect-oriented testing is defect specification, classification and modelling. Each defect must be abstracted into faults. The second point is generation of an efficient and optimum test set for the specified faults. It is not sufficient to generate test patterns by random or pseudorandom algorithms. Test patterns have to be generated by sophisticated deterministic algorithms and fault simulation techniques. The objective of the lecture is focused to some ideas and approaches how to improve test generation process for receiving better quality of testing, i.e. how to generate a test set ensuring better defect coverage for a manufactured and designed circuit. The tutorial lecture is organised as follows. Defect classification and fault models fortheir usability in test generation algorithms will be presented as the first part of the lecture. Some defects are not observable by logical values but they are manifested by increasing of the quiescent current (specially in CMOS ICs). Then, the testing technique, named IDDQ testing, is based upon the fact that defective circuits produce an abnormally high value of power supply current. Test pattern generation for IDDq testing is simpler than for the classical Boolean testing because the fault effect has not to be propagated towards primary outputs. It is sufficient to set up specified values on cell inputs inside CUT if IDDQ measurement is applied. However, current testing is not meant to replace voltage based test methods; it is meant to augment them and increase the quality and reliability of CMOS ICs. The second part of the lecture is focused to test pattern generation (TPG) algorithms for both classical voltage and IDDq testing. Explanation of test generation algorithms and techniques will be concluded by test pattern generation for delay faults. Demonstration of one automatic test pattern generation (ATPG) system DefGen developed at the Institute of Informatics will complete the lecture.
Acknowledgement
The work on the tutorial lecture has been supported by the 5 FP proj ect IST-2000-30193: Research and Training Actions for System on Chip Design (Reason).
R&I, 2003, Ns 3
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