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DEFECT ANALYSIS AND PROBABILITY EVALUATION FOR IMPROVING TEST GENERATION
WITOLD A. PLESKACZ
Institute of Microelectronics & Optoelectronics Warsaw University of Technology ul. Koszykowa 75, 00-662 Warszawa, POLAND e-mail: pleskacz@imio.pw.edu.pl
It is well known from the literature [e.g. 1-5] that classical test generation methods cannot handle the actual behaviour of faulty digital circuits implemented as CMO S integrated circuits (IC). These methods allow to generate test vectors using logic-driven gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-at fault model - SAF) to describe manufacturing defects causing IC failure. As a result the circuit layout, physical defects characteristics and the actual circuit behaviour are ignored.
To overcome these limitations, in [5, 6] circuit and layout-driven test generation methods were proposed. In these works the whole circuits having hundreds of gates were analysed as single blocks. Such an approach is computationally expensive and thus highly impractical as a method of generation of tests for real VLSI designs. An alternative approach has been proposed recently [7-11]. In these works functionality of gates from a standard cell library is analysed for all possible physical defects using transistor-level simulation. This characterisation process may be computationally expensive, but it should be done only once for every standard library cell. This information can be used for defect oriented fault simulation and test generation at higher levels of abstraction [13-17]. It can be shown that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results [12].
In the tutorial lecture, a methodology for probabilistic modelling of physical defects in CMOS gates and estimation of the effectiveness of test patterns for detecting physical defects will be discussed. Quality of testing depends also on quality of test patterns generated for a circuit under test. Evaluation criteria for digital circuits te sting are fault coverage and test application time. Low efficiency of the classical stuck-at fault model in real defect coverage in CMOS logic has initiated the need of new test approaches. These approaches extend the CMOS standard cells characterisation methodology for voltage defect based testing and for IDDQ testing. The proposed methodology allows to find the types of faults which may occur in a real IC, to determine their probabilities, and to find the input test vectors which detect these faults. For shorts at the inputs two types of cell simulation conditions - “Wired-AND” and “Wired-OR” - are used. Examples of industrial standard cells characterisation indicate that a single logic fault probability table is not sufficient. Separate tables for “Wired-AND” and “Wired-OR” conditions at the inputs are needed for full characterisation and hierarchical test generation.
Acknowledgements
The work on the tutorial lecture has been supported by REASON - “Research and Training Actions for System on Chip Design” (IST-2000-30193), an IST project funded by the European Union.
References: 1. Chakravarty S. Defect based testing / Invited talk at the 4th Int. Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001, Gyor, Hungary, April 2001.2. Soden J.M., HawkinsC.F. Quality Testing Requires Quality Thinking / Proc. of the Int. Test Conference, pp. 596, Baltimore, USA, October 1993. 3. Maly W., Shen J.P., Ferguson J. System. Characterization of Physical Defects for Fault Analysis of MoS IC Cells / Proc. of the Int. Test Conference, pp. 390-399, Philadelphia, USA, October 1984. 4. Shen J.P., Maly W., Ferguson J. Inductive FaultAnalysis ofMOS ICs // IEEE Design&Test, 1985. PP.13-26. 5. Nigh P., Maly W. Layout - Driven Test Generation / / Proc. of the IEEE Int. Conference on Computer-Aided Design -ICCAD-89. Santa Clara, USA, November 1989. P. 154-157. 6. JacometM., Guggenbuhl W. Layout-Dependent Fault Analysis and Test Synthesis for CMOS Circuits // IEEE Trans. on Computer-Aided Design, 1993. Vol. 12, N°. 6. P. 888-899. 7. BlyzniukM, Pleskacz W.A., LoburM., Kuzmicz W. Estimation ofthe Usefulness of Test Vector Components for Detecting Faults Resulting from Shorts in Standard Cells // Proc. Int. Conference: “Mixed Design of Intengrated Circuits and Systems” - MIXDES 2000, pp. 527-532, Gdynia, Poland, June 2000. 8. Pleskacz W.A., Kasprowicz D., Oleszczak T., Kuzmicz W. CMOS Standard Cells Characterization for Defect Based Testing // Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems -DFT’01, San Francisco, USA, October 2001. PP. 384-392. 9. Blyzniuk M., Kazymyra I. , Kuzmicz W., Pleskacz W. A., Raik J., Ubar R. Probabilistic Analysis of CMOS Physical Defects in VLSI Circuits for Test Coverage Improvement // Microelectronics Reliability (PERGAMON - Elsevier Science). December 2001. Vol. 41/12. PP. 2023-2040. 10.Pleskacz W. A., Borejko T., Kuzmicz W. CMOS Standard Cells Characterization for IDDQ Testing // Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - DFT’02. Vancouver, Canada, November 2002. PP. 390-398. 11. KasprowiczD., Pleskacz W. A. Improvement of Integrated Circuit Testing Reliability by Using the Defect Based Approach // Microelectronics Reliability (PERGAMON - Elsevier Science), June 2003. Vol. 43/6. PP. 945953. 12. BlyzniukM., Cibakova T., Gramatova E., Kuzmicz W., Lobur M., Pleskacz W.A., Raik J., Ubar R. Defect Oriented Fault Coverage of 100% Stuck-At Fault Test Sets // Proc. of the 7th Int. Conference “Mixed Design of Intengrated Circuits and Systems” -MIXDES 2000. Gdynia, Poland. PP. 511-516. 13. BlyzniukM , Cibakova T., GramatovaE., Kuzmicz W., LoburM., Pleskacz W.A., Raik J., Ubar R. Hierarchical Defect-Oriented Fault Simulation for Digital Circuits // Proc. of the IEEE European Test Workshop. Cascais, Portugal, May 2000. PP. 69-74. 14. Kuzmicz W., Pleskacz W., Raik J., Ubar R. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits // Proc. of the 2001 IEEE 2nd International Symposium on Quality Electronic Design - ISQED 2001, San Jose, USA, March 2001. PP. 365-371. 15. Cibakova T., Gramatova E., Kuzmicz W., Pleskacz W., Raik J., Ubar R. Defect-Oriented Library Builder and Hierarchical Test Generation // Proc. of the 4th Int. Workshop on IEEE Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS 2001, Gyor, Hungary, April 2001. PP. 163-168. 16. Kuzmicz W., PleskaczW.A., RaikJ., UbarR. Module Level Defect Simulation in Digital Circuits // Proceedings of the Estonian Academy of Science - Engineering, Vol. 7/4, pp. 253-268, December 2001. (Proc. Estonian Acad. Sci. Eng., 2001, 7, 4, 253-268). 17. Cibakova T., Fischerowa M., Gramatova E., Kuzmicz W., Pleskacz W.A., Raik J., Ubar R. Hierarchical Test Generation for Combinational Circuits with Real Defects Coverage // Microelectronics Reliability (PERGAMON -Elsevier Science). July 2002. Vol. 42/7. PP. 1141-1149.
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