Coverage Problem Solving on Quantum Computing Текст научной статьи по специальности «Компьютерные и информационные науки»

Coverage Problem Solving on Quantum

Computing

Hahanova I.V.

Abstract - The qubit (quantum) structure of data and computing processes that allows significantly increasing the speed of binary optimization problem decisions was proposed. The hardware parallel models (one cycle) for Boolean (set of all subsets) calculation on the basis of n-element universum for coverage decision solutions, boolean function optimizations, compression of data, digital systems synthesis and analysis that use the Hasse diagram for implementation processor structure were described.

Index Terms - quantum computing, hardware model, Boolean function, processor.

I. Introduction

The purpose of the qubit-processor creation is significant reduction of time that needs to decision of the optimization problems by using concurrent calculation of the vector logical operations [1-3] over the set of all subsets of the primitives through the cost of increasing the memory size for intermediate data saving. Problems of the research are the follows: 1) Definition of data structures for boolean decision coverage problem of columns of a matrix

M = |My|,i = 1,m;j = 1,n by ones from the rows. In

particular, for case m = n = 8, It should be done the concurrent boolean operation on 256 combinations of the vectors (the matrix rows) that form boolean. 2) The instruction set processor should have m-bit vector operations: and, or, xor; 3) Developing of the qubit-processor architecture for concurrent processing of the

2 — 1 data combinations that direct to the optimal solution of the NP-complete coverage problem; 4) Qubit-processor prototype implementation into PLD and hardware model verification [2-13] based on the boolean function optimization solutions. 5) Bringing other practical discrete optimization problems to a form of the coverage task that allows processing them on the qubit processor. As an example it was solved searching of the minimal row number that cover all 1’s in columns of the following matrix M:

Manuscript received November 18, 2012

Hahanova I.V. is with Computer Engineering Faculty, Kharkov National University of Radioelectronics, Kharkov, Ukraine (e-mail:

[email protected]).

M 1 2 3 4 5 6 7 8

a 1 . 1..

b 1.. .1.

c 1 . ..1 .1.

d . 1 . 1 . ..1

e . 1 ..1

f 1. 1.. 1 1 .

g .1 .1. ..1

h 1.1

The computation complexity of the problem solution depends of checking of all 255 row combinations: one with 8 rows, two with the others, three, four-, five, six, seven, and eight. The optimal solution is the minimal number of rows forming coverage. There can be some optimal solutions. The Hasse diagram is a compromise between time and memory size, or solution strategy where previous results are used to form the next more complex superposition. Therefore, it is necessary for each cover table that consist of n primitives (rows) to create own multiprocessor structure in form of Hasse diagram, that can be used for NP full, problem solution. For example, figure 1 shows the Hasse diagram multiprocessor structure for the four row table.

optimal solutions coverage problem for the matrix M that generates 255 possible combinations are presented at the form of DNF lines: C = fghvefgvcdf. Finite state machine for the quantum computing process structure by bottom-up analysis of vertices based on the implementation of the following step sequential:

Fig. 1. Quantum structure computing processes

1. Store information in the registers of the primitives

(matrix) L1 = Pi of the first level, followed by an analysis

of the coverage quality of the each primitive in a binary format (1 - a covered, 0 - no covered). If one of the

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primitives forms the full coverage

m 1 л L1.

j=1 1J

1 the process of

analyzing the Hasse diagram are finished. Otherwise, the transition (r = r + 1) to the next level of the graph are executed:

1 m 1 |0 L1 = P ^ л L1. = l

i i j=1 ij l1

0 ^ n = n +1; ^ end.

2. Initialize the next (second) level of the process. Consistently implement the vector (matrix) operations (or 1 m 1 m

Lr = Li л Li , and л Lr- = 1) in order to analyze the

i ij j=1 tj j=1 ij

coverage ability of the r-level primitive combinations. Here t = 1,m, i = 1,m, r = 1,n, where n is the number of levels or

the number of rows in the cover table, m is the number of columns in it. If a combination of at the present level creates a full coverage, which forms an assessment equal to 1, the processing of all subsequent levels of the processor is canceled. Otherwise, the transition to the next level of analysis of the structure of the processor:

Lr = Lr-1 ЛЛ Lj1 i ij j=1 tj

m

^ л Lr- = j=1 ij

0 ^ r = r + 1;

1 ^ end.

To find the best coverage is always enough to have only two elements of the lower level. It means that all operating vertices have got two register (matrix input), which significantly reduces the cost of the hardware design. The number of time cycles for processing structure of the processor is equal n in the worst case. You can create an algorithm for finding the optimal coverage through top-down analysis of the vertices. In this case, finding the full coverage in one of the levels needs another structure descending to make sure that there is no bottom to the next level of complete coverage. If it is right the obtained solution is optimal. Otherwise the down levels should be analyzed until the adjacent layer will not contain complete coverage. The vertices of processor structures can have more than one binary (unary) the register logical operation. Then you need to create a simple instruction decoder to enable other operations, for example: and, or, xor, not. Thus, the advantages of Hasse qubit processor (Quantum Hasse Processor - QHP) is the ability to use no more than a 2-input gates for the vector logical operations (and, or, xor), and thus, substantially reduce the cost of implementation by Quine of the processing elements (vertices) and memory through the use of sequential computations and a slight increase in processing time of all vertices of Hasse diagram. For each vertex the quality coverage measure is the presence ones in the all coordinates of the vector result. If the quality criterion is satisfied all the other calculations can be escaped, because the Hasse diagram is a strictly hierarchical structure according to the number of combinations in each levels. This means the best solution is at a lower level of the hierarchy. The same level options are equivalent to implementation, so the first high-quality

n

coverage (Q = 2 qi = n) is a better solution that suggests i=1

stopping evaluating of all further strategies of the Hasse diagram.

Considering the sequence-concurrent strategy of the vertex analysis of time that is taken to process all primitives of the QH-processor is equal to the number of hierarchy levels (the number of bits (primitives, rows in a cover table) of the qubit variable) multiplied by the time the

of the single vertex analysis: T = log2 2n x t = t x n . The length of the row m of the cover table does not affect to the performance evaluation. The graph vertex analysis includes two kinds of command: the logical (and, or, xor) and a calculating test coverage quality operation that is implemented by applying and-reduction function to all bits of the result vector:

mir j = Mi j v Mr j, (j = 1,n;{i Ф r} = 1,m;);

msr = ^ir,j = 4Mi,j v Mr,j)

The cost of the hardware implementation of the QH-processor depends of the number of the Hasse diagram vertices and the number of the row cover bits:

H = 2n x k x m, where k - coefficient of hardware implementation (complexity) of one bit of a binary vector operation and the subsequent calculation of the command coverage quality. Thus, high performance of the coverage problem solutions is achieved by a significant increase of

hardware cost (in 2n x k x m/k x m x n = 2n/n time compared to the sequential processing of graph nodes) that provides a compromise between fully parallel structure of computational processes (here the cost of equipment depend of the number of primitives in each vertex

H = k x m x n x 2n, and the increase of equipment is equal 2 n time) and sequential evaluation uniprocessor computer

(here Hasse diagram performance is equal T = t x 2n, and well as hardware cost is equal H*=kxmxn).

Reducing hardware size in comparison with the parallel version of graph processing is

QH = k x mx n x 2n /k x mx 2n = n times. The result of the significant hardware redundancy is vertex analysis time reduction in compared to sequential structure and it has the following estimate:

QT = 1x2^ = 2^ t x n n

Thus, the hardware-oriented model of concurrent boolean calculating (the set of all subsets) on the universe of the n primitives for coverage minimization of Boolean functions, data compression, analysis and synthesis of digital systems through the implementation of the processor structures in the form Hasse diagram is described above. The prototype of a quantum device, implemented on the basis of programmable logic devices for optimal coverage problem solution in the cyberspace analysis is presented in Section 4.

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II. WlNDOWS-DECOMPOSITION METHOD TO SOLVE THE COVERAGE PROBLEM

The matter of the problem is the large dimension cover table, for example 1000x1000, in this case it is almost impossible to process the optimal coverage solution that has exponential complexity in reasonable period of time. So it is necessary to use optimization approach that can significantly reduce the time and make it acceptable to the practice. Below there are several strategies that allow reducing the time spent to process the large dimension cover tables.

1. Method of the cover table decomposition by string slices

C = {C1,C2,...,Ci,...,Cn},Ci = (Cil,Ci2,...,Cij,...,Cim).

Each segment contains m lines, provided that the dimensions of the table and the segment are equal

|C = n x m x k and |Cjj | = m x k , respectively. Here m is

the number of rows in the segment or the number of variables in the Hasse processor, k is the length of the string in the cover table that has to be processed in parallel, n is the number of segments. Disjunction operation is performed on all rows in each segment and after that the table dimension is lowered to m times. If the dimension of the resulting segment table is more than the number of inputs Hasse processor, then it is again the procedure of decomposition. Thus, the original table into a multi-layered cover pyramid, where the upper size is determined by the number of lines, no more than the amount of the inputs of the Hasse processor. For example, if the processor has 8 variables to process concurrently the eight rows of the cover table, the previous (lower) levels should be increased by 8 times (Fig. 2 a). It takes only 5 cycles of matrix multiprocessor Hasse system to process concurrently the table with dimension 32768x3276. At each level the segments that are involved in the higher level declared coverage formation are selected. Keep in mind that presegmentation of whole cover space rows is performed until the last level will have the number of segments less or equal to eight (Fig. 2 b).

Level m

1 8

2 64

3 512

4 4096

5 32768

Level m

1 32768

2 4096

3 512

4 64

5 8

a b

Fig. 1. Quantum structure computing processes

At each level the vector coverage quality of the higher level segments is computed. Vector operation or is used as

k

it is showed below: C;j = ® C;jr. For example, the

r=1

coverage table with the dimension 16 to 16

M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

a 1 1 1

b . . 1 . . . 1 1.1.

c 1 . . . 1 1

d . . . 1 . . . 1 . . 1

e . ... 1 ... 1 . . . . 1 . .

f 1 . 1 . . . 1 1.1

g . . . 1 . . . 1

h . . 1 . 1 . . . 1 . 1 . 1 . 1 . 1 . 1 . . 1 . . 1 . .. . . . 1

j k 1 .. 1 ... 1 ... 1 ... . . 1 . 1 . . . . 1 . 1 . . . . .

m 1 ... 1 1 1 . . .

n 1.1

p 1

q ...1.1.11 1 .

has to be divided into 4 segments, where each of them consists of four vectors:

M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

a b c d 1 1 1 . . 1 . . . 1 1.1. 1 . . . 1 1 ... 1 ... 1 . . 1

e f g h .... 1 ... 1 . . . . 1 . . 1 . 1 . . . 1 1 . 1 ... 1 ... 1 . . 1 . 1 . . . 1 . 1 . 1 . 1 .

i j k l . 1 . . 1 . . 1 1 .. 1 ... 1 ... 1 ... . . 1 . 1 .... 1 . 1 . . . . .

m n p q ... 1 1 1 . . . .1 1 1 ...1.1.11 1 .

1.111.111. 1 . 1 . 1 1 1.111.111. 1 . 1 1 1 1 . 1 1 . . 1 . 1 1 . 1 1 . . . 1 ..1111.111 1 . 1 . 1 .

After that, the disjunction of all the s-vectors of each segment is processed, and the result is stored in the (s +1)-vector of the corresponding segment. Then all these vectors are used to solve the coverage problem, but at the higher hierarchy level.

2. The decomposition method for two-dimensional table

coverage segments.

M 1 23 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

a 1 1 . 1 . 1 .

b 1 1 . 1 1 1

c 1 1 1 1 . .

d 1 1 1 1 . 1 . .

e 1 1 . 1

f 1 1 1 1 1 1

g 1 1 . . 1

h 1 1 1 . 1 . 1 1 1

i 1 1 . 1 .

j 1 1 .

k l 1 1 1

m 1 . 1 1 1

n . 1 . 1 .

p q 1 1 1 . 1 . . 1

r 1 1 1 . 1 1 1 . .

s 1 1 1 1 . 1 . 1 1

t

u 1 1 1 . 1

v 1

w 1 1 1 1 . . 1 1 1

x . 1

y 1 1 1 . . 1 1

q1 1 1 1 1 1 1 1 . 1 . 1 1 1 1 1 . 1 111 1

q2 1 1 1 11 1 1 . 1 1 1 . 1 1 1

q3 1 1 1 1 1 1 11 1 . 1 1 1 . 1 1 1 1 . .

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After the window partition is finished, (s +1, t +1)-vectors are calculated basing on vector disjunction through all s-t-vectors of each window, and the result is stored in (s +1, t +1)-vector of the corresponding (s + 1, t +1)-window. Then all these vectors are used to solve the covering problem at a higher level of the (s +1, t +1)-vectors.

The partition of the table to the segments and the windows has benefits of decreasing in time of the problem solution through the parallel approach where all segments (windows) are processed simultaneously. The drawback is the quasi-determined solution that may differ from the minimum coverage. Below there are the numerical estimates of the costs and benefits of the implementation of two strategies of the proposed optimization method:

Hr

2

n

(2n1 + 2n2 +... + 2ni +... + 2nk) + 2n/u

Hu

[(2nl + 2n2 +... + 2ni +... + 2nk) + 2n/u] x -

n = 1000;n1 = n2 = ... = n; = ... = = 10; r = 1000;u = 100^

H

H

2

1000

2

1000

10 x 2100 + 2

1000

>0/ 10 x 2100 + 210

/100 10 x 2 +2

2

1000

2

1000

1000

(10 x 21W + 2 *““) x

100 , 2 z'100 ) x 1000 1000 x 2100 +100 x 2

+ 2 )x 10

10

n

2

u

Here, the first estimate is the timing cost gain of the solution the coverage problem throgh partitioning the table into k segments, and the second estimate is the gain when string with length r, is divided into segments with length u,

r

that is equal to the number of segments —. Profit generated

u

by the simultaneous processing of segments or windows. After that, the problem is reduced to covering the segment table. Then an exact result that consist of the strings of segments involved in the cover of the original table is formed of. This method is focused on concurrent processing of all quadrants (windows) by Hasse-processor, the number of them is determined by the number of quadrants. Thus, the cost of the high performance of the concurrent processing is hardware redundancy, depending on the number of windows on the lowest level of the hierarchy table cover.

III. Hardware implementation of QH-processor

A software generator for creating the Verilog code of the Hasse multiprocessor models with different configuration parameters is designed. As input data generator use: the number of input vectors, their length in bits. The program is written on Python 2.7 programming language, and contains 255 lines of code.

The class structure that is designed by the ArgoUML software tools is shown in Fig. 3.

Fig. 3. The class structure of the program (ArgoUML)

It includes the main class Generator, as well as indices of internal registers generator model, that is selected in a separate class genIndex.

The genIndex class has variables: levels is the number of levels in the model (corresponding to the number of Hasse processor inputs), level is the current level of the index register generate, ind_lisc is the list of string values of the indices. The class has two methods: genLevel () and getIndList () which generates and returns a list of indices. objects of the genIndex class are used in the methods of the Generator class that create descriptions and implementations of the registers.

The Generator class has variables: numInputs is the input number of the Hasse processor model, numBits is the length of the input / output vectors, file_name is file name of the model, inter_output may be equal “True” or “False” and allows to disable the generation of attribute outputs for registers internal levels. Initialization method sets the variables their default values.

def ___ init__ (self, numInputs = 4, numBits = 8,

file_name = "model.v", inter_output = True):

Any of the parameters can be changed during creation of the Generator class instance, for example: numInputs = 16 numBits = 8

obj1 = Generator(numInputs, numBits, "model"+str(numInputs)+".v", False).

Functional parts that form the Verilog model of the processor are shown in Fig. 4.

Header__________________________

Input definitions_______________

Output definitions_______________

Register declarations Register implementations Outputs assignments End______________________________

Fig. 4. Verilog model structure of the processor

For implementation of the each part of the model following Generator class methods were designed:

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outTitle(), outInput(), outOutput(), outRegDeclaration(), outRegImplemen(), outAssignImplemen() and outEnd(), respectively. Method genRegDefinition(name1, name2, vec = True) is called by outRegDeclaration(). Method generate() that uses the other methods of the class to perform generation of the whole model and write it to a file. In addition the outTitle() and outEnd() functions open and close the external file also. def outTitle(self):

self.f = open(self.file_name, 'w') self.f.write("module device\n (input clk, rst,\n") def outEnd(self):

self.f.write("\nendmodule")

self.f.close()

Tab. 1 illustrates how the device external line number is increased according to rising of the number of the inputs (numInputs). It is obvious that the number of the input signal bits (numBits) doesn’t significantly effect on the total number of the inputs and outputs of the model.

Table 1

The Dependence Of The Output Number On The Input Number

(Numinputs) And Their Length (Numbits)

numinputs numBits

4 8 12 16 20 24 28 32

4 31 55 79 103 127 151 175 199

6 83 115 147 179 211 243 275 307

8 279 319 359 399 439 479 519 559

10 1 051 1 099 1 147 1 195 1 243 1 291 1 339 1 387

12 4 127 4 183 4 239 4 295 4 351 4 407 4 463 4 519

14 16 419 16 483 16 547 16 611 16 675 16 739 16 803 16 867

16 65 575 65 647 65 719 65 791 65 863 65 935 66 007 66 079

18 262 187 262 267 262 347 262 427 262 507 262 587 262 667 262 747

The model of the device that has 16 inputs, where the length of each input is 8 bits, is implemented using Xilinx Spartan-3E chip: xc3s1200e.

In this case, the resulting circuit contains 3337 flip-flop FF and 3233 4-input lookup tables FUT:

Logic Utilization:

Number of Slice Flip Flops: 3,337 out of 17,344 19%

Number of 4 input LUTs: 3,233 out of 17,344 18%

The generated Verilog code of the 16 input quantum processor has 288,738 lines (16 kb) Based on the results of static timing analysis (Fig. 5), the minimum operating cycle time is equal 9.2 ns that corresponds to 108 MHz frequency.

Clock elk to Pad

------------+-------------+------------------+-------+

I elk (edge) I I Clock I

Destination | to PAD |Internal Clock (s) | Phase |

------------+-------------+------------------+-------+

ol5<0> | 7.280(P)|clk_BUFCP | O.OOOI

ol5<l> | 7.512(P)|clk_EUFCP | O.OOOI

olS<Z> I б.ЭЭЭ(Р)|clk_BUFGP I 0.0001

ol5<3> I 8.072(P)Iclk_BUFCP I 0.0001

ol5<4> | 7.866(P)|clk_BUFCP | 0.0001

ol5<5> | 3.242(P)|clk_BUFCP | O.OOOI

ol5<6> | 7.884(P)|clk_EUFCP | 0.0001

olS<7> I 9.186(P)|clk_BUFGP I 0.0001

ol6 I 7.680(P)|clk_BUFGP I 0.0001

------------+-------------+------------------+-------+

Clock to Setup on destination clock elk

---------------+----------+---------+--------+---------+

I Src:Pise I Src:Fall| Src:Pise| Src:Fall| Source Clock |Dest:Pise|Dest:Pise|Dest:Fall|Dest:Fall|

---------------+----------+---------+--------+---------+

elk | 4.250 | | | |

---------------+----------+---------+--------+---------+

Fig. 5. Time parameters of the 16-input Hasse processor

The GuI of the program code generator that was designed to generate scalable Hasse multiprocessor models is shown in Fig. 6.

The synthesis and the implementation of the Hasse processor model was done using open software IsE from Xilinx Inc. The result of its work for 5.5 hours on the Intel processor, 2.1 GHz, is presented in the form of circuit topology xc3s1200e two components at Fig. 7: a) the general plan chips after the Place & Rout procedures of the Implementation stage; b) enlarged fragment of the chip, namely the lower left corner.

a

Fig. 7. Placing the device in the chip xc3s1200e: the general plan (a), enlarged fragment (lower left corner) of the chip (b)

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IV. Conclusion

The scientific innovation lies in the proposed qubit data structure and quantum model of computational processes, which are based on the use of the Hasse diagram and allow improving significantly (x10-x100) performance of the discrete optimization problem solving. The quasi-optimal method for solving the coverage for large dimension tables was proposed, it differs from the analogue ones due to it has the preliminary phase of the matrix decomposition into segments or windows that allows significant reduction of searching time by applying the parallel register logical operations on the rows of the table. The hardware-oriented model of concurrent (one cycle) calculating of the power set (the set of all subsets) on the n primitive universe for solving covering minimization of Boolean functions, data compression, analysis and synthesis of digital systems through the implementation of the Hasse diagram processor structure was described.

The practical importance of the research lies in the following. Hardware Hasse multiprocessor implementation into the chip Xilinx Spartan-3E: xc3s1200e can

significantly reduce the optimization problem solution time by concurrent computing the logical vector operations by increasing the number of processing elements and memory that store intermediate data. Automatic code generator is built in an environment Python significantly reducing (x3 x5) the Verilog code design time and create scalable Hasse processor models for subsequent implementation in Xilinx FPGA chip.

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