Concurrent controller design by means of high-level Petri nets

Wegrzyn Agnieszka

венств (2), то и общая точка, найденная в этом домене, не будет удовлетворять (2) и, следовательно, все точки отображаемой поверхности i-го ГП не принадлежат k-му домену, что и требовалось доказать.

Запишем в виде предиката P5 условие (10), причем P5 = 1, если условие (7) выполняется, и P5 = 0 , если не выполняется. Тогда, с учетом утверждения 3, окончательно функция принадлежности бприн будет иметь вид

{прин = f • P5 = P1 • P5 • [a v a (p3 V P4>]. (11)

Утверждения 1, 2, 3 и соотношение (11) являются основой для построения алгоритма классификации, состоящего из следующих этапов.

Этап 1. Из исходного количества доменов Nd выбирается k-й домен.

Этап 2. Для i-го ГП вычисляется соотношение (11) и устанавливается принадлежность ГП k-му домену. Соотношение (11) рекомендуется вычислять в следующем порядке. Устанавливается значение двоичной переменной а. Если а= 1, то вычисляется P5, затем Pi и далее P3 или P4. Если а=0, то вычисляется только Pi. Этап 2 повторяется для всех ГП.

Этапы 1 и 2 выполняются поочередно для всех К доменов, и в процессе вычислений заполняется список — классификационное описание. На этом работа алгоритма завершается.

UDC 519.714.5

CONCURRENT CONTROLLER DESIGN BY MEANS OF HIGH-LEVEL PETRI NETS

WEGRZYN AGNIESZKA__________________________

Concurrent controllers can be modelled using Petri net. Petri net is a graphical and mathematical modelling tool. It can describe processing systems, characterized as being concurrent, asynchronous, distributed, nondeterministic [5]. Wide theory of Petri nets is a powerful tool for modelling and analysis of the behaviour of logic controllers. In the paper, a system for modelling, simulation and analysis of logic controllers described by Petri nets is presented. The new tool (XML language) for modelling Petri net and new possibility connected with it is presented, too.

1. Introduction

Design of concurrent controllers consists of a few steps. The first step is modelling. A large majority of logic controllers perform parallel actions. By reason of it, very useful tools for modelling of such circuits are the Petri nets. Petri nets are the mathematical objects that exist independently of any physical representation. The nets can effectively describe parallelism.

3. Результаты и рекомендации

Выполнено моделирование предложенного алгоритма при составлении классификационного описания ДО, представленного на рис.1. Данный объект имеет графических примитивов N га = 85 , доменов Nd = 3840 . Классификация всех ГП выполнена без их потерь.

Предлагаемый алгоритм целесообразно использовать при составлении описания динамических объектов для синтеза изображения методом обратного трассирования в системах визуализации.

Литература: 1. Foley J.D., van Dam A., Feiner S.K., Hughes J.F. Computer Graphics (principles and practice) by Addison-Wesley Publishing Company, Inc. 1996. 1175 p. 2.Гусятин B.M. Итерационный алгоритм синтеза изображения в растровой графике реального масштаба времени // Радиоэлектроника и информатика. 1998. №3. С.81-83.

Поступила в редколлегию 05.02.2002

Рецензент: д-р техн. наук, проф. Кривуля Г.Ф.

Гусятин Владимир Михайлович, канд. техн. наук, доцент кафедры электронных вычислительных машин ХНУРЭ. Научные интересы: теория и практика построения спецпроцессоров растровых графических систем реального времени. Адрес: Украина, 61166, Харьков, пр. Ленина, 14, тел. 40-93-54, 66-61-22.

Филимончук Михаил Анатольевич, аспирант кафедры электронных вычислительных машин ХНУРЭ. Научные интересы: теория и практика построения спецпроцессоров растровых графических систем реального времени. Адрес: Украина, 61166, Харьков, пр. Ленина, 14, тел. 40-93-54._______________________

The most important design stage is analysis. In the paper, two methods of formal analysis and one method of simulation are described.

In presented design system PeNCAD (section 3), Petri nets are modelled using XML. Because of this fact, it is possible to simulate using SVG graphics. For large Petri net models, such method of analysis is very inconvenient.

As Petri nets have well-defined semantics, their formal analysis is possible. The analysis of Petri net is based on checking some properties of Petri net called liveness and boundedness. Liveness is one of the most important properties in Petri net analysis.

In section 3.3, two methods of analysis are presented. Both methods use special expressions called Horn formulae as the representation of Petri nets. In the first case, Horn formulae are solved using Thelen’s tree and the second algorithm is based on ROBDD diagram. These methods are suitable for Extended Free Choice (EFC) Petri net.

Analysis techniques can be grouped into three classes:

1) analysis of interpreted Petri net;

2) analysis based on testing a net depending on initial marking;

3) structural analysis based on testing a net independent on initial marking.

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Presented methods (section 3.3) belong to the third class of analysis techniques.

2. Basic definitions of Petri net

A Petri net is a well-known mathematical formalism. The graphical form of a Petri net is used as a tool for the modelling and analysis of digital circuits, especially concurrent controllers. There are different classes of Petri nets [5]. However, for the modelling of digital systems only selected classes are applicable. First of all, only basic information and definitions are presented.

Petri net is an oriented bipartite graph with two subsets of nodes called the places and the transitions and the arcs joining places to transitions or transition to places.

A Petri net PN is a 4-tuple [5]:

PN=(P, T;F,Mo),

where P — a finite set of places; T — a finite set of transitions; F — flow function (i.e. a finite set of arcs); M0 — initial marking.

An ordinary Petri net PN=(P, T;F,M0) is extended free choice (EFC) iff

Vt, t'e T: • t n »t' Ф 0 ^ »t = »t'

equivalently: Vp, p'e P: p • np'» Ф 0 ^ p» = p'»

Fig. 1 presents an example of interpreted Petri net.

The analysis of digital circuits can be considered in terms of checking Petri net properties, especially liveness.

Liveness can be described as follows [2,5]:

— Transition t є T in PN, is live iff:

VM є [M0) 3M 'є [M): t is enabled at M'.

— PN is live iff V te T: t is live.

In addition, other definitions are presented [2,5]:

— PN is deadlock free iff:

VM є Mo) 3t є T: t is enabled at M.

— Transition t є T in PN, is dead iff:

-i3M є [Mo): t is enabled at M.

— VM є [Mo): is dead marking iff:

-,3t eT 3M'є [M0):[Mt)M'.

A deadlock in a Petri net is a transition or a set of transitions, which cannot be fired. Petri net is live iff no unmarked deadlock can be found.

Equation (1) shows the expression describing deadlock in Petri nets:

П teT^ p;et» (УІ +Z!pj<=*t/yj) , (1)

where t, T — (respectively) transition, set of transitions; • t, t • — input and output places of transitiont; pi, pj

— places; yi — variable representing place pi, i.e. pi ^ Уі = 0 .

Hierarchical Petri nets

Most practical systems have a very large number of states and transitions. A large Petri net model is unclear and ineffective. A solution to such problem is hierarchical Petri net.

A net can be constructed as the multiple modules that can be modified independently of each other. Various modules can be linked together as needed to create a net. The same module can be used repeatedly at different places in a net, so that redundant logic is not needed to handle the same situation in different contexts.

Hierarchical Petri nets consist of macroplaces and macrotransitions. There are different approaches to constructing hierarchical Petri nets. In one of them, macromodules can be created for P-net and T-net. At the beginning, it is checked, whether Petri net contains a P-net and a T-net, and it is exchange into macromodule. The next step is searching parallel branches that have the same input and output transition. Such branches are exchanged into macromodules. These steps are executed so long as all parallel branches will be exchanged.

3. PeNCAD system

PeN CAD system for modelling, analysis and synthesis of logic controllers is being developed at Technical University of Zielona Gora.

The textual format of Petri net (PNSF2) is used as an entry format. On the other hand, Petri net can also be alternatively modelled using well-known hardware description languages (HDLs), particularly with Verilog or VHDL. In addition, for modelling Petri nets, Design/ CPN system can be used, as well. In Design/CPN, coloured Petri nets can be modelled, simulated and analysed. PeNCAD has two entries: graphical and textual. As a graphical input a dedicated editor or Design/CPN are used. Then, the net is analysed by means of this system. Design/CPN uses a textual format that is based on ML (Markup Language) language, and it is called CPN mL. For translation from CPN ML format into PN SF3 (i.e. into PeNCAD system) it is used a program written in J ava language. Such a solution gives opportunity for using the same program on different platforms, e.g. SUN Solaris or PC LINUX.

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Ifa Petri net is correctly designed, it could be synthesised using PeNCAD system. There are two methods applied. In the first one, a Petri net is modelled in HDLs, and then it is synthesised by using standard synthesis tools. In the other one, a Petri net is directly mapped into a netlist. There are two approaches to such synthesis: one level and hierarchical. Finally, the net is implemented into FPGA structure. For this purpose vendor-depended development tools are used, e.g. Xilinx M1 system. In Fig. 2 a general scheme of PeNCAD system is shown.

3.1. XML modelling

program execution. During the simulation it is possible to check whether a circuit modelled by a Petri net behaves correctly. Therefore, it is possible to recognise and remove errors in the controllers, even at an early stage of the design.

Several specifications and design techniques based on Petri nets have been proposed [1]. They are based on software tools that help designers to develop and simulate (animate) the system at a conceptual and abstract level. They are usually very formal and oriented towards the verification (simulation) aspects of the design.

Petri net can be presented in a textual form as a set of rules. Petri Net Specification Format 3 (PNSF3) is one of such textual formats. The format is based on Extensible Markup Language. PNSF3 is developed at Technical University of Zielona Gora and it is based on PNSF2. Using PNSF3, an interpreted, hierarchical and coloured Petri net can be modelled.

The PNSF3 format specifies the structure of Petri net. PNSF3 does not keep information about placement of places, transitions, arcs, etc. It keeps information about names of places, transitions, number of markers, connection between places and transitions. That’s why this format is simple to create and modify. PNSF3 format is easy to parse and converse to various representations. Such a way of describing provides new possibilities, for example simulation of Petri nets using a scalable vectorgraphics.

Most Petri-net research groups have their own software packages and tools to assist the drawing, analysis and simulation ofvarious applications. They have their own Petri net formats, too [6]. Now, XML based format helps to exchange data between various tools. Such approach gives possibility to verification new methods of analysis using well-known and tested systems. The old formats of describing Petri nets are insufficient to be applied for such verification. The goals for new XML based format are [10]:

— flexible (extendable),

— complex description,

— platform independent,

— human readable,

— easy to parse and transform.

The format presented above in (Fig. 3) is different from an XML based format used in other Petri net tools. They differ in storing information about Petri nets. In otherwell-known systems for modelling and analysis, an XML based format keeps information about placement of elements of Petri net [6]. It is very difficult to prepare such a format without a graphical editor is very difficult. As system in which PNSF3 is used, have no graphical editors: information about placement cannot be stored there.

3.2. Simulation

The next step (after modelling) in the design of digital circuits is analysis. There are different methods of verification modelled systems. One of the simplest methods is simulation. It is similar to the debugging of

The main advantage of XML is that it is very easy to transform it into another format (e.g. SVG). In this section a way of transformation from XM L based format (PNSF3) into SVG is presented.

SVG is a language for describing two-dimensional graphics in XML. SVG allows three types of graphic objects: vector graphic shapes (e.g., paths consisting of straight lines and curves), images and text. Graphical objects can be grouped, styled, transformed and composed into previously rendered objects.

A large majority of generally available XML based format use XSL to transform it into another format. XSL is a stylesheet language for XML. XSL specifies

PeNCAD

HDL Symulation (behavioral, postsynthesis, postlayout

Analysis

CPN ML -> PNSF2 (lexical, syntax)

Synthesis Tools

FPGA Implementation

(for exapmle: M1 XILINX)

Fig. 2. Schema of PeNCAD system

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<?xml version="1.0" encoding=nISO-8859-2M standalone="yes"?>

<clock>CLOCK</clock>

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</place>

<net>

<arc>

</arc>

<arc>

</arc>

<arc>

</arc>

<arc>

</arc>

</net>

</pnsf3>

Fig. 3. PNSF3 format of Petri net (Fig. 1)

the styling of an XML document by using XSLT, to describe how the document is transformed into another.

Fig. 4. Diagram of method of transformation

Because PNSF3 does not keep information about placement, it is difficult to make XSL file for transformation into SVG, directly. For such a case, a special program should be created to prepare an XSL file.

<ellipse cx="231.424" cy="76.3614" rx="20.5" ry="20.5" style="stroke-width:1;stroke-

opacity:1;stroke:rgb(0,0,0);fill-opacity:0;fill:rgb(0,0,0);opacity:1"/>

</g>

<animateColor attributeName="fill" attributeType="CSS"

values="white;white;white;white;black;black" dur="6s" repeatCount="indefinite"/> </ellipse>

Fig. 5. A part of SVG file

A SVG file [11] can be made in other way, too. In Fig.

4 diagram of method of transformation from a PNSF3 into a SVG file, without preparing an XSL file, is shown. For the conversion a Java application is used. The program generates a dynamic SVG file. The SVG file keeps information about places, transitions, predicates, markings and placement of these elements. Using the option of animation of a dynamic SVG, it is possible to simulate a Petri net. At present stage, simulation of Petri nets without interpretation is made. The next step of research will be studying possibilities of simulation of interpreted Petri nets.

3.3. Analysis

Determining whether a modelled system is live is very important, because a good system should not contain

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events that can never occur. Testing the liveness of Petri nets depends on finding deadlocks and traps and analysing relationship between them [2,5,7].

The presented method of analysis is based on calculation of Horn formulae and prime implicants for an uninterpreted hierarchical Petri net. The analysis of hierarchical Petri nets can be considered as separately analysis of macromodules and macronet.

Petri nets can be represented by special expressions, called characteristic functions. However, in the presented algorithm another symbolic formula is used, i.e. the Horn formula.

The Horn formula is a conjunction of basic Horn formulae. A basic Horn formula (Horn clause) is a disjunction ofliterals, with at most one positive literal. A literal is either a propositional letter P (a positive literal) or the negation /P of a propositional letter P (a negative literal) [4].

A solution of expressions can be considered as:

— presenting all possibilities of solution for a given expression;

— checking, if given expression has any solution — satisfiability (SAT problem).

A Horn formula is satisfiable if all clauses are positive and it means that a Petri net described by this Horn formula is not live. Satisfiability means that as a solution to Horn formula is searching one result only. The “trivial” solutions, it means setting all literals to 0 or to 1, have to be removed, because these results give incorrect solutions [4]. A majority of methods that solve a SAT problem is NP-complete. Testing satisfiability of the Horn formula is complete for the class P of problems solvable in polynomial time [4]. A problem belongs to class P if there exists an algorithm using a polynomial number of steps that can solve the problem.

Firstly, the Horn formula for Petri net (macronet) is prepared. It can be prepared in two ways. It depends on the property trap or deadlock that is checked. These methods are described in [4]. Then, such an expression is solved using Thelen method. If the prepared expression has a solution it means that the Petri net contains a deadlock or trap. Then, it is necessary to check the dependence between them [5]. If a net on this level is not live, then the whole net is not live, either. Otherwise, all macromodules are analysed separately, recursively by means of the same methods as the macronet.

In Fig. 6 prepared Horn formula for Petri net (Fig. 1) is presented.

HF = (/P1vP2) л (P1v/P2v/P3) л (/P1vP3)

Fig. 6. Horn formula for Petri net (Fig. 1)

Horn formula is being solved using the search tree algorithm proposed by Thelen [3,8]. This method is based on generation of all prime implicants for each clause of Horn formula. There is a tree prepared for Horn formula, which is searched using a DFS (Depth First Search) algorithm. The tree can be traversed via three rules [8]. The three Thelen’s rules are used:

R1. an arc is pruned, if its predecessor nodeconjunction contains the complement of the arc-literal

(xi *Xi = 0);

R2. an arc is pruned, ifanother non-expanded arc on

a higher level still exists which has the same arc-literal;

R3. a disjunction is discarded, if it contains a literal which appears also in the predecessor node-conjunction

[3].

Rule R4 about first solution and R5 about “trivial” solution are added:

R4. the tree is searched as long as the first solution is found.

R5. if the solution is “trivial”, it is removed, and the next solution is being searched. It is execution as long as solution is found or the whole tree is being searched.

Thelen’s method has a linear space-complexity for converting a conjunctive form into the sum of all prime implicants.

In Fig. 7 Thelen’s tree for Horn formula (Fig. 6) is shown. Petri net described by such Horn formula is not live, because expression HF has a solution (/P1AP2A/ P3).

Fig. 7. Thelen’s tree for Horn formula (Fig. 1)

3.4. Binary decision diagram-based analysis method

BDD diagram can be described as a rooted, directed, acyclic graph, which has two sink nodes labelled 0 or 1, representing Boolean functions 0 and 1, and non-sink nodes, each labelled with a Boolean variable x [1]. To apply BDDs to a problem domain, the data to be represented must first be encoded as Boolean functions. There are many kinds of BDDs [1]. In the presented method a reduced ordered binary decision diagram (ROBDD) is used. ROBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases.

Similarly, as in a method based on prime implicants, in this method, a Petri net is described by the Horn formula. Then, using ROBDD diagram, Horn formula is solved. Horn formula is represented by conjunction of disjunctions, but for using ROBDD diagram such an expression has to be translated into disjunction of conjunctions. After such a step, ROBDD diagram is prepared for new expressions. Solutions are paths to

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node “ 1 “, but if in such a path all literals are setting to 0 or 1, such a solution is removed.

4. Conclusions and future work

In the paper a system for design logic controllers (PeNCAD) is presented. Using such a system it is possible to model concurrent controllers by interpreted, hierarchical Petri nets. Petri nets are described using XML language (PNSF3). It gives a new possibility of analysis, especially the simulation of such modelled systems. Another advantage of using XML is possibility of exchanging data between different Petri net tools (for example PeNCAD system and Design/CPN).

PNSF3 format represents the structure of Petri nets, only. Existing XML formats for modelling of Petri net are based on their graphical representation that effaces the difference between structure and graphical format of Petri nets.

In the paper two methods of analysis of Petri net are described, too. The methods are based on calculation of Horn formulae. The Horn formulae are solved by means of Thelen’s tree and ROBDD diagram.

Future work will concentrate on storing PNSF3 documents in a database and on a direct transformation from database into other XML format (for example format for SFC net).

5. Acknowledgment

The presented results are financially supported by Polish State Committee for Scientific Research (KBN) (grant no.7T11C00920) and University of Zielona Gora (grant).

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References: 1. Bilinski K.: Application of Petri Nets in parallel controllers design, PhD. Thesis, University of Bristol, Electrical and Electronic Engineering Department, Bristol, 1996. 2.Best E., Fernandez C.: Notations and terminology on Petri net theory, Petri Net Newsletter, 1986. 3. Mathony H.J. : Universal logic design algorithm and its application the synthesis of two-level switching circuits, IEE Proceedings, Vol.136, Pt.E, No.3. 1989. 4. Minoux M, Barkaoui K. : Deadlocks and traps in Petri nets as a Horn-satisfability solutions and some related polynomially solvable problems. Discrete Applied Mathematics, Elsevier Science Publishers (North Holland), 1990. Vol.29. P.195-210. 5. Murata T.: Petri Nets: Properties, Analysis and Applications, Proceedings of the IEEE, Vol.77, No.4, April 1989. P.541-580. 6.LyngsuiR.B., Mailund T., Textual Interchange Format for High-Level Petri Nets, Workshop on Practical Use of Coloured Petri Nets and Design, June 1998, Aarhus University. P. 47-64. 7.Peterson J.L. Petri Net Theory and The Modeling of Systems, Prentice-Hall, Inc., Englewood Cliffs, N.J., 1981. 8. Thelen B.: Investigations of algorithms for computer-aided logic design of digital circuits, (in German), PhD d issertation, ITIV, Univ. of Karlsruhe, 1988. 9. Wegrzyn A., Bubacz P., “XML application for modelLing and simulation of concurrent controllers”, DESDes2001, Przytok, June 2001, P.215-221. 10. Extensible Markup Language (XML) 1.0. W3C Recommendation http: // www.w3.org. 11.Scalable Vector Graphics (SVG) 1.0 W3C Candidate Recommendation http://www.w3.org.

Поступила в редколлегию 31.10.2001

Рецензент: д-р техн. наук, проф. Хаханов В.И.

Wegrzyn Agnieszka, M.Sc., lecturer at University of Zielona Gora. Interested in: Petri net, databases, DBMS, Internet applications. Address: Computer Eng. and Electronics Institute, University of Zielona Gora, ul. Podgorna, 50, 65-246 Zielona Gora, Poland.

E-mail: A.Wegrzyn@iie.pz.zgora.pl. Ph.: (+48 68) 3282 484.

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Concurrent controller design by means of high-level Petri nets Текст научной статьи по специальности «Компьютерные и информационные науки»

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