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11Applying the method on enlargement of schema
elements for reducing the time, necessary for
functional simulation of schemas with inverse
connection
A. Grigoryan (asya1976@mail.ru) State Engineering University of Armenia
Introduction
Contemporary integral schemas contain numerous elements. According to relevant statistical data, sizes (i.e. the number of elements) of integral schemas are doubled (according to Mour's law) in every 18 months. Under these circumstances, both conciseness of schema description and simulation speed have a supreme importance. In order to address these issues the following actions are suggested:
1. As a schema description language, it is used Alex language [1-4]. Currently as a language for description of apparatuses are widely used Verilog HDL [5] and VHDL [6]. Together with the indisputable advantages (i.e. easy adaptation to schema design, etc), these languages have a number of important disadvantages. In particular, they describe schemas inefficiently (i.e. description sizes are approximately double than optimal one). Unlike the languages above, Alex is the most optimal one, since the record length (the number of symbols) equals to the number of schema graph edges (if schema elements are considered as graph vertexes, and connections between them are considereed as graph edges). Another advantage of Alex language (in comparison with Verilog HDL and VHDL) is the fact that simulation for schemas by Alex is fulfilled by one "review" of schema record (practically without additional searching work), which provides significant simulation speed.
2. In order to reduce the number of schema elements and increase schema simulation time, the method on enlargement of schema elements is developed in this paper. Proceeding from the relevant experience, it can be stated that modern integral schemas contain repeatedly found subschemas, differing from each other just by inputs. Replacement of such subschemas by one element is the main idea of the method on enlargement of schema elements. This paper is based on the description of the method above.
1. Schema simulation
Assume, schema S has x1,_,xn inputs and y1,^,ym outputs. The procedure of finding output values of schema (if a1,_,an schema inputs are known) is considered schema simulation. Simulation of combinational schemas is performed by applying the following procedures to schema record (in any order):
1) fn) a1_ an segment is replaced by value of function f(a1,_ ,an)
2) Mi(1)a and Mi(0) are replaced by a.
The outputs are obtained as a result of applying the procedure above.
After a simple modification, above procedures for simulation of combinational schemas could be applied also for schemas with inverse connections. Schemas with inverse connections are the main subject of this paper. In [4] an algorithm on converting the description of schema with inverse connection to description of combination schema is described. It should be mentioned that after applying this algorithm, the number of inputs and outputs is increased by k, where k is the number of flipflop (storage) elements of schema.
2. Description of the method on enlargement of schema elements
Based on the relevant experience, it could be stated that the time of schema simulation is directly proportional to the number of symbols in schema description. Consequently for reducing this time it is expedient to find a way to decrease the description sizes without affecting the functional concept. In most cases this problem can be efficiently sorted out by enlargement of schema elements.
This method could be done by applying sequentially the following three procedures:
1) To factorize schema description by labels level;
2) To find structurally identical subschemas, differing from each other (in some cases) just by inputs and to replace them by one new element;
3) To estimate and save in a table all outputs for all 2n set of (a1,_,an) of new element, where n is the number of the element inputs.
After applying the method on enlargement of schema elements, schema simulation time is reduced due to the following factors. In first, the values of frequently found selections are not calculated every time but they are taken from tables created in advance; i.e., in the beginning, a table for 2n set of (a1,_,an) enlarged element is created and in future values of this element are not calculated again but are taken from a relevant table. In second, the simulation time is decreased due to decreasing the schema description sizes.
The method on enlargement of schema elements has been tested by pattern of schemas with inverse connection ISCAS89. The results of the relevant experiment are presented in the Table below, where N1 is the number of symbols in schema record before applying the method, N2 is the number of symbols in schema record after applying the method, t1 is the schema simulation time before applying the method (100 random sets), t2 is the schema simulation time before applying the method (100 random sets).
Table - Analyzing the data before and after applying the method on enlargement of elements.
Название N1 N2 ti t2 N соращ. % t соращ. %
c349_bench 354 233 0,95 0,55 34,18 42,1
c400 bench 421 331 1,15 0,85 21,38 26,09
c444 bench 465 382 1,25 0,85 17,85 32
c526 bench 547 526 1,35 1,25 3,83 7,41
c641 bench 658 472 1,85 1,25 28,27 27,03
c713 bench 732 528 2,05 1,35 27,87 34,15
c832 bench 820 810 2,1 2,05 1,22 2,38
c1423 bench 1497 1005 4,9 2,5 32,87 48,98
In order to demonstrate the efficiency of the method on enlargement of elements, a recording the schema s349_bench by Alex language is presented before and after applying this method. Before applying the mentioned method schema s349_bench was as follows:
# 9 inputs
# 11 outputs
# 15 D-type flipflops
# 57 inverters
# 104 gates (44 ANDs + 19 NANDs + 10 ORs + 31 NORs)
NOR(2)NOT(1)M_CT2(1)Y_CT2(0)M_CNTVCON1(0)NAND(2)M_CT2(0)NOR(2)NOT(1)M_CT1(0)M_ CNTVCON0(0)M_READY(0)M_P0(1)NOT(1)Y_MRVQN0(0)M_P1(0)M_P2(0)M_P3(0)M_P4(0)M_P5(0) M_P6(0)M_P7(0)Y_CT2(1)NOR(2)NAND(2)OR(2)M_CT2(0)M_CNTVG3VD1(1)NOR(2)M_READY(1) NOT(1)M_READYN(1)NAND(3)M_CT0(1)Y_CT0(0)NOT(1)M_CT1(1)Y_CT1(0)M_CT2(0)M_CNTVC ON1(1)NAND(2)M_CT 1 (0)NOT(1)NOT(1)M_CT0(0)NAND(2)M_CT2(0)M_CNTVG3VD 1(0)X_START(
0)Y_MRVQN0(1)NOR(2)AND(2)M_MRVSHLDN(1)NOT(1)M_ADSH(1)NOR(2)M_READY(0)M_INIT(
1)NOR(3)M_CT0(0)M_CT1(0)M_CT2(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(1)NOT(1)M_REA DYN(0)X_B0(0)AND(2)M_BMVS0N(0)M_P0(0)AND(2)M_ADSH(0)M_P1(1)NOT(1)Y_MRVQN1(0)Y_ CT0(1)NOR(2)NAND(2)OR(2)M_CT0(0)M_CNTVG1VD1(1)NOT(1)M_READY(0)NAND(2)M_CT0(0) M_CNTVG1VD1(0)X_START(0)Y_CT1(1)NOR(2)NAND(2)OR(2)M_CT1(0)M_CNTVG2VD1(1)NOR(2 )M_READY(0)M_CNTVCON0(1)NOT(1)M_CT0(0)NAND(2)M_CT 1(0)M_CNTVG2VD 1(0)X_START(0 )Y_MRVQN1(1)NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B1 (0)AND(2)M_BMVS0N(0)M_P1(0)AND(2)M_ADSH(0)M_P2(1)NOT(1)Y_MRVQN2(0)Y_MRVQN2(1) NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B2(0)AND(2)M_B MVS0N(0)M_P2(0)AND(2)M_ADSH(0)M_P3(1)NOT(1)Y_MRVQN3(0)Y_MRVQN3(1)NOR(2)AND(2) M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B3(0)AND(2)M_BMVS0N(0)M_P3
(0)AND(2)M_ADSH(0)NOT(1)NAND(2)OR(2)M_AD0(1)NOT(1)NAND(2)M_P0(0)M_AX0(1)Y_AX0(0) M_P4(1)NOT(1)Y_ACVQN0(0)M_ADDVG1VCN(0)Y_AX0(1)NOT(1)NOR(2)AND(2)NOT(1)M_AMVS 0N(1)NOT(1)M_INIT(0)X_A0(0)AND(2)M_AMVS0N(0)M_AX0(0)Y_ACVQN0(1)NAND(2)M_ACVPC N(1)NOT(1)X_START(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(1)NOT(1)M_ADSH(0)NOT(1)NO R(2)AND(3)M_ADDVC1(1)NOT(1)M_ADDVG1VCN(1)NAND(2)M_AD0(0)M_P4(0)M_AD1(1)NOT(1) NAND(2)M_P0(0)M_AX1(1)Y_AX1(0)M_P5(1)NOT(1)Y_ACVQN1(0)AND(2)OR(3)M_ADDVC1(0)M_ AD1(0)M_P5(0)M_ADDVG2VCN(0)AND(2)M_SMVS0N(0)M_P4(0)Y_AX1(1)NOT(1)NOR(2)AND(2)N OT(1)M_AMVS0N(0)X_A1(0)AND(2)M_AMVS0N(0)M_AX1(0)Y_ACVQN1(1)NAND(2)M_ACVPCN(
0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)NOR(2)AND(3)M_ADDVC2(1)NOT(1)M_ADD VG2VCN(1)NOR(2)AND(2)M_ADDVC1 (0)OR(2)M_AD 1(0)M_P5(0)AND(2)M_AD1 (0)M_P5(0)M_AD2
(1)NOT(1)NAND(2)M_P0(0)M_AX2(1)Y_AX2(0)M_P6(1)NOT(1)Y_ACVQN2(0)AND(2)OR(3)M_ADD VC2(0)M_AD2(0)M_P6(0)M_ADDVG3VCN(0)AND(2)M_SMVS0N(0)M_P5(0)Y_AX2(1)NOT(1)NOR(2 )AND(2)NOT(1)M_AMVS0N(0)X_A2(0)AND(2)M_AMVS0N(0)M_AX2(0)Y_ACVQN2(1)NAND(2)M_ ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)NOR(2)AND(3)M_ADDVC3(1)NOT(
1)M_ADDVG3VCN(1)NOR(2)AND(2)M_ADDVC2(0)OR(2)M_AD2(0)M_P6(0)AND(2)M_AD2(0)M_P6 (0)M_AD3(1)NOT(1)NAND(2)M_P0(0)M_AX3(1)Y_AX3(0)M_P7(1)NOT(1)Y_ACVQN3(0)AND(2)OR( 3)M_ADDVC3(0)M_AD3(0)M_P7(0)M_ADDVG4VCN(0)AND(2)M_SMVS0N(0)M_P6(0)Y_AX3(1)NO T(1)NOR(2)AND(2)NOT(1)M_AMVS0N(0)X_A3(0)AND(2)M_AMVS0N(0)M_AX3(0)Y_ACVQN3(1)N AND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)M_ADDVG4VCN(1)NOR(
2)AND(2)M_ADDVC3(0)OR(2)M_AD3(0)M_P7(0)AND(2)M_AD3(0)M_P7(0)AND(2)M_SMVS0N(0)M
_P7(0).
Further, breaking down schema s349_bench according to label levels, the following description is obtained:
CNTVCO2=NOR(2)NOT(1)M_CT2(0)M_CNTVCON1(0) CNTVCON2=NAND(2)M_CT2(0)NOR(2)NOT(1)M_CT1(0)M_CNTVCON0(0)
ready=m_ready(o)
P0=M_P0(0) P1=M_P1(o) P2=M_P2(0) P3=M_P3(o) P4=M_P4(0) P5=M_P5(o) P6=M_P6(o) P7=M_P7(0)
Y_CT2=NOR(2)NAND(2)OR(2)M_CT2(0)M_CNTVG3VD1(0)NAND(2)M_CT2(0)M_CNTVG3VD1(0)X _START(0)
Y_MRVQN0=NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B0(0) AND(2)M_BMVS0N(0)M_P0(0)AND(2)M_ADSH(0)M_P1(0)
Y_CT0=NOR(2)NAND(2)OR(2)M_CT0(0)M_CNTVG1VD1(0)NAND(2)M_CT0(0)M_CNTVG1VD1(0)X _START(0)
Y_CT 1=NOR(2)NAND(2)OR(2)M_CT1(0)M_CNTVG2VD1(0)NAND(2)M_CT1 (0)M_CNTVG2VD 1(0)X _START(0)
Y_MRVQN1=NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B1(0) AND(2)M_BMVS0N(0)M_P1(0)AND(2)M_ADSH(0)M_P2(0)
Y_MRVQN2=NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B2(0) AND(2)M_BMVS0N(0)M_P2(0)AND(2)M_ADSH(0)M_P3(0)
Y_MRVQN3=NOR(2)AND(2)M_MRVSHLDN(0)NOT(1)NOR(2)AND(2)NOT(1)M_BMVS0N(0)X_B3(0)
AND(2)M_BMVS0N(0)M_P3(0)AND(2)M_ADSH(0)NOT(1)NAND(2)OR(2)M_AD0(0)M_P4(0)M_ADD
VG1VCN(0)
Y_AX0= NOT(1)NOR(2)AND(2)NOT(1)M_AMVS0N(0)X_A0(0)AND(2)M_AMVS0N(0)M_AX0(0) Y_ACVQN0=NAND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)NOR(2)AN D(3)M_ADDVC1(0)M_AD1(0)M_P5(0)AND(2)OR(3)M_ADDVC1(0)M_AD1(0)M_P5(0)M_ADDVG2V CN(0)AND(2)M_SMVS0N(0)M_P4(0)
Y_AX1= NOT(1)NOR(2)AND(2)NOT(1)M_AMVS0N(0)X_A1(0)AND(2)M_AMVS0N(0)M_AX1(0) Y_ACVQN1=NAND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)NOR(2)AN D(3)M_ADDVC2(0)M_AD2(0)M_P6(0)AND(2)OR(3)M_ADDVC2(0)M_AD2(0)M_P6(0)M_ADDVG3V CN(0)AND(2)M_SMVS0N(0)M_P5(0)
Y_AX2=NOT(1)NOR(2)AND(2)NOT(1)M_AMVS0N(0)X_A2(0)AND(2)M_AMVS0N(0)M_AX2(0) Y_ACVQN2=NAND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)NOR(2)AN D(3)M_ADDVC3(0)M_AD3(0)M_P7(0)AND(2)OR(3)M_ADDVC3(0)M_AD3(0)M_P7(0)M_ADDVG4V CN(0)AND(2)M_SMVS0N(0)M_P6(0)
Y_AX3=NOT(1)NOR(2)AND(2)NOT(1)M_AMVS0N(0)X_A3(0)AND(2)M_AMVS0N(0)M_AX3(0)
Y_ACVQN3=NAND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)NOT(1)M_ADDV
G4VCN(0)AND(2)M_SMVS0N(0)M_P7(0)
//******* LEVEL 1 *********
M_CT2=Y_CT2(0)
M_P0=NOT(1)Y_MRVQN0(0)
M_CNTVG3VD1=NOR(2)M_READY(0)M_CNTVCON1(0)
M_MRVSHLDN=NOT(1)M_ADSH(0)
M_BMVS0N=NOT(1)M_READYN(0)
M_P1 =NOT(1)Y_MRVQN 1(0)
M_CNTVG1VD1=NOT(1)M_READY(0)
M_CNTVG2VD1=N0R(2)M_READY(0)M_CNTVC0N0(0)
M_P2=NOT(1)Y_MRVQN2(0)
M_P3 =NOT(1)Y_MRVQN3(0)
M_AD0=NOT(1)NAND(2)M_P0(0)M_AX0(0)
M_P4=NOT(1)Y_ACVQN0(0)
M_AMVS0N=NOT(1)M_INIT(0)
M_ACVPCN=NOT(1)x_START(0)
M_SMVS0N=NOT(1)M_ADSH(0)
M_ADDVC1=NOT(1)M_ADDVG1VCN(0)
M_AD 1=NOT(1)NAND(2)M_P0(0)M_AX 1 (0)
M_P5=NOT(1)Y_ACVQN1(0)
M_ADDVC2=NOT(1)M_ADDVG2VCN(0)
M_AD2=NOT(1)NAND(2)M_P0(0)M_AX2(0)
M_P6=NOT(1)Y_ACVQN2(0)
M_ADDVC3=NOT(1)M_ADDVG3VCN(0)
M_AD3=NOT(1)NAND(2)M_P0(0)M_AX3(0)
M_P7=NOT(1)Y_ACVQN3(0)
M_ADDVG4VCN=NOR(2)AND(2)M_ADDVC3(0)OR(2)M_AD3(0)M_P7(0)AND(2)M_AD3(0)M_P7(0)
//******* LEVEL 2 ********* M_READY=NOT(1)M_READYN(0)
M_CNTVCON1=NAND(2)M_CT1(0)NOT(1)NOT(1)M_CT0(0)
M_ADSH=NOR(2)M_READY(0)M_INIT(0)
M_CNTVCON0=NOT(1)M_CT0(0)
M_AX0=Y_AX0(0)
M_ADDVG1VCN=NAND(2)M_AD0(0)M_P4(0) M_AX 1=Y_AX 1(0)
M_ADDVG2VCN=NOR(2)AND(2)M_ADDVC1(0)OR(2)M_AD 1(0)M_P5(0)AND(2)M_AD1(0)M_P5(0) M_AX2=Y_AX2(0)
M_ADDVG3VCN=NOR(2)AND(2)M_ADDVC2(0)OR(2)M_AD2(0)M_P6(0)AND(2)M_AD2(0)M_P6(0) M_AX3=Y_AX3(0)
//******* LEVEL 3 *********
M_READYN=NAND(3)M_CT0(0)NOT(1)M_CT 1(0)M_CT2(0) M_INIT=NOR(3)M_CT0(0)M_CT1(0)M_CT2(0)
//******* LEVEL 4 *********
M_CT0=Y_CT0(0)
M_CT1=Y_CT1(0)
Finally, after applying the method on enlargement of elements, schema s349_bench obtains the following view:
NOR(2)NOT(1 )M_CT2( 1 )Y_CT2(0)M_CNTVC0N1(0)NAND(2)M_CT2(0)N0R(2)N0T(1 )M_CT1 (0)M_ CNTVC0N0(0)M_READY(0)M_P0(1)N0T(1)Y_MRVQN0(0)M_P1(0)M_P2(0)M_P3(0)M_P4(0)M_P5(0) M_P6(0)M_P7(0)Y_CT2(1)FI1 (3)M_CT2(0)M_CNTVG3VD 1( 1)N0R(2)M_READY(1)N0T(1 )M_READ
YN(1)NAND(3)M_CT0(1)Y_CT0(0)NOT(1)M_CT1(1)Y_CT1(0)M_CT2(0)M_CNTVCON1(1)NAND(2)
M_CT1(0)NOT(1)NOT(1)M_CT0(0)X_START(0)Y_MRVQN0(1)FI2(6)M_MRVSHLDN(1)NOT(1)M_A
DSH(1)NOR(2)M_READY(0)M_INIT(1)NOR(3)M_CT0(0)M_CT1(0)M_CT2(0)M_BMVS0N(1)NOT(1)M
_READYN(0)X_B0(0)M_P0(0)M_ADSH(0)M_P1(1)NOT(1)Y_MRVQN1(0)Y_CT0(1)FI1(3)M_CT0(0)M
_CNTVG1VD 1(1)NOT(1)M_READY(0)X_START(0)Y_CT 1(1)FI1 (3)M_CT 1 (0)M_CNTVG2VD1(1)NOR
(2)M_READY(0)M_CNTVCON0(1)NOT(1)M_CT0(0)X_START(0)Y_MRVQN1(1)FI2(6)M_MRVSHLD
N(0)M_BMVS0N(0)X_B1(0)M_P1(0)M_ADSH(0)M_P2(1)NOT(1)Y_MRVQN2(0)Y_MRVQN2(1)FI2(6)
M_MRVSHLDN(0)M_BMVS0N(0)X_B2(0)M_P2(0)M_ADSH(0)M_P3(1)NOT(1)Y_MRVQN3(0)Y_MR
VQN3(1)NOR(2)AND(2)M_MRVSHLDN(0)FI3(3)M_BMVS0N(0)X_B3(0)M_P3(0)AND(2)M_ADSH(0)
NOT(1)NAND(2)OR(2)M_AD0(1)NOT(1)NAND(2)M_P0(0)M_AX0(1)Y_AX0(0)M_P4(1)NOT(1)Y_AC
VQN0(0)M_ADDVG1VCN(0)Y_AX0(1)FI3(3)M_AMVS0N(1)NOT(1)M_INIT(0)X_A0(0)M_AX0(0)Y_A
CVQN0(1)FI4(7)M_ACVPCN(1)NOT(1)X_START(0)M_SMVS0N(1)NOT(1)M_ADSH(0)M_ADDVC1(1
)NOT(1)M_ADDVG1VCN(1)NAND(2)M_AD0(0)M_P4(0)M_AD1(1)NOT(1)NAND(2)M_P0(0)M_AX1(
1)Y_AX 1(0)M_P5 (1)NOT(1 )Y_ACVQN 1(0)M_ADDVG2VCN(0)M_P4(0)Y_AX1(1)FI3(3 )M_AMVS0N(
0)X_A1(0)M_AX1(0)Y_ACVQN1(1)FI4(7)M_ACVPCN(0)M_SMVS0N(0)M_ADDVC2(1)NOT(1)M_AD
DVG2VCN(1)FI5(3)M_ADDVC1(0)M_AD1(0)M_P5(0)M_AD2(1)NOT(1)NAND(2)M_P0(0)M_AX2(1)Y
_AX2(0)M_P6(1)NOT(1)Y_ACVQN2(0)M_ADDVG3VCN(0)M_P5(0)Y_AX2(1)FI3(3)M_AMVS0N(0)X
_A2(0)M_AX2(0)Y_ACVQN2(1)FI4(7)M_ACVPCN(0)M_SMVS0N(0)M_ADDVC3(1)NOT(1)M_ADDV
G3VCN(1)FI5(3)M_ADDVC2(0)M_AD2(0)M_P6(0)M_AD3(1)NOT(1)NAND(2)M_P0(0)M_AX3(1)Y_A
X3(0)M_P7(1)NOT(1)Y_ACVQN3(0)M_ADDVG4VCN(0)M_P6(0)Y_AX3( 1 )FI3(3)M_AMVS0N(0)X_A
3(0)M_AX3(0)Y_ACVQN3(1)NAND(2)M_ACVPCN(0)NOT(1)NOR(2)AND(2)NOT(1)M_SMVS0N(0)N
OT(1)M_ADDVG4VCN(1)FI5(3)M_ADDVC3(0)M_AD3(0)M_P7(0)AND(2)M_SMVS0N(0)M_P7(0).
The templates mentioned below have been used in the schema, where the inputs are defined by Z_desc(0):
#FI1(3)Z_1(0)Z_2(0)Z_3(0)=NOR(2)NAND(2)OR(2)Z_2(0)Z_1(0)NAND(2)Z_2(0)Z_1(0)Z_3(0) #FI2(6)Z_1(0)Z_2(0)Z_3(0)Z_4(0)Z_5(0)Z_6(0)=NOR(2)AND(2)Z_4(0)NOT(1)NOR(2)AND(2)NOT(1)Z_2(0)Z_3(0
)AND(2)Z_2(0)Z_0(0)AND(2)Z_5(0)Z_1(0) #FI3(3)Z_1(0)Z_2(0)Z_3(0)=NOT(1)NOR(2)AND(2)NOT(1)Z_1(0)Z_2(0)AND(2)Z_1(0)Z_3(0) #FI4(7)Z_1(0)Z_2(0)Z_3(0)Z_4(0)Z_5(0)Z_6(0)Z_7(0)=NAND(2)Z_1(0)NOT(1)NOR(2)AND(2)NOT(1)Z_2(0)NOT
(1)NOR(2)AND(3)Z_3(0)Z_4(0)Z_5(0)AND(2)OR(3)Z_3(0)Z_4(0)Z_5(0)Z_6(0)AND(2)Z_2(0)Z_7(0) #FI5(3)Z_1(0)Z_2(0)Z_3(0)=NOR(2)AND(2)Z_1(0)OR(2)Z_2(0)Z_3(0)AND(2)Z_2(0)Z_3(0)
The above analysis shows that practically in all templates the number of arguments is decreased due to identity of some arguments.
Finally, it should be mentioned that the number of symbols in the description of schema s349_bench has been reduced from 354 to 233.
CONCLUSION
1. The method on enlargement of schema elements has been tested by pattern of schemas with inverse connection ISCAS89. The results of these experiments, presented in the Table, show that after applying the method on enlargement of schema elements the sizes of tested schemas are decreased within 1,22% - 34,18%, and simulation time is decreased within 2,38% - 48,98%.
2. It has been shown that despite the time used for creation of the table for the set of elements, the overall time is reduced, since the relevant tables are created once but simulation is done repeatedly.
LITERATURE
1. Bozoyan Sh. E. Language of functional schemas description// Izv. USSR Academy of Sciences, Technical Cybernetics 4, 1978.
2. Bozoyan Sh. E. Adaptation of Lukasevich's language to description of functional schemas// AS Arm. SSR, v 63, 4, 1979.
3. Bozoyan Sh. E, Yeghiazaryan V. S. Some procedures on logical schemas and implementation of them by Alex language.-0nline journal «Researched in Russia», http://zhurnal.ape.relarn.ru/2003/073.pdf , p.817-824.
4. Bozoyan Sh. E., Yegiazaryan V. S. New solution for module-oriented design of systems based on chips - 0nline journal «Researched in Russia», http://zhurnal.ape.relarn.ru/2003/115.pdf , p.1386-1395.
5. S.Palnitkar. Verilog HDL: A Guide to Digital Design and Synthesis. SunSoftPress. Prentice Hall, 1996.
6. Marshner F.E. VHDL for simulation, synthesis and formal verification of apparatuses. M., 1995, p. 1-13
