A Programmable Built-in Self-diagnosis Methodology with Macro and Micro Codes for Embedded SRAMs Текст научной статьи по специальности «Медицинские технологии»

A Programmable Built-in Self-diagnosis Methodology with Macro and Micro Codes for

Embedded SRAMs

P. Manikandan, Bj0rn B. Larsen, Einar J. Aas , M. Areef

Abstract - Memories are one of the most universal cores that are embedded into almost all system on chips (SoCs). Finding cost effective test solution for embedded memories is paramount. Industries are still improving the existing low cost memory test solutions which can support current technologies and advanced SoC architectures. This paper presents a programmable built-in self-diagnosis (PBISD) methodology with self-test for embedded SRAMs. The BISD logic adapts the test controller with micro code encoding technique in order to control test operation sequences for fault detection. It also encompasses a diagnosis array in order to locate fault sites. The macro codes are used to select any of seven MARCH algorithms, and detect different faults of the memory under test (MUT). This BISD supports the test, diagnosis and normal operation modes. The experimental results show that this work gives 17-47% improved area overhead and 16-41% enhanced speed compared to three published results.

Index Terms - Micro code, Macro code, Self-Test, Diagnosis, Memory test.

I. Introduction

Testing of embedded memories receive growing attention in both industrial and academic researches. Built-in self-test (BIST) of memories is considered as the best solution because of its at-speed test support, on-chip test pattern generation and on-chip response analysis. BIST can also support on-line and off-line tests. On-line BIST has shorter test time but results in area overhead. Off-line BIST employs longer test time but small area overhead. However, area overhead and performance penalty represent two major concerns for SoC testing. Improvements in these measures are extremely important in order to attain high quality testing. Also, the diagnosis of embedded memories is receiving a growing attention in industries [1] while targeting the effective fault analysis, reduced test cost and improved design verification. This diagnosis function is important to reduce the defects per million (DPM) level as well as to help the SRAM design and process engineers to improve the yield during the development stage. Therefore it

Manuscript received July 20, 2012.

Manikandan P. is with Institute of E&T, The Norwegian University of Science and Technology, Trondheim, Norway (corresponding author to provide e-mail: manikandan.palanichamy@iet.ntnu.no).

Bj0rn B. Larsen is with Institute of E&T, The Norwegian University of Science and Technology, Trondheim, Norway

Einar J. Aas is with Institute of E&T, The Norwegian University of Science and Technology, Trondheim, Norway

M. Areef is with Juniper Networks, Bangalore, India

is desirable to have the combination of BIST and selfdiagnosis, such as Built-in self-diagnosis (BISD). This method is the most acceptable solution while locating fault sites of the embedded SRAMs [2-6].

This work combines BIST with a diagnosis array in order to detect the defective memory and its fault location address. It also addresses the improvement of area overhead and performance measures by employing an efficient test controller. This BISD exploits the same macro codes [7-9] for selecting the test algorithm. [7] introduced structured programmable memory BIST (PMBIST) with online programmable capability using “macro command”. In which, the memory BIST (MBIST) controller unit is used to produce the correct sequence of MARCH elements according to the selected test algorithm. In [8], PMBIST employs FSM based algorithm generator and test controller which are used to control MARCH elements and test data. The PMBISTs of [7] and [8] provides simplified macro command based test methods in order to achieve flexibility feature, reduced test time and test data. However, there is an area overhead due to their state machines dependability on certain conditions like last memory address run on the MARCH element and the additional sequence counter. The similar PMBIST approach was stated in [9]. It used the same encoding technique for the MARCH elements but instead of using state machines as in [7] and [8] the test controller was designed using clusters of microcode which controls the read/write operation and test data injection. Also it requires less number of states to perform read and write operations. Thus, an improved performance of the test controller and minimizing the area overhead can be achieved if an efficient coding technique is employed especially in read/write operation FSM. This paper used an efficient encoding technique with dual operation segments (OS1 and OS2) while assigning micro codes to MARCH elements.

Fig. 1.

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Generally, memories are used to store (write operation) and retrieve the data (read operation) by addressing specific memory locations. This basic concept is also used in memory testing as shown in Figure 1. In memory testing, according to the algorithm and fault model there will be consecutive write and read operations of test patterns (0/1) with respect to time. The correct output response will be expected from each memory cell during the read operation.

If the actual output is different from the expected output then it is considered that the memory has defect. MARCH based test techniques are most commonly used in memory test because it is simple and provides good fault coverage [1016]. It supports a sequence of read or write operations that examines the memory either in ascending or descending address order.

Table I.

Fault Detection of MARCH Algorithms

Test Algorithm Description Fault detection saf tf cf

MATS+ {ftft (w0); ft (r0, w1); ft (r1, w0)} Yes No No

MARCH X {ftft (w0); ft (r0, w1); ft (r1, w0); ftft (r0)} Yes Yes Yes

MARCH A {ftft (w0); ft (r0, w1, w0, w1); ft (r1, w0, w1); ft (r1, w0, w1, w0); ft (r0, w1, w0)} Yes Yes Yes

MARCH B {ftft (w0); ft (r0, w1, r1, w0, r0, w1); ft (r1, w0, w1); ft (r1, w0, w1, w0); ft (r0, w1, w0)} Yes Yes Yes

MARCH C- {ftft (w0); ft (r0, w1); ft (r1, w0); ft (r0, w1); ft (r1, w0); ftft (r0)} Yes Yes Yes

MARCH U {ftft (w0); ft (r0, w1, r1, w0); ft (r0, w1), ft (r1, w0, r0, w1), ftft (r0)} Yes Yes Yes

MARCH LR {ftft (w0); ft (r0, w1); ft (r1, w0, r0, w1); ft (r1, w0); ft (r0, w1, r1, w0); ftft (r0)} Yes Yes Yes

SAF - Stuck-At Fault, TF - Transition Fault, CF - Coupling Fault

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Fig. 2. Functional model of RAM chip (a) and reduced functional model (b) [14]

Some of the MARCH based algorithms and their descriptions with fault detection are presented in Table 1, using Van de Goor [14] notation. Refer to Section 2.1, for fault definitions. in Table 1, (i) w0 and w1 represents writing 0 and 1 into a cell, (ii) r0 and r1 represents reading 0 and 1 from a cell, respectively. ft and ft denotes memory address order increment and decrement, respectively. ftft denotes either memory address order increment or decrement and the description shows the algorithm steps. Generally, MARCH based test algorithms supports a sequence of read or write operations that examines the memory either in ascending or descending memory address order. For example in MARCH C- algorithm with m words x n bits memory under test, the algorithm begins writing 0s from location 0x0 with

ascending address order increment. The write operation continues until it reaches the last bit of the memory array or mxn. Then it reads 0s from the memory array in ascending order and checks whether the same data (0s) is available or not. Next, it changes the content of every cell by 1 and then reads back the same data in ascending order. This read operation expects 1s from every cell of the memory array. Again the write operation writes 0s into all memory cells in ascending order. Similarly, the same test operation repeats in descending order as shown in the description of MARCH C-algorithm in Table i. in this paper we consider Static RAM with flexible test features. This programmable memory BISD (PMBISD) technique supports seven MARCH test algorithms, and the number was chosen in order to make a

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fair comparison with existing works [7-8]. The algorithms were chosen based on their effectiveness, fault coverage and industry test results analysis [17].

The rest of the paper is organized as follows. Section II shows the overview of memory and its fault distribution with summary of different test algorithm types. Section III introduces the architecture of PMBISD with macro and micro codes. Section IV describes the details of the functional flow and diagnosis array. Section V illustrates the experimental results. Section VI concludes this work. Finally, Section VII gives discussions and future directions.

II. Overview of MBIST

Figure 2(a) shows the general model of an SRAM chip. The simplified functional model of the SRAM chip is also given in Figure 2(b) [14], including the control line which provides the clock signal to control the timing behavior of read/write operations. As indicated in Figure 2(a), the address latch contains the current address. The higher order bits of address are connected to the row decoder which is used to select a row and the lower order address bits are connected to the column decoder which is used to select the required columns in the memory array. In the memory array, several adjacent memory cells are connected to form a single word line. The number of adjacent cells depends on the data width of the chip since each cell corresponds to a single bit operation. Several word lines are connected to form a memory array. During the write operation, the write enable signal is active and therefore the data is written into memory through the write drivers and bit lines. Similarly, during the read operation the read enable signal is active. Here the data of the selected cells can be read from the memory through sense amplifiers. The data-in and data-out lines are used to transfer the data between memory and external world. These lines are bidirectional, thus reducing the number of pins of the chip. The testing target is to detect the occurrence of different faults in the memory array or peripheral circuits. The possible faults and their distribution among the memory

2.1

Fig. 3. Memory Faults Distribution [17] Fault Distribution

The functional faults of memory can be classified into four categories [14]. In the first category, faults involving only in a single cell are placed. For example (i) Single-cell

stuck-at fault (SAF) - the cell contains 0 instead of 1 (SA0) or 1 instead of 0 (SA1), and it remains at the same value. (ii) Transition fault (TF) - the cell cannot go through 0 to 1 or 1 to 0 transitions. In the second category, there are faults in which two cells are involved. For example, coupling faults (CF) - the victim (coupled cell) is forced to 0 or 1 when the aggressor (coupling cell) updates its values to 0 or 1. In the third category, there are faults in which k cells are involved. For example the k-coupling, the bridging and the state coupling faults. The bridging and state coupling faults are special cases of the general coupling fault model. Fourth, and the last category is accommodating faults that are the neighborhood pattern sensitive faults. In addition to the faults mentioned in [14] and Table I, there are also some other complex fault models like linked faults (LF) [20] and dynamic faults (DF) [21] considered by researchers. Faults requiring more than one operation sequentially in order to be sensitized are called dynamic faults and linked faults are faults that influence the behavior of each other. M. Linder et al [17] analyzed and summarized the distribution of complex memory faults in addition with basic faults along the chip. The data from [17] is shown here to give an idea to readers about different types of faults distribution along the chip (Figure 3) and the fault coverage values of different MARCH like algorithms (Figure 4) based on the industry test results and its credits will go to corresponding authors. In Figure 3, the amount of all coupling faults is about 50%. It includes some coupling faults - 22% detected by type II, and remaining coupling faults - 28% detected by type III algorithms of Table II. Then the basic single cell faults are 34% and complex memory faults (LF and DF) results 16% in the total faults distribution. These complex faults can be only detected by some specific algorithms such as MARCH AB, MARCH LR and MARCH LA.

2.2 Fault Detecting Algorithms

Functional test algorithms are targeting defects between memory cells, or within a single memory cell by applying test patterns, and performing output response analysis. These test algorithms basically write 1s or 0s into all memory cells in order to detect individual cell defects. As shown in Section 1, MARCH-like algorithms begin by writing a background of zeros. Then it reads the data at the first location and writes a 1 to that address. It continues the read/write procedure consecutively until the last address is reached. The test is then repeated for different read/write sequences according to the algorithm. The test length is of order N, where N is the number of words in the memory [18]. These algorithms can find cell opens; shorts; address uniqueness; and some cell interactions. Some early algorithms considered faults only related to simple static type [14], [19], whereas a few recent algorithms are covering other and complex faults like linked or dynamic faults [20], [21]. [17] groups the algorithms into five types/sets as shown in Table II. It also demonstrates the effectiveness of different memory test algorithms based on a comprehensive analysis of empirical test results as given in Figure 4. This analysis helps to optimize the selection of memory test algorithms with respect to their efficiency. An effective selection of test

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algorithms leads to high quality test with low test time. However, this work considered only few efficient MARCH based algorithms from Figure 4. The chosen algorithms are mainly from Type II, III and IV of Table II as given in Table I. The reader may refer to the source for analyses of different memory test algorithms.

III. Architecture of PMBISD

The I/O port model of the PMBISD is shown in Figure 5. This BISD scheme can support seven test algorithms as shown in Table 1 which includes the basic test algorithms (MATS+, MARCH X, MARCH A, MARCH B, MARCH C-) plus the advanced memory test algorithms (MARCH U and MARCH LR). This number of algorithms was considered in order to make a fair comparison with earlier

programmable BIST with macro codes. 3-bit Macro codes

(MaC) 000, 001, 010____110 are assigned to the algorithms

MATS+, MARCH X .... MARCH LR, respectively. In this model, test_h is used to select either operation mode such as normal operation (NO) or test operation (TO). Similarly, test_d is used to enable diagnosis operation of the BISD circuit. The hold signal is used to stop the BIST operation during the test mode and keep the current data / address when required. Clk is the memory BISD clock signal. During the BIST operation, if any memory defect is detected then fail_h goes high. At the completion of the BIST operation, tst_done signal goes from low to high and the diagnosis operation results in the faulty address and data through scan_out, AO_mem and DO_mem.

Table II.

Fault Detection Capability of Different Algorithms

Detecting Faults

Type Source Algorithms SS CF LF DF

I [14], [19] Scan, Scan+ Yes - - -

II [14], [18], [22] MATS, MATS+, MATS++, MARCH X, MARCH C-, MARCH Y, PMOVI, MARCH 1/0, MARCH TP, MARCH C+, MARCH A, MARCH B and MARCH SS Yes Yes - -

III [23], [24], [25] Algorithm B, MARCH U, MARCH SR Yes Yes - -

IV [26], [27] [21], [28], [29], MARCH LA, MARCH LR Yes Yes Yes -

V [30], [31] MARCH RAW, MARCH AB, MARCH BDN, Hammer 5R, MARCH G Yes Yes Yes Yes

SS - Static Single-cell Fault, CF - Coupling Fault, LF - Linked Fault, DF - Dynamic Fault

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Algorithms

Fig. 4. Effectiveness of Memory Test Algorithms [17]

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A simplified architecture of PBISD is given in Figure 6 with their internal signal flow. The internal signal descriptions are given in Table III. The memory to be tested is showed in the shaded background. The test circuitry is composed of an algorithm selector, address decoder, test controller, test pattern generator and diagnosis array. The test set-up also consists of the comparator in order to evaluate the acquired data of MUT.

Fig. 5. I/O Port Model of PMBISD

MaC test_h (TO/NO) test_d

Fig. 6. Architecture of BISD

3.1 Algorithm Selector and Test Controller This BIST design can be programmed on-line using Macro commands in which the algorithm selector is used to select the test algorithm through 3-bit macro codes. Each MARCH algorithm has a sequence of MARCH elements (ME) which can be encoded into 4 bits micro opcode as shown in Figure 7. It uses 11 MEs to represent seven algorithms. The given opcode in Figure 7 is not including the address direction bit. Algorithm selector gives the encoded MARCH elements (EME) of the selected algorithm to the test controller as well as the address sequence micro code (AMC) signal to the address decoder. The test controller is using two operation segments (OS1 and OS2) while assigning micro codes to the MARCH elements. Each MARCH element has different number of operation sequences and they can be encoded into OS1 and OS2. According to the algorithm execution the MARCH elements are encoded into either single operation or double operation segments. Then the corresponding micro code instructions (MCI) through the test pattern generator are used to control read/write operation sequences.

Fig. 7. Micro op-codes with MARCH Elements and Operation Segments

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Test Operation Sequences

While implementing ME8 this work results r0, w1 into

051 and r1, w0, r0, w1 into OS2. There are 4 operations in a single segment (OS2). For this same problem, [9] encoded ME8 into triple clusters (Cluster 1, Cluster 2 and Cluster 3). Each cluster can support single or double read/write operations. For instance, each cluster is encoded into three individual MARCH elements 9, 11 and 12. Again, MARCH element 9 has two dual operation clusters and each element of 11 and 12 has two dual operation clusters and one single operation cluster. The method in [9] needs micro code instructions to control 14 read/write operations. But this work used only double operation segments in order to increase the speed while assigning micro codes to the respective MARCH elements. We programmed to encode

052 of ME8 into 1010 without affecting the operation sequences of test algorithms. It needs three operation segments and its corresponding micro code instructions are used to control only 6 read/write operations. When the test controller completes the encoding process, it gives the end of operation encoding (EOE) signal to the address decoder. The address decoder gives Activate signal to the algorithm selector in order to indicate that the test controller is ready to receive the next MARCH element.

Table III.

Internal Signals Description

Internal Signals Description

EME Encoded MARCH Element

AME Address Micro Code

EOE End of Encoding Operation

MCI Micro Code Instructions

EPM End of the process of MCI

R\W ES Read/Write Enable Signals

TO Test Operation

NO Normal Operation

TD Test Data

AD Acquired Data

A&D Address & Data

FDI Fault Detection Information

SOE Scan out Enable

3.2 Test Pattern Generator and R/W Control

During the BIST operation, the test controller is used to control read/write operations in MUT. It provides micro code instructions (MCI) to the test pattern generator in order to control the test data sequences and address order increment/decrement. Then the test pattern generator decodes these MCIs and gives read/write enable (R/W ES) signals and test data (TD) to the MUT with operation sequences. When the operation reaches the last address and at the end of read/write operation encoding, the test pattern generator gives end of the process of micro code instructions (EPM) to the address decoder and also ready signal to the test controller. The increment/decrement of the addressing order is achieved by a direction bit together with appropriate micro code.

In test mode, the generated test data (TD) by the test circuitry is applied to the SRAM, and according to the test algorithm MUT will be examined by the corresponding operation sequences. The acquired data (AD) of MUT will be compared with the actual data in a comparator. If the

comparison results in mismatch, then it indicates a defective memory. Then the signal fail_h goes high. Fault detection information (FDI) and scan-out enable (SOE) signals are bridging the built-in self-test controller and diagnosis array. In diagnosis mode, the scan_out signal gives the faulty memory address (AO_mem) and the faulty memory data (DO_mem) at the output. The functional flow with diagnosis operation is described in the next section. However, the test controller of this BISD provides less area overhead due to the absence of the sequence counter. It also provides improved speed due to its double operation segments with efficient reuse of MARCH elements. As well as this micro code encoding technique is not depending on the last address insertion.

IV. Functional Flow and Analysis

The input ports, test_h and test_d are used to select the functional mode of the BISD. This BISD scheme supports four different modes such as normal operation, BIST/test operation, diagnosis operation and hold operation. The functional flow of the BISD is illustrated in Figure 8.

4.1 Functional Flow Chart

As shown in Figure 8, the operation begins by asserting test_h signal to either low or high. When test_h=0, it starts the normal operation (mode 1) and test_h=1 enable the BIST operation (mode 2). If there is fault detection then fail_h signal goes high and at the end of the BIST operation tst_done signals goes high. However, by asserting test_d signal to high the diagnosis operation (mode 3) starts. Diagnosis operation mode enables the shifting out of address and data signals of the failed location of the memory. The scan_out signal is active in this mode and it scan out the faulty address and data from memory. The BIST operation continues the testing process while the active test_d signal scan out the faulty site data. During BIST and diagnosis operations hold signal keeps logic 1. If we assign logic 0 to hold signal, it stops the operation and hold the current address and data.

Diagnosis

Diagnosis operation is used to identify the faulty site of the MUT. For this purpose the test circuit adapts the diagnosis array with shift counter and diagnosis fields as shown in Figure 9. The three diagnosis fields (DFs) are corresponding to the faulty address (FA), faulty data (FD) and faulty pulses (FP). When test_d signal is active the diagnosis array receives fault detection information (FDI) from the test circuit. Then the diagnosis array gives scan out enable (SOE) to the BIST circuit and activates the scan_out signal. When a faulty word is detected in MUT, it transfers the corresponding faulty address and data to the output ports (AO_mem and DO_mem) through DFs of the diagnosis array. This BISD also gives faulty pulses through fail_h signal. This BISD circuit continues the testing while shifting the faulty address and data. After completing the test process in all addresses of the MUT according to the algorithm the tst_done signal goes high. It indicates the end of the BISD operation.

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Fig. 8. Functional flow of BISD

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The previous PMBIST [7] [8] consists of the sequence counter in the test controller in order to control the read/write operations. Even though our test controller avoids the sequence counter because of an efficient encoding technique of MARCH elements, the shift counter and DFs of the diagnosis array costs additional area overhead. However, the performance and area overhead of our test controller is better than existing PMBISTs and the comparison results are given in the next section. The faulty data output of the BISD helps design engineers to locate the faulty site in a memory array and improve the SRAM design in the early phase of the circuit design. The obtained faulty data can be represented in the form of MARCH signatures in order to analyze the fault location. For example, a MARCH test

detects a faulty cell during the read operations. Also the read out data is available in the output port. If we make the MARCH signature of the consecutive read operations of a memory cell, it helps to analyze the type of fault with fault site. Let us consider a single cell in a word and expect a MARCH signature (correct data) of that particular cell as 01010. After completing the test process if the MARCH signature is 00000 then it concludes the cell failure occurs during the second and fourth read operations. Even though this signature comparison helps to locate the faulty cell in a word, when we consider the large size memory it is reasonable to label the read operations of MARCH tests with fault dictionary. For each fault model we can compare the signature of every faulty cell. Since the fault analysis is not the focus of this paper, the reader may refer more about the concept of fault dictionary, MARCH signatures and memory fault simulator in [32].

IV. Experimental Results

This section shows the experimental results of a programmable MBIST with macro and micro code encoding techniques for a synchronous single port SRAM. In order to show the functional verification of our work, case simulations had been done and results are shown in Figures 10 (a), (b) and (c). In order to have a fair comparison with existing work, Mentor Graphic’s Precision tool has been used to synthesize the test circuit. The results are compared with the previous programmable MBIST test controllers.

Case 1: Fault Free Simulation

Figure 10 shows the simulation waveform of the fault-free SRAM. In which, the BIST mode was enabled by high test_h signal and it also has high hold_l signal. The

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comparator gives match result for fault-free memories and therefore fail_h signal is in logic low status. After completing the BIST operation, tst_done signal goes high, indicating the end of the test mode.

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Fig. 10. Case 1 - Fault Free Simulation

Case 2: Fault Simulation

Figure 11 shows the simulation waveform of the faulty SRAM. In this case simulation, MARCH C- algorithm was executed. The SRAM model is also modified to be in defective state by inserting single-cell faults. The BIST mode was enabled by high test_h signal and also it has high hold_l signal. The comparator gives mismatch result in the faulty locations. Therefore the fault detect waveform fail_h gives high pulses when faults are detected.

Synthesized Results

This PMBIST was synthesized for two different number of test algorithms such as six (6A) and seven algorithms (7A) with adapted test controller. Noor [9] synthesized PMBIST test controllers and showed the test results in terms of logic elements (LE). For the comparison, the synthesized results of our BIST controller in terms of logic elements (LE) are shown in Table IV. First, the test setup with 6A achieved improved area overhead and speed which are 1846% and 16-22%, respectively. Similarly, the second case (7A) gives 17-47% improved area overhead and 16-41% improved speed than previous works. Also the time results for BISD that implements all the six and seven test algorithms are 9.11ns and 10.86ns, respectively. This proves that the proposed approach reduces the number of required cycles and it results less execution time than [7] and [8]. In this method, micro-code needed to execute the selected test algorithm is considerably reduced while controlling the test operation sequences. The dual segments technique efficiently utilizes the available MEs. However, when we include more algorithms the complexity of the test controller as well as the number of MARCH elements and its storage requirements will increase. It may result in more area overhead while sacrificing the speed.

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Fig. 11. Case 2 - Fault Simulation

Case 3: Diagnosis Operation

Figure 12 shows the simulation waveform of the diagnosis operation. In this case, test_d signal is high. When the BIST operation finds defect, its corresponding fault data and faulty address are shifted to the output ports Do_mem and Ao_mem, respectively. The fault pulses are indicated by fail_h signal.

In this paper, the programmable BISD architecture and its MARCH test algorithms with operation segment technique ere presented. The experimental results show that this ethod results in 17-47% improved area overhead compared to [7], [8] and [9]. It also has the advantages of improved ^peed, and simple to control test procedure. The diagnosis function is used to identify the faulty location by reading faulty address and faulty data from MuT. This will help the SRAM design and process engineers to improve the circuit and yield during the development stage. However, an efficient reuse of existing MARCH elements will help to add or replace less complex MARCH test algorithms, without the need to redesign the entire circuitry.

VI. Discussions and Future Directions

Area Overhead and Speed Comparison

Area Overhead Speed (MHz)

Source

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Fig. 12. Case 3 - Diagnosis Operation

The flexibility feature of our BISD allows adding more MARCH algorithms with the cost of additional area overhead and performance degradation in the test controller. The cost depends upon the complexity of the newly added algorithm. For example from Table I, let us consider MARCH u and MARCH LR algorithms with the test length of 14n. If either or both algorithms are replaced by MARCH G and/or MARCH RAW with the test length of 23n+2D and 26n respectively, then the complexity of implementing test sequences will also increase. According to the description of MARCH RAW algorithm it requires the test sequences for %1,w1,r1,r1,w0,r0);%0,w0,r0,r0,w1,r1);W(r1,w1,r1,r1,w0, r0). Even though dual segments technique can handle six operations in each ME as shown in ME8, in order to implement this algorithm in the current architecture, the required number of MARCH elements will be increased. This will automatically increase the area overhead and influence the performance of the test controller. In this

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current work, we have chosen the selective algorithms based on two factors which are their efficiency in terms of fault coverage and sequences of MEs where it can be shared efficiently. Therefore, this architecture cannot be applied universally but it is possible to utilize this structure with additional cost. Thus, the existing works differ in a way of using the number of MARCH algorithms and its corresponding MEs, implementation of the test sequences control and micro code encoding technique with improved measures [2-9].

However, when we consider the future directions, it is interesting to note from Figure 4 that the fault coverage is only based on single algorithms. There is not much work about the analysis of combinations of different memory test algorithms (MARCH-like and MARCH-unlike) in a test set. While testing memories, the combination of different test algorithms gives better fault coverage and yield improvement than using a single algorithm. When we use the combination of different algorithms, each algorithm may detect more number of unique faults. The concept of the union and intersection of the fault coverage is used to determine the efficiency of such an algorithms combination [17]. If we consider two algorithms in the combination, the union is the combined fault coverage of both algorithms and the intersection is the number of unique faults that are detected by both algorithms. This is also a challenging task to determine an efficient combination of algorithms with low intersection.

M. Linder [17] discussed about the efficient algorithms combination based on industry test results. For example, MARCH U and Hammer 5R results low intersection in their fault coverage. It means that the number of faults detected by each algorithm is high, but the number of fault detected twice is low. The implementation of such combinations in BISD/BIST will cover different types of memory faults with high fault coverage. Finding efficient combinations of algorithm pairs and their realizations are still open to research in order to cover more complex fault models like dynamic or linked faults, in addition with detecting traditional faults (Single Cell Faults and Coupling Faults).

Acknowledgments

Special thanks to Prof. S. Hamdioui, Delft University of Technology, The Netherlands, for his valuable advice and discussions. This work is supported by the NTNU PhD Research Fellowships in Information Technology, Mathematics and Electrical Engineering IME 082-2007.

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Palanichamy Manikandan received the Diploma in electrical and electronics engineering from Alagappa Polytechic, Tamilnadu, India and Bachelors degree in electronics and communications engineering from Madurai Kamaraj University, Tamilnadu, India, in 2001 and 2004, respectively. He received his Masters degree in electrical engineering from National Cheng Kung University, Tainan, Taiwan in 2007. At present he is working towards his PhD in electronics and telecommunications engineering at the Norwegian University of Science and Technology, Trondheim, Norway.

Mr. Manikandan received IEEE - Best paper awards in 2006 and 2011. He also received Industrial scholar award in 2007. Mr. Manikandan got the diploma award of “IET Ambassador 2011” from NTNU, Norway. He has a research experience from the department of electrical and computer engineering at The University of Iowa, IA, USA and Indian Institute of Technology, Kharagpur, India in 2010 and 2004-2005 respectively. He has published numerous papers in international conferences and journals. He also worked as a Senior system engineer in Hsinchu Science park, Taiwan in 2007-2008. He is working as a research fellow at NTNU, Norway since 2008. He is also the chairman of Region 8, IEEE-SB of Norway section since 2010. His research interests are built-in self test, path delay fault testing, memory test and content addressable memories.

Bjorn B Larsen received his Ph.D. degree from the Norwegian Institute of Technology in 1991. Since 1992, he is working as an associate professor in electronics and telecommunications engineering at the Norwegian University of Science and Technology. His current areas of research include VLSI design, field programmable gate array testing, Design for Testability, Built-in self-test and verification.

Einar Johan Aas received his Ph.D. degree from the Norwegian Institute of Technology in 1972. In 1972, he joined SINTEF (The Foundation for Scientific and Industrial Research). Since 1981 he has been a full professor in Electronic Design Methodology at NTH, now the Norwegian University of Science and Technology. Dr. Aas is author and coauthor of more than 400 technical and scientific publications. His current areas of research include VLSI design, verification and testing. Prof. Aas is Member of the Norwegian Academy of Technological Sciences and The Royal Norwegian Society of Sciences and Letters.

M Areef received his engineering degree in electronics and communications from Madurai kamaraj university, India in 2004. Since 2004, he has a vast work experience in VLSI design and testing from industries - texas instruments, sasken and juniper networks. He had receive IEEE best paper award in 2011.

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