Matrix-Model for Diagnosing SoC HDL-Code Текст научной статьи по специальности «Компьютерные и информационные науки»

Matrix-Model for Diagnosing SoC HDL-Code

Vladimir Hahanov, Senior Member, IEEE , Eugeniya Litvinova, Member, IEEE,

Vladimir Obrizan, Igor Yemelyanov

Abstract — This article describes technology for diagnosis SoC HDL-models, based on transaction graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis.

I. TAB-MODEL FOR DIAGNOSIS FAULTY SoC COMPONENTS

The goal is creation TAB-matrix model (Tests -Assertions - Blocks functional) model and diagnosis method to decrease the time of testing and memory for storage by means of forming ternary relations (test - monitor - functional component) in a single table.

The problems are: 1) development of digital system HDL-model in the form of a transaction graph for diagnosing functional blocks by using assertion set [1-6,15]; 2) development method for analyzing TAB-matrix to detect minimal set of fault blocks [4-7,13]; 3) Synthesis of logic functions for embedded fault diagnosis procedure [8-11,14].

Model for testing a digital system HDL-code is represented by the following xor-relation between the parameters <test - functionality - faulty blocks B*>:

T © B © B* = 0;

B* = T © B = {T x A} © B,

Manuscript received March 14, 2013.

Vladimir Hahanov is with Kharkov National University of Radioelectronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 321 (corresponding author to provide phone: (057)7021326; fax: (057)7021326; e-mail: hahanov@ kture.kharkov.ua).

Eugeniya Litvinova is with Kharkov National University of Radioelectronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 380 (phone: (057)7021421; fax: (057)7021421; e-mail: kiu@

kture.kharkov.ua).

Volodymyr Obrizan is with Kharkov National University of Radio Electronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 319 (e-mail: [email protected]).

Igor Yemelyanov is with Kharkov National University of Radioelectronics, Ukraine, 61166, Kharkov, Lenin Prosp., 14, room 319 (phone: (057)7021326; fax: (057)7021326; e-mail:

[email protected]).

which transformed relationship of the components in the TAB-matrix:

M = {{Tx A}x{B}}, Mjj = (Tx A)i ©Bj.

Here, the coordinate of the matrix is equal to 1, if the pair test-monitor (T x A)i detects or activates some faults of the

functional block Bj є B .

An analytical model for verification by using a temporal assertion (additional observation statements or lines) is focused to achieve the specified diagnosis depth and presented as follows:

Q = f(G,A,B,S,T),

G = (A*B) x S;S = f(T,B);

A = {AbA2,...,Ai,...,Ah};

B = {BbB2,...,Bi,...,Bn};

S = {S1,S2,...,Si,...,Sm};

T = {T1,T2,...,Ti,...,Tk}.

Here G = (A*B) x S is functionality, represented by CodeFlow Transaction (CFT) Graph (Fig. 1); S = {SbS2,...,S;,...,Sm} are nodes represented by software variables states when simulating test segments (patterns). Otherwise the graph can be considered as an ABC-graph -Assertion Based Coverage Graph. Each state Sj = {Sj1,Sj2,...,Sjj,...,Sjp} is determined by the values of

design essential variables (Boolean, registers, memory). The oriented graph arcs are represented by a set of software blocks:

n

B = {BbB2,...,Bj,...,Bn}; u Bj = B;Bj n Bj =0.

j=1 j*j

The assertion Aj є A = {A1,A2,...,Aj,...,An} can be inserted to the end of each block Bi - a sequence of code statements which determines the state of the graph node Sj = f(T,Bj) depending on the test pattern T={Tt,T2,-,Tb...,Tk}. The monitor, uniting an assertions of incoming arcs A(Sj) = Ap v Ai2 v... v Aij v...v Aiq can be put on each node.

B = (B1B3B9 v (B2B7 v B1B5 )B11)B13 v v((B1B4 vB2B6)B10 vB2B8B12)B14 =

= B1B3B9B13 v B2B7B11B13 v B1B5B11B13 v vB1B4B10B14 vB2B6B10B14 v B2B8B12B14.

Figure 1. Example of ABC-graph for HDL-code

The model of HDL-code, represented in the form of ABC-graph, describes not only software structure, but also test segments of the functional coverage, generated by using software blocks, incoming to the given node. The last one defines the relationship between achieved on the test variable space and potential one, which forms the functional coverage

of graph node state Q = cardSj / cards?. In the aggregate all

nodes have to be full state coverage space of software variables, which determines the test quality, equal to 100%:

m , m

Q = card IJSj/ card |J S? = 1. Furthermore, the assertion set i=l i=l

<A,S> that exists in the graph, allows monitoring arcs (code-coverage) В = (Е^Зг*—Зь—3n) and nodes

(functional coverage) S= The

assertions on arcs Bi є B are designed for diagnosis of the functional failures in software blocks. The assertions on graph nodes Si є S carry information about the quality of test and assertion set for their improvement or complement. The ABC-graph makes possible the following: 1) to estimate the software quality via diagnosability design; 2) to minimize the costs for generating tests, diagnosing and correcting the functional failures by using assertions; 3) to optimize test synthesis via coverage all arcs and nodes by a minimum set of activated test paths. For instance, the minimal test for the above mentioned ABC-graph has six segments, which activate all existent arcs and nodes, shown in Fig. 1.

For diagnosing, test segments T = {T1,T2,...,Tr,...,Tk} activate transaction paths in the graph model covered all nodes and arcs. Generally, the testing model is represented by the Cartesian product M = T x A x B that accordingly has the dimension Q = k x h x n. To reduce the amount of diagnosys data, separate monitor or assertion point for visualization functional blocks activation is assigned to each test segment. It makes possible to decrease the matrix dimension to Q = n x k and retain all features of the triad relationship M =< T x A x B >. Pair «test - monitor» are represented by three possible forms:

< T; —»Aj >,< {T;,Tr} ^Aj >,< {Tj} —» {Aj,As} >.

The method for diagnosis of functional block failure uses pre-built TAB-matrix (table) M = [My], where the row is

the relation between the test segment and a subset of activated blocks

Ti ^ Aj * (Mi1,Ml2,...,MiJ,...,Min),MiJ = {0,1},

observed by the monitor Aj . Column of the table describes

the relation between the functional blocks, detected on test segments, relatively monitors Mj =Bj(Tj, Aj).

For faulty blocks diagnosis at the testing procedure, the

* * * * *

real assertion response (vector) A (A^A^,—,A .,...,An)

on the test pattern T is determined, by forming

A* = f(TbBi) . Detecting faulty functional blocks is based

on xor-operation between the real assertion response vector and TAB-matrix columns

A* ©[M1(B1) vM2(B2) v... vMj(Bj) v... vMn(Bn)]. The faulty block is defined by a vector B J , which gives result with minimal number of 1-unit coordinates:

b = min [Bj = 2 (Bij © a*)].

j=1,n i=1

As an addition to the diagnosis model, necessary to describe the following important features of the TAB-matrix:

m n

1) Mi = (^ x Aj); 2) v Mij ^V Mj = 1;

i= J=1

n k

3) Mij © Mrj * Mij; 4) Mij © Mir * Mij;

J=1 i=1

5) log2n < k ^ log2 |B < |T|

6) Bj = f(T, A) ^ B © T © A = 0.

The features mean: 1) Each row of the matrix is a subset of the Cartesian product between test and monitor. 2) Disjunction of all matrix rows gives a vector equal to 1-unit over the all coordinates. 3) All matrix rows are distinct, which eliminates the test redundancy. 4) All matrix columns are distinct, which exclude the existence of equivalent faulty blocks. 5) The number of matrix rows must be greater than the binary logarithm of the number of columns that determines the potential diagnosability of every block. 6) The diagnosis function of every block depends on the complete test and monitors, which must be minimized without diagnosability reduction. In accordance with 6 test segments activated the following graph nodes paths relatively assertion point S9:

T = SoS^SySg V SoS^SgSg V SoS^SySg V vSoS2S4S8S9 VS0S2S5S7S9 VSoS2S6S8S9,

it will be easy using graph structure to define all functional block paths (oriented arcs) activated by test:

B = B1B3B9B13 V B2B7B11B13 V B1B5B11B13 V VB1B4B10B14 VB2B6B10B14 VB2B8B12B14.

The assertion engine can be represented by 3 groups of components, which create logical equations for monitoring software or hardware functionality HDL-code blocks based on visual points {A9 c S9,A3 c S3,A6 c S6 } :

A9 = T1(B1B3B9B13) V T2(B2B7B11B13) V

V T3(B1B5B11B13) V T4(B1B4B10B14) V

V T5(B2B6B10B14) V T6(B2B8B12B14);

A3 = T1(B1B3); A6 = T6(B2B8).

The next step allows creating 6 rows of TAB-matrix M ij (G1) in the form of relations between test segments and

blocks activated respectively:

Mij(G,) Bi B2 B3 B4 B5 B6 B? Bg B9 Bio B11 B12 Віз Bl4

Tl_>S9 1 1 1 1

T2_>S9 1 1 1 1

T4->Sg 1 1 1 1 1 1 1 1

Т4 >■ Sq 1 1 1 1

1 1 1 1

Ti^-Sa t6->s6 1 1 1 1

The TAB-matrix of paths activation shows the existence of equivalent failure blocks 3 and 9, 8 and 12, on 6 test segments with one assertion point in the graph node 9. The columns 3 and 9, 8 and 12 are equivalent. To resolve indistinguishability of two pairs faulty blocks it is necessary to create two additional monitors in the nodes S3 and S6 for test segments T1 and T6 respectively. As a result, three assertions in the nodes A=(S9,S3,S6) allow distinguishing all faulty blocks of software HDL-code. Thus, the graph enables not only to synthesize the optimal test, but also to determine the minimal number of assertion monitors in the nodes to detect faulty blocks with a given diagnosis depth.

Diagnosis procedure by using the created matrix is defined the folloving equation of vector xor-operation between real 8 assertion values and the B-columns:

{[A9(T1,T2,T3,T4,T5,T6),A3(T1), А6 0б)] © Bj = 0} ^

^ (Bj - failed).

II. Design for diagnosability

Diagnosability is the relationship D = Nd /N between the recognized faulty blocks amount Nd, (when there are not equivalent components, or the diagnosis depth is equal to 1), and the total number N of HDL-blocks.

For the expense E evaluation of the TAB-matrix model for detecting functional failures, it can use the pair test-assertions efficiency for a given diagnosis depth. Criterion E functionally depends on the relation between the ideal ]log2N[xN and real |t| x |a| x N memory sizes or resources

(where |T - the test length, |a| - a number of assertions)

for the corresponding TAB-matrices, which compose the relative expense reduced to 0-1 intervals:

E = ]log2N[xN = ]log2N[

IT x |a| x N IT x |a|

The general diagnosis quality criterion depends on expense E and diagnosability D:

Q = ExD = ^ xN..

IT x |a| N

For instance, the diagnosis quality of the TAB-matrix MijtGj) before and after adding two rows equal to

Q1[M(6 x 1x 14)] = Q2[M(8 x 1x 14)]

x Ю = 0,47

16 x 1 14

]log214[ x 14 = 05

|8 x 1 14 =-

1. it means, the first matrix dimension is a little bit less than the second, but diagnosability is a better in the second variant of matrix, which becomes the winner of the whole. Comparing to the well-known solutions [12], when every

cell of a matrix contains all existing assertions KHAI

the second variant evaluates the following low value:

]log214[ 14

Q2[M(6 x 3 x 14)] = J f21 x — = 0,2.

6 x 3 14

So, the TAB-matrix operating by the selected pair test-assertion concurrently allows having the essential advantages in memory size reducing in |A| — 1 times with the same diagnosability value.

The TAB-matrix diagnosis quality is the ratio of the bit number needed for identification (recognition) of all blocks ]log2N[ related to the real number of code bits, presented by

the product of test length and number of assertions |t| x | A|.

if the first part E of quality criterion Q is equal to 1 and every block with functional failures is recognized in the field of the rest components Nd = N , it means a test and assertions are optimal, that gives the best quality criterion of diagnosis model Q=1.

The purpose of the ABC-graph analysis is structured evaluation of assertion monitor placement, which make possible to obtain maximal diagnosis depth of fault blocks. Diagnosability of the ABC-graph is a function depending on the number Nn of transit not ended nodes where exist only two adjacent arcs, one of which is incoming, other one is outgoing. Such arcs form paths though the node without fan-

in and fan-out branches (N is the total number of arcs in the graph):

D

N-Nn

N

The estimation Nn is the number of unrecognizable or equivalent functional blocks. Potential installation of additional monitors for improving diagnosability of failure blocks is pure transit nodes composed Nn. The diagnosis quality criterion of the ABC-graph takes the form:

Q = E x D = ^ x N-Nn .

T x A N

The last expression produce some practical rules for synthesis of diagnosable HDL-code: 1) Test or testbench must create a minimal number of single activation paths, covered all the nodes and arcs in the ABC-graph. 2) The base number of monitors equals to the end node number of the graph with no outgoing arcs. 3) An additional monitor can be placed on each not ended node, which has one incoming and one outgoing arc. 4) Parallel independent code blocks must have n monitors and a single concurrent test, or one integrated monitor and n serial tests. 5) Serially connected blocks have one activation test for serial path and n-1 monitor, or n tests and n monitors. 6) The graph nodes, which have more than 1 number of input and output arcs, create good conditions for the diagnosability of the current section by single path activation tests without installation additional monitors. 7) The test pattern or testbench has to be 100% functional coverage for the nodes of the ABC-graph. 8) Diagnosis quality criterion as a function depending on the graph structure, test and assertion monitors can always be increased close to the 1-value. For this purpose there are two alternative ways. The first one is increasing test segments by activating new paths for recognition equivalent faulty blocks without increasing assertions, if the software graph structure allows the potential links. The second way is adding assertion monitors on transit nodes of the graph. A third so called hybrid variant is possible, based on the joint application of two above-mentioned ways.

III. Multilevel diagnosis method of digital system

Multilevel model of the multi-tree B (Fig. 3) is shown, where each node is represented by digital or computer system component, which has a three-dimensional activation TAB-matrix of functional unit subcomponents.

The outcoming from the node arcs are transitioning to a lower detailed level in diagnosing process, when replacing faulty block is too expensive:

rs n mr prs krs rs

B = [Brs], cardB = 2 2 2 2 Brs,

J r=1 s=1 i=1 j=1

where n is a number of diagnosis multi-tree levels; mr is a number of functional units or components at the level r; krs (Prs) is a number of components (test length) in the table

Brs ; Bj = {0,1} is a component of an activation table,

which is defined by 1-unit the detected faulty functionality

under the test segment T relatively to the observed

i-Ai

monitor-assertion Ai . Each node-table has the number of outcoming down arcs equal to the number of functional components, which are represented by activation TAB-matrixes as well.

Figure 3. Diagnosis multitree model

Method for faulty blocks diagnosis Hardware-Software HS-system, based on multi-tree model, allows creating the universal engine in form of algorithm (Fig. 4, block 6) for traversal of tree branches on the depth, specified a priory:

|0 ^ {Br+1,s,R}; Brs ® Ars =i j

j І1 ^ {Bjrs+i,,T}.

Here xor-vector-operation is executing the matrix columns

with the assertion (output) response vector Ars , which is

determined by the real (m) and gold (g) functionality responses under test patterns based on xor-operation:

A[s = m[s ©g[s,i = 1,krs . If all coordinates of vector xor-

sum Brs © Ars = 0 is equal to zero then one of the

following action is performed: the transition to the activation

matrix of the lower level Br+1,s or repair of the functional block B = B]S.

One of two analysis ways is executed, what is the most important: 1) the time (t>m, block 10) - then repair of faulty block is performed; 2) the money (t<m) - than a transition down is specify more exact fault location, because replacement of smaller block decreases the repair cost. If at least one coordinate of the resulting xor-sum vector is equal

to one Brs © Ars = 1 , then transition to the next matrix column is performed. When all coordinates of the assertion vector are equal to zero Als = 0, fault-free state of a HS-system is defined. If all vector sums by executig TAB-matrix

column are not equal to zero Brs © Ars Ф 0, it means a test,

generated for detecting the given component of functionality has to be corrected. If more than one wector sum obtained by executig TAB-matrix column are equal to zero

Brs © Ars = 0 , it means an assertion engine, created for

detecting the given component of functionality on the represented test has to be supplemented an extra assertion monitors. So, the TAB-engine has four end-nodes, where one of them is B-good which indicates successful finishing of the testing. Anoters three means the intermediate results in the test process, which is nessessary to take into account for the incresing a test quality and diagnosis depth by using extra assertions and/or additional test segments generation.

Thus, the graph shown in the Fig. 3, allows realizing efficient infrastructure IP for the complex technical systems. The advantages of the TAB-engine, which is invariant to the hierarchical levels, are the simplicity of preparation and presentation of diagnostic information in the form of minimized activation table of functional blocks on the test segments.

Technological model of infrastructure for embedded testing, diagnosis and repairing of faulty blocks (Fig. 5) has three components: 1. Block testing (Unit Under Test -UUT) by using a reference gold model (Model Under Test -MUT) for generating the assertion response vector ma which dimension corresponds to the number of test patterns.

2. Searching faulty blocks based on analysis of the TAB-matrix. 3. Repairing faulty blocks by replacing the good components from the Spare Primitives.

Process model of embedded IP service operates in real time and allows supporting good state of the HS-system without human actions distantly. The proposed algorithm or TAB-engine for analysis of TAB-matrix, as well as the introduced diagnosis quality criteria allow solving the problems of quasi-optimal coverage for software and hardware blocks by test and assertions. The model shown in Fig. 5 allows effectively servicing complex HS-system. The advantages of this functionality that is invariant to the hierarchical levels, lies in simplification of preparation and

presentation of diagnosis information in the form of minimized activation table for functional blocks by using test segments.

In the last case, the effect - time benefits - is obtained via introducing the additional infrastructure to the design, Fig. 6, which allows performing selective testing, diagnosis, and reprogramming some modules in the faulty detected blocks.

Fig. 5. Model for embedded testing HS-components

Fig. 6. Infrastructure for testing CS

Here (fig. 5) the blocks are shown: Testbench - tests for functional blocks, FC - functional test coverage, F -functional blocks, DI - diagnosis information in form of faulty blocks detection tables, DT - methods and tools for diagnosing, DA - results of diagnosis analysis, FB - faulty functional modules, Repairing - repair of functional modules. The boundary scan cell, shown in Fig. 7, performs service of a single functional cell.

Fig. 7. Boundary scan cell

IV. Case study for diagnosis

To illustrate the performance of the proposed model and method the functionalities of three modules of the digital filter of Daubechies [11] are considered below.

As a second test case for the practical use of the proposed activation model and xor-method TAB-matrix analysis for searching faulty blocks is further proposed the synthesis of diagnosis matrix for the main graph filter, shown in Fig. 8.

Figure 8. Transaction main-TL graph

The graph is associated with the following diagnosis TAB-matrix, which has 6 activated test segments and 8 assertions:

Mjj(TL) Bi Bz B4 B5 B6 B7 Bg B9 Bio Bn Вц Віз Bl4

Tt^F7 1 1 1 1

T2 т3 >Cj 1 1 1 1 1 1 1 1

T4 -^Tio 1 1 1 1

TS “*^2 T6 >і'із 1 1 1 1 1 1 1 1 1 1

Ti^-F2 T2 >І'3 1 1

The system of diagnosis functions for hardware implementation as a part of Infrastructure IP corresponding to the rows or monitors is followed:

F7(T1) = bJb13B15B17; F8(T2) = b2b4b5b8;

F9(T3) = b11b6b1b13; F^Ot) = b4b15B16b12;

FL2CT5) = BlB13B15B19Bl3; F^Oe) = b2b4b6b10b14; F2CT1) = ВІ; F3 (T2 ) = B2.

synthesis of the diagnosis matrix for one discrete cosine transform module from the Xilinx library in the form of functional coverage is shown in Listing 1.

Listing 1. Part of functional coverage

c0: coverpoint xin {

bins minus_big={[128:235]};

bins minus_sm={[236:255]};

bins plus_big= {[21:127]};

bins plus_sm={[1:20]};

bins zero={0}; }

c1: coverpoint dct_2d

{ bins minus_big={[128:235]};

bins minus_sm={[236:255]};

bins plus_big= {[21:127]};

bins plus_sm={[1:20]};

bins zero={0};

bins zero2=(0=>0);

}

endgroup

The rest 12 modules of the transaction graphs, activation TAB-matrices, and logic functions are developed for testing and fault detection in the discrete cosine transform too.

A fragment of monitor engine is presented by Listing 2.

Listing 2. Code fragment of monitor engine

sequence first( reg[7:0] a, reg[7:0]b); reg[7:0] d;

(!RST,d=a)

##7 (b==d); endsequence property f(a,b);

@(posedge CLK)

// disable iff(RST||$isunknown(a)) first(a,b);

!RST |=> first(a,b); endproperty

odin:assert property (f(xin,xa7_in))

// $display("Very good");

else $error("The end, xin =%b,xa7_in=%b", $past(xin, 7),xa7_in);

Testing of discrete cosine transformation in the environment Riviera, Aldec detects incorrectness in seven rows of HDL-models:

//add_sub1a <= xa7_reg + xa0_reg;// subsequent correcting code allowed obtaining the following code (Listing 3).

Listing 3. Corrected code fragment

add_sub1a <= ({xa7_reg[8],xa7_reg} + {xa0_reg[8],xa0_reg}); add_sub2a <= ({xa6_reg[8],xa6_reg} +{xa1_reg[8],xa1_reg}); add_sub3a <= ({xa5_reg[8],xa5_reg} +{xa2_reg[8],xa2_reg}); add_sub4a <= ({xa4_reg[8],xa4_reg} + {xa3_reg[8],xa3_reg}); end

else if (toggleA == 1'b0) begin

add_sub1a <= ({xa7_reg[8],xa7_reg} - {xa0_reg[8],xa0_reg}); add_sub2a <= ({xa6_reg[8],xa6_reg} - {xa1_reg[8],xa1_reg}); add_sub3a <= ({xa5_reg[8],xa5_reg} - {xa2_reg[8],xa2_reg}); add_sub4a <= ({xa4_reg[8],xa4_reg} - {xa3_reg[8],xa3_reg});

Practical implementation of models and verification methods is integrated into the simulation environment Riviera of Aldec Inc., Fig. 9. New assertion and diagnosis modules, added into the system, improved the existing

verification process, which allowed 15% reduces the design time of digital product.

Actually, application of assertions makes possible to decrease the length of test-bench code and considerably reduce (х3) the design time (Fig. 10), which is the most expensive. Assertion engine allows increasing the diagnosis depth of functional failures in software blocks up to level 1020 HDL-code statements.

Due to the interaction of simulation tools and assertion engine, automatically placed inside the HDL-code, an access of diagnosis tools to the values of all internal signals is appeared. This allows quickly identifying the location and type of the functional failure, as well as reducing the time of error detection in the evolution of product with top-down design. Application of assertion for 50 real-life designs (from 5 thousand up to 5 million gates) allowed obtaining hundreds of dedicated solutions, included in the verification template library VTL, which generalizes the most popular on the market EDA (Electronic Design Automation) temporal verification limitations for the broad class of digital products. Software implementation of the proposed system for analyzing assertions and diagnosing HDL-code is part of a multifunctional integrated environment Aldec Riviera for simulation and verification of HDL-models.

Figure 9. Implementation of results in the system Riviera

Time-to-market comparison

0,112 0,207 0,315 0,389 0,504 0,620 0,731 0,824 0,931 1,015 Design capacity (MGates)

Figure 10. Comparative analysis of verification methods

High performance and technological combination of assertion analysis system and HDL-simulator of Aldec Company is largely achieved through integration with the internal simulator components, including HDL-language compilers. Processing the results of the assertion analysis system is provided by a set of visual tools of the Riviera

environment to facilitate the diagnosis and removal of functional failures. The assertion analysis model can also be implemented in hardware with certain constraints on a subset of the supported language structures. Products Riviera including the components of assertion temporal verification, which allow improved the design quality for 3-5%, currently, occupies a leading position in the world IT market with the number of system installations of 5,000 a year in 200 companies and universities in more than 20 countries.

V. Conclusion

1. Infrastructure and technology for digital systems analysis are presented. Proposed transactional graph model and method for diagnosis of digital systems-on-chips are focused to considerably reducing the time of faulty blocks detection and memory for storing the diagnosis compact matrix describing ternary relations in format: the monitor-oriented test-segments which detect faulty functional components of the Hardware-Software system.

2. New diagnosis quality criterion as a function depending on the graph structure, test, and assertion monitors is proposed. For this purpose there are two alternative ways. It allows making good choices in diagnosability improving by increasing test segments set for recognition equivalent faulty blocks or adding assertion monitors on transit nodes of the activation HDL-code graph.

3. An improved TAB-engine or algorithm for functional failures detection in software or hardware is proposed. It is characterized by using the xor-operation, which makes possible to improve the diagnosis performance for single and multiple faulty blocks on the basis of parallel analysis of the TAB-matrix, boundary scan standard IEEE 1500, and vector’s operations called and, or, xor.

4. A model for diagnosing the functionality of system-on-chip in the form of multi-tree and method for tree traversal, implemented in the engine for detecting faulty blocks with given depth, are developed. They considerably increase the performance of software and hardware Infrastructure IP.

5. Test verification of the diagnosis method is performed by three real case studies, presented by SoC components of a cosine transform filter, which showed the consistency of the results in order to minimize the time of faulty blocks detection and memory for storing diagnosis information, as well as increase the diagnosis depth of digital unit.

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