CC BY
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Modification of Elementary Operational Linear Chains in Compositional Control Unit with
Code Sharing
Aleksander A. Barkalov, Member, IEEE, Larysa A. Titarenko, Aleksander N. Miroshkin
Abstract - The new design method for compositional microprogram control units with code sharing and elementarization of operational linear chains is proposed. The method targets on reduction in the number of LUT-elements in the combinational part of control unit. Some additional control microinstructions containing codes of the classes of pseudoequivalent chains are used for operational linear chains modification. Proposed method is illustrated by an example. Most desirable GSA characteristics for using proposed method were obtained.
Index Terms - Circuit synthesis, flow graphs, logic devices, minimization methods.
I. Introduction
Using of any elementary basis for realization of control unit circuits causes necessity of taking into account not only control algorithm peculiarities but basis features also. The task of hardware amount decrease became very urgent when one need to realize complex of operational and control units on one chip [1]. One of possible way of this task solving is hardware amount decrease in control unit due to using of pseudoequivalent states of Graph-Scheme of Algorithm (GSA). High percentage (>75%) of operational vertices in GSA [2] and presence of embedded memory blocks make it possible of using this synthesize method modification.
Compositional microprogram control unit (CMCU) is reasonable to use in case of linear GSA (percentage of operational vertices in GSA is over 75%) [2]. FPGA (Field-Programmable Gate Arrays) basis is commonly used for realization of control unit circuit [3, 4]. Modification of synthesis method for CMCU with code sharing and modification of operational linear chains (OLC) is proposed in this article.
The main purpose of investigation is simplification of
Manuscript received December 20, 2009. Modification of elementary operational linear chains in compositional control unit with code sharing.
A. A. Barkalov is with University of Zielona Gora, Poland. E-mail: A.Barkalov@iie.uz.zgora.pl
L. A. Titarenko is with University of Zielona Gora, Poland.
E-mail: L.Titarenko@iie.uz.zgora.pl
A. N. Miroshkin is with Donetsk National Technical University, Donetsk, Ukraine. MiroshkinAN@gmail.com.
combinational part of CMCU via implementation to GSA of additional vertices containing pseudoequivalent operational linear chain (POLC) class code. The main task of investigation is development of CMCU synthesis method modification that let decrease number of LUT-elements (Look-Up Tables, structural elements of FPGA basis) in Block of Microinstruction Addressing (BMA). Control algorithms are represented as GSA.
II. MAIN STATEMENTS
Graph-scheme of control algorithm consists of operational and conditional vertices, making sets E1 and E 2 accordingly, and the set of arcs E . Let us begin vertex be marked as b0 , end - bE . Operational vertex bq e E1 contain set of microinstructions Y(bq) c Y, where Y = {yi,.. .yN} is the set of output signals of control unit. Conditional vertex bg e E2 contains one elements X(bg) of the logical conditions set X = {x1,...xL}. In case of operational vertices percentage is over 75% from total number of vertices, we talk about linear GSA.
OLC is a sequence of operational vertices of graph-scheme of algorithm. Each OLC a g has accidental number
of inputs Ig and only one output Qg . Formal definitions of
OLC, its input and output one can find in [5]. OLC with only one input and one output is called elementary [2].
OLC, outputs of which are connected with the input of the same vertex are called pseudoequivalent operational linear chains (POLC). Such OLCs make the class Bi. All
classes are packed into the set B = {Bi,..Bi} of POLC classes.
Let GSA contains G elementary OLC ag that form the set C .
Ri = I"log2 G1 (1)
bits are enough for encoding elements of the set C . Number of components in OLC a g is marked as Fg.
Maximum length Q = max(, .Fg ) of linear chain
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determines number of bits R2 in the code for encoding OLC components, where
R2 = ["log2 QT (2)
Elements Tr ex and Tr e T are used for encoding elementary OLC and their components accordingly. It being known that |x| = R1 and |t| = R2 . Encoding of components is performed in natural order, that is
K(bgi) = K(bgi-1) +1, (3)
where g = 1,G, i = 1,Fg.
Each operational vertex bq e Ej corresponds to microinstruction MIq storing in control memory (CM) in the cell with address A(bq) = Aq. Code sharing is obtaining of the address A q as concatenation of OLC code and its component code [2]. Total width of address is
RA = R1 + R2 • (4)
Structure of compositional microprogram control unit with elementary OLC and code sharing can be used for interpr etation of graph-scheme of control algorithm (Fig. 1). Let us call this structure U1.
Fig. 1. Structure of compositional microprogram control unit with elementary OLC and code sharing
Block of microinstruction addressing in CMCU scheme realized function of memory excitation for register RG:
^ = ^ (X, t). (5)
When signal Start is coming initial microprogram address is loaded into RG, zero value is loaded into CT, and flip-flop TF is set to “1” that allows reading microinstructions from control memory. There are two additional internal signals: yo and yE. In case of yo = 1 content of CT is incremented and next vertex of current operational linear chain is addressed. If yo = 0 then OLC output is reached and BMA prepares address of next OLC
using code of current POLC class. Signal yE is used at the end of microprogram to reset flip-flop TF. The value “0” of TF output stops access to CM.
Asynchronous reset of counter must be controlled by function Start v yo . Signal yo ensures loading zero value to the CT when transition to another OLC performed.
Number of terms in BMA scheme can be decreased by implementation OLC code transformer into POLC class codes [2]. But such realization demands extra FPGA recourses.
In the article complexity of code transformer is proposed to decrease by additional vertices with pseudoequivalent class codes. Free recourses of embedded memory are proposed for storing additional microinstructions.
Ш. MAIN IDEA OF PROPOSED METHOD
In initial GSA the set Q contains OLC a g, which are
not connected to the end vertex of GSA. All operational linear chains are divided into classes Bi еПc of POLC. Binary code K(Bi) of width R3 is set to each class Bi, where
R3 =Tlog2 IT . (6)
In (6) I is number of POLC classes. After output vertex of each OLC a g e Q additional vertex is added. It
contains pseudoequivalent class code K(Bi) of current
1
OLC. For modified OLC encoding R2 five bits are enough, where
r2 = (log2 Q'T (7)
In (6) Q' is maximum number of vertices in OLC after
I
their modification, therefore R2 > R2 .
Embedded memory blocks (EMB) in FPGA can be configured for different task performing. So, in Stratix III chip exists next configurations: 16Kx8, 8Kx16, 4Kx32, 2Kx64, 16Kx9, 8Kx 18, 4Kx36, 2Kx72 [4]. Total number of chip contacts is constant value, that’s why method modification usage restriction presents. If Nc is memory chip contacts number, then
n1 = Nc -rA (8)
free contacts of each block can be used for microinstruction generation, where
RA = R1 + R2 . (9)
For all output signals realization Nemb memory blocks are used:
nemb =
N + 2 n1
(1o)
In (1o) N is number of bits for output signals unitary encoding [2]. Constant «2» takes into account additional
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internal variables y0 and yE. Total number of unused memory outputs is obtained according (11):
n2 = n1
*
N + 2
(N + 2)
(11)
n1
Address width of OLC component can be increased as a result of additional vertices implementation. In this case only (11 -1) outputs of each block are used for output
functions realization. If number of used EMB still the same when number of free memory outputs is decremented, usage of proposed method modification is reasonable, i.e.:
N+2
n1
*n1 =
N+2 n1 -1
* (1 -1).
(12)
Thereby, condition of reasonability is one of next conditions fulfillment:
R2 = R2;
N + 2 n1
*n1 =
N + 2 n1 -1
* (1 -1)
(13)
First condition means the same code width for encoding both non-modified and modified OLC components. Second one ensures the same number of used EMB block when codes of non-modified and modified OLC components have different widths. If one or/and two conditions from (13) take place, modification of syntheses method can be done. CMCU structure U2 is obtained (Fig. 2).
Other blocks of CMCU U2 perform corresponding functions to functions of CMCU U1 blocks. Let us point out that structural elements BMA, CT, RG, TF is realized in LUT-elements, and CM is implemented in embedded memory.
The following method of CMCU U2 synthesis is proposed in this article:
1. Construction of the sets C, C1, and Пc for a GSA Г.
2. Implementation of additional vertices with pseudoequivalent class codes K(Bi) to OLC a g .
3. Encoding of OLC, their components and classes Bi e ПC .
4. Construction of the content of control memory.
5. Construction of CMCU transition table and ¥ = ¥(Z,X) functions.
6. Synthesis of CMCU logic circuit.
IV. Example of method using Let GSA Г1 (Fig. 3) be characterized by next sets: C = {a1,..., a б} - elementary OLC, C1 = C\ {a 5, a 6 } OLC without connection to the end vertex, Пc = {BbB2} -classes of pseudoequivalent operational linear elementary chains, where B1 = {a^, B2 = {a 2, a 3, a 4}.
Fig. 2. Structure of compositional microprogram control unit with elementary OLC and code sharing after implementation addition microinstructions
In CMCU U2 variables zr e Z, where |z| = R3, are bits of code K(Bi). Block of microinstruction addressing performed function
¥ = ¥(Z,X). (14)
with pseudoequivalent class codes
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Number of OLC G = 6, R1 = 3 bits from the set t = {tj, t2, t3} are used for their encoding. Maximum length of OLC is Q = 4, let us use R2 = 2 variables from the set T = {t1,T2 } for OLC components encoding. Total number of operational vertices is M = 12, this number demands R = 4 bit of address in CM. For encoding I = 2 classes B; e ПC of POLC R3 = 1 bit is used.
Fig. 4. Initial GSA Г after implementation of additional vertices with pseudoequivalent class codes
Let us encode OLC ag e C and their components in
arbitrary manner (3). Addresses A(bq) of CMCU U2(r1)
microinstructions are shown in Table I. Here and after symbol Ui(Tj) means, that CMCU U; interprets GSA Г .
From Table I one can obtain addresses as concatenation of OLC code and code of component, for example: A(b6) = 001011, A(b10) = 011000 and so on. Extra bit is
added to the OLC component code according to (6) and (9) because of maximum length of OLC after modification is
Q' = 5.
Table I
Addresses of CMCU Microinstructions
^"'--^^^t1t 2 t3 (T0)TjT^^ 000 001 010 011 100 101
(0)00 bi b3 b7 bi0 bii bi2
(0)01 b2 b4 b8 bi6 - -
(0)10 bi3 b5 b9 - - -
(0)11 - b6 bi5 - - -
(1)00 - bi4 - - - -
Codes of classes B; еПC are set as K(B1) = 0, K(B2) = 1. Microinstruction format of CMCU U2 in case of y0 = 1 includes fields y0 , yE , FY, where field FY contains code of microoperation set; and in other case y0, yE , FB - code of class B; e ПC .
Let EMB block contacts be NC = 25 [4], then according to (8), each block has n1 = 25 - 5 = 20 free contacts. Let us suppose number of output functions be N = 30. For their realization NEMB = 2 blocks of memory are used (10). According to (11) last block has n2 = 8 free contacts after realization of all output functions. Second condition of (13) takes place, modification of syntheses method is reasonable. Contents of CMCU U2(r1) control memory is shown in Table II.
Table II
Contents of CMCU Control Memory
A(bq) y0 FY yE
FB * 0
A(bi) 1 Y(bi) 0
A(b2) 1 Y(b2) 0
A(b13) 0 K(Bi) * 0
A(bs) 1 Y(bs) 0
A(b4) 1 Y(b4) 0
A(bs) 1 Y(b5) 0
A(b6) 1 Y(b6) 0
A(b14) 0 K(B2) * 0
A(b7) 1 Y(b7) 0
A(b8) 1 Y(b8) 0
A(b9) 1 Y(b9) 0
A(b15) 0 K(B2) * 0
A(b10) 1 Y(bi0) 0
A(b16) 0 K(B2) * 0
A(bll) * Y(bn) 1
A(b12) * - 1
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As one can see from Table 2, if bq e E1 is output of OLC ag e Cb microinstruction has value “0” in y0 field and code K(B;) instead of output function set Y(bq) in the microinstruction word.
Transitions from outputs of OLC ag e C1 are expressed by next system of formulae [2]:
B1 ^ x1b3 v x1x2b10 v x1x2b7; (15)
B2 ^ x3b11 v x3b12.
Such system is the base for CMCU U 2 transition table formation. This table consists of next columns: B;, K(B;), bq, A(bq), Xh, Yh, h. Their purpose became clear from Table III.
are used for analysis GSA additional vertices. But at the same time complexity of control unit circuit decreases, that leads to clock signal duration reduction. Conclusion about time characteristics of control unit can be done only for individual case.
Disadvantage of proposed method is in its usage limitation (13).
Scientific novelty of proposed method modification is in usage of POLC classes and free recourses of control memory for LUT-elements number decrease in block of microinstruction addressing. Practical meaning is in chip parameters decrease. It allows realization of device with less cost.
Our future work is directed at development of CAD system for synthesis of control units [5].
Table III
Fragment of CMCU transition table
Bi K(Bi) ■ bq A(bq) Xh Yh h
z1 T1 T2 T3
b3 0 0 1 x1 D3 1
B1 0 b7 0 1 0 x1 x2 D2 2
b10 0 1 1 x1x2 D2, D3 3
Addresses of microinstruction is taken from Table 1. Let us point out, that system of memory excitation functions Y includes functions {D1,D2,D3}. Total number of rows
References
[1] Соловьев В.В. Проектирование цифровых схем на основе программируемых логических интегральных схем. М.: Горячая линия-ТЕЛЕКОМ, 2001. 636 с.
[2] Баркалов А.А. Синтез устройств управления на программируемых логических устройствах. Донецк: ДНТУ, 2002. 262 с.
[3] Virtex-6 FPGAs. Lowest Power High-Performance FPGAs // Available:
http://www.xilinx.com/support/documentation/data sheets/ds150.pdf
[4] Stratix III FPGA: Lowest Power, Highest Performance 65-nm FPGA
// Available: http://www.altera.com/products/devices/stratix-
fpgas/stratix-iii/st3-index.jsp
[5] Баркалов А.А., Титаренко Л.А. Синтез микропрограммных автоматов на заказных и программируемых СБИС. Донецк: УНИТЕХ, 2009. 336 с.
H2(rj) in transition table of CMCU U2(rj) is equal to
number of terms in system transition formulae. In our example, H2(r1) = 5 .
System (15) is formed according to transition table. Fragments of system Y can be found from Table III:
D2 = z,x,;
11
D3 = z1x1 v z1 x1x2.
(16)
For minimization of terms number in (15) classes В; еПc may be encoded with the help of ESPRESSO algorithm, for example.
Realization of logical circuit of CMCU U 2 reduces to implementation of system (16) in base of integrated circuit (FPGA) and realization of control memory on blocks of embedded memory. Modern CAD systems or methods [1, 2] can be used for this purpose.
Aleksander A. Barkalov, Doctor of Science, Professor of DonNTU (Ukraine), Professor of University of Zielona Gora, Poland.
Scientific interests: digital control units, SoPC Address: Campus A, Budynek Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora
E-mail: A.Barkalov@iie.uz.zgora.pl
Larysa A. Titarenko, Doctor of Science, Professor of Kharkiv National Univercity of Radioelectonics (KNURE), Professor of University of Zielona Gora, Poland.
Scientific interests: Digital, adaptive and spatialtime processing of signals in telecommunication. Management and control in communication networks Research of modern digital telecommunication systems and nets.
E-mail: L.Titarenko@iie.uz.zgora.pl
V. Conclusion
Proposed method of OLC modification for compositional microprogram control unit is oriented to LUT-elements decrease in the block of microinstruction addressing. Number of memory blocks in device is the same as for base structure CMCU U1 with code sharing. Extra clock cycles
Aleksander N. Miroshkin, Assistant of Donetsk National Technical University. Scientific interests: digital control units.
E-mail: MiroshkinAN@gmail.com
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