Design of compositional microprogram control units with maximal encoding of inputs Текст научной статьи по специальности «Электротехника, электронная техника, информационные технологии»

UDC 519.713:681.326

DESIGN OF COMPOSITIONAL MICROPROGRAM CONTROL UNITS WITH MAXIMAL ENCODING OF INPUTS

BARKALOVA, REMIGIUSZ WINIEWSKI

The method of optimization of logic circuit of compositional microprogram control unit with sharing of the codes is proposed. Method is based on the transformation of the pairs (code of operational linear chain, maximal code of input) in the addresses of the input of operational linear chain. The method of design and example of its application is proposed.

1. Introduction

A control unit of any digital system can be implemented as a compositional microprogram control unit (CMCU) including a finite-state-machine (FSM) of microinstruction’s addressing [1]. The circuit of FSM can be implemented using programmable logic devices (PLD) such as PLA, PAL, CPLD, FPGA [2,3]. The method of sharing of the codes [4] can be used to decrease the amount of PLDs in the circuit of FSM. But application of this method has sense only if total width of the code of operational linear chain (OLC) and the code of OLC’s component is equal to the width of the microinstruction’s address in CMCU with a base structure [1]. The method of synthesis permitting to apply sharing of the codes in any CMCU is proposed in given article. The method is based on the usage of special converter to form an address of the OLC’s input on the base of the transformation of the pair (code of OLC, code of input).

2. The main idea of the method

Let set of OLC[1] C = (a1v.., a G} is formed for flowchart Г and let natural addressing of microinstructions [1] is worked out for each OLC ag є C. In this case condition

A(bq) = A(bt) +1 (1)

is true for each pair of the operational nodes (bt ,bq) such as bt = prag,bq = pr1+1ag . Here A(bj) means an address of microinstruction corresponded to the operational node bj є B , B is a set of operational nodes. Each OLC ag є C has at least one input and sharply one output Og. Let I(ag) = {Ig,...,^} is a set ofinputs of OLC ag є C and І(Г) is set of inputs of all OLC of flow-chart Г.

A control unit can be implemented as a CMCU with base structure (Fig. 1) which will be denotated as Up

Here combinational circuit CC forms the excitation functions of register RG and counter CT

¥ = ¥ (т, X), (2)

Ф = Ф(т,Х), (3)

where x = {t1,...,tr } is a set of internal variables using to encode the internal states am є A = {a 1,..., aM } of the FSM, X={xi,..., xL}is a set of logic conditions. Counter CT forms an address bits Tr є T = {T1,...,TR1} of the control memory CM. Here R =]log2 M[, R1 =]log2 M1 [, M1=|B|. Signal y0 is used to add 1 to the content of CT according with (1).

Fig. 1. Structural diagram of compositional microprogram control unit U1

The disadvantage of CMCU U1 is a considerable amount of outputs of CC: t(U1) = R + R1 .

To reduce this amount we can represent an address A(bt) as a concatenation [4]:

A(bt) = K(a g)*K(bt). (4)

Here K(ag) is a code ofOLC ag є C with R2 =]log2 G[ bits, K(bt) is a code of component of OLC ag є C corresponding to the node bt є B . Code K(bt) has R3 =]log2M2[ bits where M2 is maximal amount of components in OLC ag є C. Sign * in (4) is used for operation of concatenation.

In this case control unit can be implemented as CMCU with sharing of the codes U2 (Figure 2).

Fig. 2. Structural diagram of compositional microprogram control unit U2

Here functions ф form a code K(Ig) of the j-th input, Ig (j=1,..., Kg) of OLC ag є C, functions ^ form a code of OLC ag є C in register. It’s clear that | x |= R2,| T |= R3 and circuit CC has t(U2)=R2+R3 outputs.

Such approach has sense if condition

R 2 + R3 = R1 (5)

is true. Otherwise R2 + R3 > R1 and the volume of CM in CMCU U2 is quite greater than a similar characteristic of CMCU U1.

In this article we propose to use a special address transformer (AT) to form an address A(Ig) on the base

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of the pair (K(ag), C(Ig)). Here C(Ig) is a maximal code ofthej-th input ofOLC ag є C. Let Z = {zj,...,zR } is a set of variables to encode the inputs ig by the codes C(lk) where

R4 =]log2M4[. (6)

Here M4 is a maximal amount of inputs among the OLC ag є C. In this case a control unit can be implemented as compositional microprogram control unit U3 (Fig. 3).

Fig. 3. Structural diagram of compositional microprogram control unit U3

Here circuit CC forms the system of functions

¥ = ^(t,X),Z = Z(x,X), (7)

circuit AT forms the excitation functions of counter

® = ®(Z, t). (8)

Such approach permits to diminish the amount of outputs ofthe circuit CC to t(U3) = R2 + R4 and to keep minimal amount of address bits of control memory (Ri) in a case when condition (5) is violated. This approach has sense if total cost of circuits CM and AT in CMCU U3 is less than cost of the control memory of CMCU U2 if condition (5) is not true.

3. Method of design of CMCU U3

The proposed method of design includes the following steps:

1. Formation of the set of OLC, natural addressing of microinstructions and formation of content of control memory. This step is executed using approach from [ 1 ]. Here we should form set І(Г) and addresses A(Ig) of the inputs of OLC ag є C.

2. Maximal encoding ofthe inputs. The parameter M4 can be find as M4=max(K1,..., KG). To minimize the amount of letters in the terms ofthe system (8) the inputs ofOLC ag є C should be encoded in such manner that major (R4-]log2Kg[) bits of the code C(Ig) contain zeros.

3. Formation ofthe table of transactions of CMCU. This table is a base for formation of the system (7). It contains the following columns:

ag,K(«g),atK(at),It,C(It),Xh,^h,Zh,h .

Here a t is an OLC of transaction and It is an input of transaction for output of OLC ag є C if input signal Xh= 1; input Xh is equal to conjunction of some elements

of the set X; excitation functions Th с T are used to switch the register RG from K(a g) to K(at); variables Zh c Z are equal to 1 in the code C(It). This table contains H lines and their amount is the same one as in case on CMCU U1.

4. Formation of the table of address transformer. This table is the base for formation of the system (8) and it contains the columns: ag , K(ag), Ig , C(Ig), A(Ig), Ф m , m. Here an address A(Ig) is taken from the table of content of control memory, column Фm contains the excitation functions фгеФ that are equal to one to load an address A(Ig) in the counter CT. The amount of the lines in this table is determined as M3=|I(r)|.

5. Design of the logic circuit of CMCU U3. The circuit CC is implemented using the system (7), terms

Fh (h = 1, H) of this system are determined as

r2 l

Fh = BgXh = ( Axj.gr)Xh. (9)

r=1

Here Bh is a conjunction of internal variables xr ex corresponding to the code K(a g) ofthe OLC from the h-th line of the table, lgr є {0,1} is a value of r-th bit

of the code K(ag), x0 =xr , x'r =xr(r = 1,...,R2). The circuit AT is implemented using the system (8) with terms

R4 і ■

Em = BmZgm = Bg1 (^zj^ )• (10)

Here zm is a conjunction of variables zr є Z corresponding to the code C(Ig) from the m-th line of this table (m=1,..., M3), lg є {0,1,*} is a value of the r-th bit of the code C(Ig) , z0 = zr , z'r = zr

z* = 1(r = 1,...,R4). Control memory is implemented using the table of its content. The problems arousing under the implementation of such circuits on PLDs are discussed in [3, 4].

4. Example of application of proposed method

Let CMCU U1 is set up by the table of control memory’s content (Table 1) and table of transactions (Table 2).

Table 1

Content of control memory of CMCU U1

Address Content Reference

000 У0 У1 У2 і! b

001 У0 У1 Уз B2

010 У0 У1 У2 B3

011 У0 У3 II2 b4

100 У2 У5 O1 b5

101 У0 У1 У4 i2 be a 2

110 Уз O2 b7 a 3

111 У1 Уз i3 O3 bs

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Table 2

Table of transactions of CMCU Uj

Og A(Og) 1j A(lj) Xh Фь h

O1 100 101 X1 D1 D3 1

i3 111 x1x2 D1 D2 D3 2

i2 011 X1 X2 D2 D3 3

O2 110 i3 111 1 D1 D2 D3 4

O3 111 i2 101 1 D1 D3 5

It is clear that C = {a1;a2, a3}, G=3, aj =< bj,...,b5 >,

Ij = bj, I2 = b4 , O1=b5, M1 = 5 , a2 =<b6,b7 > ,

I2 = b6 , O2=b7j M1=8, R1=3, T= { T1, T2, T3 } •

According to (7), M2=5 and R2=3. Because of G=3 we have R2=2, x = {x1, x2} • It means that R2+R3 > R1 and application of our approach has sense.

In our case M4=2 and R4=1, Z={z1}. Let’s encode the inputs in a following manner: C(lj) = 0 , C(lf) = 1, C(Ij2) = C(I3) = * • Here symbol * means a don’t care situation.

To form the table of transactions of CMCU U3 we should transform the table of transactions of CMCU U1 in the following manner:

— column Og is replaced by column a g;

— column A(Og) is replaced by column K(a g);

— column K(Ij) is replaced by column C(Ij);

— column Ф h is replaced by columns and Zh;

— columns at and K(at) are inserted.

Such transformation produces for our example the table of transactions of CMCU U3 (Table 3).

Table 3

Table of transactions of CMCU U3

«g K(ag) I t at K(at) C(I j) Xh Zh h

i2 a2 01 * X1 D2 -- 1

a1 00 i3 a3 10 * X1X2 D1 -- 2

i2 a1 00 1 X1 X2 -- Z1 3

a2 01 i3 a3 10 * 1 D1 -- 4

a3 10 i2 a2 01 * 1 D2 -- 5

Table 4

Table of the address transformer of CMCU U3

ag K(ag) !g c(i g) A(i g) Фт m

a1 00 11 0 000 -- 1

I? 011 D5 D6 2

a2 01 * 101 D4 D6 3

a3 10 i3 * 111 D4 D5 D6 4

5. Conclusion

The proposed method permits to use the principle of sharing of codes under any characteristics of operational linear chains of initial flow-chart. The optimization of the length of the address of the input of the linear chain is performed The researches conducted by the authors have shown that its application permits to decrease the cost of CMCU by 15-18% in comparison with CMCU with base structure.

Literature: 1. Barkalov A. A, Palagin A.V. Synthesis of microprogram control units. Kiev: IC NAC of Ukraine, 1997. 136 pp (in Russian). 2. Barkalov A.A. Synthesis of control units on programmable logic devices. Donetsk: DNTU, 2002. 262 pp (in Russian). 3. Solovjev V. V. Design of digital systems using the programmable logic integrate circuits. Moscow: Hot line - Telecom, 2001. 636 pp(in Russian). 4. Solovjev V. V. Design of the functional units of digital systems using programmable logic devices. Minsk: Bestprint, 1996. 252pp (in Russian).

Поступила в редколлегию 29.03.2004

Рецензент: д-р техн. наук, проф. Хаханов В.И.

Alexander Barkalov, Doctor of Technical Science, professor of The University of Zielona Gyra, Faculty of Electrical Engineering, Computer Science and Telecommunication, Institute of Computer Engineering and Electronics.

Address: ul. Podgyrna, 50, 65-246 Zielona Gyra, Poland. Phone: (+48 68) 328 2693.

E-mail: a.barkalov@iie.uz.zgora.pl

Remigiusz Winiewski, Master of Science, assistant of University of Zielona Gyra,

Faculty of Electrical Engineering,

Computer Science and Telecommunication, Institute of Computer Engineering and Electronics. Address: ul. Podgyrna, 50, 65-246 Zielona Gyra,

Poland. Phone: (+48 68) 328 2526. Email: r.wisniewski@iie.uz.zgora.pl

From this table we have functions (7), for example,

D1 =X1 T2x1x2 VX1X 2 = F2 V Еф , z1 =X1 T2x1x2 = F3 .

The table of address transformer in our case contains M3=4 lines (Table 4).

From this table we have system (8), for example,

D5 = E2 vE4 =x1 x2z1 vx1 x2 .

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