General Testing Models of SOC Hardware-Software Components Текст научной статьи по специальности «Компьютерные и информационные науки»

gives a digital system the marvelous self-repair feature by means of I-IP for hardware and software components. An instance of it is robust multicore version of hardware. At that a faulty addressable component can be replaced by other one (faultless) in the process of operation. Addressability has to be used when creation of critical software, in which availability of addressable diversion (multiversion) components gives a software system an opportunity to replace components at fault appearance. 13. The technological problem of offline on-chip self-testing, self-diagnosis and self-repair by using external facilities (or without them), which are solved by all leading companies, is quite interesting. To solve the problem the modern wireless and Internet technologies of distant service are applied. Disadvantage of these technologies is opportunity of remote unauthorized access to a chip that can result in unwanted destructive consequences and digital system failure. Though, the specific character of digital system-on-a-chip is the marvelous ability to remove faults distantly due to chip connection with outer space by means of Internet or wi-fi, wi-max, bluetooth technologies, which are realized on a chip. Distance correction of software errors is possible due to utilization of SoC memory (which occupies up to 94% of chip area) for software storage. In a case of error detection new faultless code can be saved to this memory. Distance correction of hardware errors is possible due to utilization of Erasable Programmable Logic Device (EPLD), where new faultless bit stream can be saved in a case of fault detection; actually thereby new hardware is created by means of chip reprogramming.

Approximation and interpenetration of technologies result in isomorphic design, testing and verification methods in relation to software and hardware complexes that in essence are natural process of progressive concept assimilation. The most important characteristics of product lifecycle (time-to-market and yield) become commensurable by time and production volume and this fact favours the tendency above. The hardware lifecycle curve, shown in Fig. 1, to within the isomorphism represents time software stages: design, production ramp-up, fabrication improvement and maintenance.

Fig. 1. Lifecycle curve of hardware-software complex

In the context of lifecycle there are two urgent problems relating to a curve lifting ordinate-direction and a curve compression time-direction that means time-to-market reduction. Here yield rise takes place on all stages: design -because of design errors recovery, production ramp up -

correction of code, implemented to SoC memory, volume -because of service pack release, which correct errors by means of distribution by Internet or satellites.

The research aim is to show development directions of effective testable design models and methods for software to raise yield by adaptation of hardware design technologies and reduction of software structures to the existent standards and patterns of testing and verification. The research problems: 1) Development of a software model for testable design and verification; 2) Development of software testing and diagnosis technologies on basis of the register models of operational and control software parts.

II. SoC SOFTWARE TESTING TECHNOLOGIES

The standard IEEE 1500 SECT [1] has to be considered as effective component of SoC Infrastructure Intellectual Property. The main its destination is testing of all F-IP functionalities and galvanic connections between them. Next step in evolution of the standard for the purpose of repairable chip creation is development of I-IP components with SoC diagnosis and repair service functions; last ones in the aggregate with a testing module are market attractive: I = {T, D, R}. The diagnosis and repair procedures are not regulated by the testable design standards because of the complexity and ambiguity of a universal solution of this problem for various types of computers. For irregular or unique structures solutions of all three problems are based on a priori redundancy - diversification of component functionalities, which make up SoC. At that rate only it can to say about on-chip repair of a fail element. Concerning regular structures, which have underlying redundancy, such as multi- and matrix processors, one of solution variants can be a controller structure that combines realization of all functions above by means of the Boundary Scan Standard:

I = {T,F,S,D,R}, T = {T1,T2,...,T1,...,Tn};

F = {F1,F2,...,Fi,...,Fn};

S = {S1,S2,...,Si,...,Sn}; D = f(T,F,S) = FD єF;

R = g(D,F) = (FR cF)&(FR uFD = F).

Here the first three identifiers of a model are tests for functionalities; components, which represent functions; and boundary scan register cells for identification of functionalities’ technical state. Other two ones are represented by functions for SoC diagnosis and repair realization. The first function (D) defines a faulty components set that is computed on basis of the output response vector S and a test, covered all functional faults; it is entered in the form of fault detection table (FDT). Second function (R) formulates the rules of component power reduction by removal of fault elements from addressing and forming of new faultless subset F-IP SoC to use according to its intended purpose.

A question about location of a test and functionality verification analyzer is not problematical. If the matter is unique components they should be connected with service I-IP components no dispersal on a chip area. In a case of the

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regular matrix structure tests for all cells are the same, so it has to be used for all components; also a single test, diagnosis and repair analyzer has to be in a structure.

A question about computer resource relocation after a faulty cell detection is interesting. If there are additional spares for repair, the problem comes to the optimal replacement of faulty memory cells by spare rows and columns. In other case there are other system repair models, which depends on a multiprocessor representation form. The linear or one-dimensional addressing form defines consistency of input variables n of a decoder and addressable components, which are connected among

themselves by relation: |A| = 2n . The matrix representation

of a multiprocessor specifies two-dimensional component addressing that is oriented on pipelining technologically. In both cases decoding of a cell number by its address is carried out. So, for the purpose of a faulty component address change on a faultless one it is necessary to modify a decoder structure. This problem is strictly technical and its solution comes to the masking of faulty component addresses. Other solution is related to availability of spares in a processor structure. In given case the problem can be reduced to the replacement of one or several faulty processors by faultless elements from the spare. The optimal solution of the problem has considered for a case, when there are several faulty cells in a memory matrix. The problem becomes more complex if digital system functionality has parallelized yet on existent processor matrix P = Pij, P = m x n , which has faulty elements, and it

is necessary to reallocate a set of faultless cells |P * < |p| to

obtain the quasioptimal covering of functional subproblems by a subset of faultless processors.

Development of software formal model, to which CAD and EDA technologies can be applied, to use the formal methods of test synthesis, evaluation of fault covering, determination of testability (controllability and observability) for subsequent modernization of software structure is quite urgent. To solve this problem the automaton model cab be used:

M = (MOA,MCA),MOA = {XOYC,Y°,Z°}; MCA = {XC,YO,YC,ZC};

ZO = f°(XOYC);Y° = gO(XOYC); Z C=fC(XC,YO);YC = gC(XC,YO).

-O -O

Where X , Z are vectors or register input and output

variables; Y ,Y , Z are signals of operation control

(initialization), announcing signals, and monitoring signals

of a control automaton respectively; f ,g (f ,g ) are functions, which determine relations between interface signals in an operational and control automata.

But the automaton model above M = (MOA,MCA) is not technological for a developer at solution of practical

problems of testable design. Processor (software)-based modification of one is proposed; it consists of two graphs with directed ribs:

M = (MOR,MCG), MOR = {R,I};

R = {R1,R2,...,Ri,...,Rn},I = {I1,I2,...,Ij,...,Im};

Ri = f(Rk,Ij);MCG = {S,E};

S = {S1,S2,...,Si,...,Sp},E = {E1,E2,...,Ej,...,Eq};

Si = f(SkEj).

Here M is Sharshunov register transfer graph [5] with a set of points R, which describes all memory components (registers, flip-flops, counters, memory, input and output buses) used in a program, and a set of ribs, which are marked by instructions I and activate information transfer between points. Expression R; = f(Rk,Ij) defines

functional dependence between adjacent points Ri ^ Rk

which are connected by means of operation Ij є I.

Component M is conceptual graph of a control automaton that is defined on a point set S, which are connected by directed ribs E, marked by transition conditions. Expression Si = f(Sk,Ej) defines functional

dependence between adjacent points Si ^ Sk of a control graph, which are connected to realize jump Ej є E.

Instances of register transfer and control graphs are shown in Fig. 2 and 3 respectively.

Fig. 2. Register transfer graph

Advantages of graph models are not only in structure representation of functionals interaction, but applicability of testability analysis methods, because directed graph models have explicit information flow directions, input and output points. On the basis of the testability evaluation experience for digital systems the following metrics of controllability

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and observability analysis for the graph structures above can be proposed:

G = {R,I};R = {RbR2,...,RnhI = {ІьЬ-ЛшК

(RpRq);

1 k 1

7X Z

k i=1 m

1k 1

-X Z

k i=1 m

1; O(Ry) =

U Iij є (RpRq) j

UIij є (RpRq)

il

X

X

X C(Rp) ;

X O(Rq) ;

Here a software (hardware) module model is represented by the graph G = {R, I} that consists of points (registers) and ribs (instructions). Every graph rib is marked not less one operation Iij є Ii « (RpRq) that forms a command

subset, attached to the rib (RpRq). The controllability criterion for the point C(Rq ) depends on the controllability

of previous point C(Rp) and reduced additive power of a command set 1

і k k XZ

k i=i

UI4 є (RpRq)

1 k Г1 ,1 1k ' d "

— xZ — X d — xZ

J k i=1 m k i=1 m

X

m

which activate k ribs, attached to the given point C(Rq).

Here every rib contains d operations (m - the total command quantity), which initiate information transfer to (RpRq). On the analogy the observability evaluation

criterion C(Rp) based on analysis of points-successors and

ribs, outgoing from C(Rp), is formed. The advantage of

the proposed models and criteria of controllability and observability evaluation is their universality, based on realization of direct and inverse implication on a graph, as well as their invariance concerning the testable analysis and test synthesis for software and hardware components. Controllability C(Rx) = 1 of input and observability O(Ry) = 1 of output graph points is initiated by “1” values.

As advancement of point analysis to internal lines the values of evaluations above can decrease only.

Thus, the graph points are represented by the following components: input variables, output variables, register variables, ALU block, memory arrays, which are represented in a format of their presentation in a software (hardware) module. Ribs determine an operand (command) set, which transfer (transformation) of information between points. The complete model of a device, represented by the register transfer and control graphs, covers all statements of data transfer and control in a software (hardware) module that is necessary to the synthesis of testable device. At that test synthesis is based on solving of the covering problem of all paths and points in register transfer and control graphs by testbench statements.

The integral evaluation of the point testability in a graph is calculated by formula: T(Ri) = C(Ri) x O(Ri).

The total graph testability for software (hardware) is

1 n

computed by expression Ttotal =— Z T(Ri).

ni=1

For instance, represented by a register transfer graph (Fig. 2), computation of testability is given below. The controllability factors are:

C(X) = 1; d 2 2

C(R1) = C(X) x1x — = 1x1x- = - = 0,25;

m 8 8

d 2 2

C(R2) = C(X) x1x — = 1x1x- = —= 0,25;

m 8 8

d 2 2

C(R3) = C(X) x 1x — = 1x 1x- = - = 0,25;

m 8 8

C(R4) = C(R5) =

C(Y) =

C(R1) x d m

C(R2) x -m

C(R2) x-

m

C(R3) x-

m

x1 = — = 0,0625; 2 16

x1 = — = 0,0625; 2 16

C(R4) x-

C(R5) x-

x1 = — = 0,015625; 2 64

The point Y has minimal controllability. Observability computation:

+

d

d

+

d

d

+

m

m

22

O(Y) = 1; O(R4) = O(Y) x- = 1x- = 0,25;

8 8

22

O(R5) = O(Y) x- = 1x- = 0,25; 88

2 12

O(R3) = O(R5) x - = - x - = 0,0625;

3 8 4 8

2 12

O(R1) = O(R4) x - = - x - = 0,0625;

1 4 8 4 8

O(R2) = O(X):

O(R4)xf I + 1 O(R5)x8

/2 = — = 0,0625; 16

O(R1) x 8 j + ^O(R2) x 2 j + ( O(R3) x 2

/3 =

= — = 0,015625.

64

The point X has minimal observability. Testability computation:

T(X) = 1 x 0,015625 = 0,015625 ;

T(R1) = 0,25 x 0,0625 = 0,015625;

T(R2) = 0,25 x 0,0625 = 0,015625;

T(R3) = 0,25 x 0,0625 = 0,015625;

T(R4) = 0,0625 x 0,25 = 0,015625;

T(R5) = 0,0625 x 0,25 = 0,015625;

T(Y) = 0,015625 x 1 = 0,015625 .

The total circuit testability T^^l = 0,015625.

Calculation of the testability characteristics for the control automaton graph (Fig. 3) is realized similarly. Determination of the graph controllability:

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C(Si) =

C(So)X -m

C(So) = 1;

C(S3) X -m

x - =— = 0,34375; 2 32

C(S3) = C(S0) X 1x — = 1x 1X - = - = 0,75;

m 4 4

C(S5) = C(S3) x1 X — = - x 1 x - = — = 0,375;

m 4 4 16

C(S4)

=_47_

= 384"

C(S1) X- + о g X |o. + C(S5) x-

m m m

1 =

X 3 =

0,1224;

C(S2)=

C(S1) x-

C(S4)x-

1 =

X 2 =

d

d

+

m

179

1536

0,11654.

The point S2 has minimal controllability. Observability computation:

2 2

O(S2) = 1; O(S4) = O(S2) x 1x- = 1x1x- = 0,5;

O(S5) = O(S4) x 1 x1 = 1 x 1 x1 = 1 = 0,125;

5 4 4 2 4 8

O(S3)

O(S1) X -4 j + ( O(S4) X -4 j + ^ O(S5) X 2

/3 =

7

= — = 0,07292; 96

O(S1)

O(S2) x -2 j + f O(S4) x -4

/2 = - = 0,125; 8

O(S0)

O(S1) X 2j + f O(S3) X 3

/2 = — = 0,05859375 256

The point S0 has minimal observability. Testability computation:

T(S0) = 1 x 0,05859375 = 0,05859375;

T(S0 = 0,34375 x 0,125 = 0,04296875;

T(S2) = 0,11654 x 1 = 0,11654;

T(S3) = 0,75 x 0,07292 = 0,05469;

T(S4) = 0,1224 x 0,5 = 0,0612;

T(S5) = 0,375 x 0,125 = 0,046875.

The point S1 has the worst testability. The total circuit testability is Ttotal = 0,063478.

Thus, the proposed testability evaluation method has the followings advantages: 1) high effectiveness and

universality relative to its use for evaluation of register transfer and control graph testability; 2) possibility to detect bottlenecks in software or hardware to modify a project structure; 3) choice of the best project by comparison of alternative variants testability.

III. Software diagnosis technology

At development of large size software verification of development project on the correctness of statements is urgent problem. Complex software includes great many branches and verification of software on every logical path

is rather complex problem. A method of faulty statements (errors or faults) searching for software that is based on representation of software algorithm in the form of graph structure for subsequent test generation and fault diagnosis is considered below on an example. Lets it is necessary to verify the software that realizes computation of the following sum of functions:

S = (x) + ro(x),

x =

x + 3; x < 2; 2x -3; 2 < x < 12; - 3x + 7; x > 12;

fsm(x + ж 3),x < 2n 3; ffl(x) = < .

[ sin(nin + 2 , x > 2п/3.

One of the possible problem solution variants on C++ language is represented by the following listing:

Listing 3.1.

#include <iostream>

#include <math.h> using namespace std; int main()

{

const double Pi=3.14159; double F, w, f, x; cin>>x; if (x<2) f=x+3;

else if ((x>=2) && (x<12)) f=2*x-3;

else f=-3*x+7;

if (x<2./3.*Pi)

w=sin(x+Pi/3);

else w=sin(Pi*x)+2;

F=f+w;

cout<<F<<endl; return 0;

}

Lets an error takes place in a statement of computational part of software. Instead of the correct statement else w=sin(Pi*x)+2; the following one is written: else w=sin(Pi*x) I 2;

It is necessary to detect faulty statement in program code by using the testing technology, based on the graph code model. Software diagnosis stages include 4 procedures below.

1. Making of register transfer graph.

Graph ribs are a set of code fragments or separate operations (Fig. 4); graph points are points of information monitoring (registers, variables, memory), which are used for forming of assertions too.

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A number of test points in the graph (registers, variables, memory) should be adequate to diagnose of given resolution. Otherwise it is necessary to carry out the analysis of register transfer graph testability for software and to determine the minimal additional quantity of observation lines for forming of assertions, which enable to detect faulty modules with given diagnosis resolution. Every rib (see Fig. 4) is marked by an arithmetic operation set: {1} - summation; {2} - multiplication; {3} -subtraction; {4} - division; {5} - obtainment of trigonometric sine. In a case when there is a branch in a program a number of outgoing ribs from a point is equal to quantity of adjacent sinks that is formed by branch statements in respective part of a program.

Thus, for the code fragment of the instance: if (x<2) f=x+3;

else if ((x>=2) && (x<12)) f=2*x-3; else f=-3*x+7;

there are three ribs, outgoing from the point X. Computational results Ii,I2,I3, which depend on the variable X, are checked in the points Ri,R2,R3 respectively. In a case of execution of the operation Ii the following branch is realized: if (x<2./3.*Pi) w=sin(x+Pi/3); else w=sin(Pi*x)+2;

Then the general summation operation for all transactions is carried out regardless of which branch statements had been executed.

F=f+w;

The summation operation is executed on various ribs (the objects I6A5I6B5I6C5I6D), but all of them correspond to the same part of the program code. So, faultless execution an operation on a rib eliminates a fault on other three ones. On next stages of software diagnosis these objects are merged to I6 . The result are checked in the final point Y.

The method of software algorithm representation by graph structure enables to show all possible variants of software execution, as well as to simplify realization of next diagnosis stage of software and forming of minimal test.

2. Test synthesis and analysis. A set of ribs are written in the form of disjunctive normal form (DNF), where every term is one-dimensional path from input port to output, which covers a subset of internal lines: P = X14Y v X15Y v X2Y v X3Y . In the aggregate onedimensional paths, represented in DNF, cover all possible transactions - graph points and ribs. An aggregate of code fragments or statements (activation instructions), written by disjunction, is brought to conformity with every rib. For instance, the path X14Y activates execution of operations on ribs I1,I4,I6A. At that the ribs I1 and I6A have only one statement, and consecutive execution of three statements corresponds to the identifier I4 . The test Pj = [(1)(1 v 4 v 5)(1)] that activates the path X14Y ensures

the correctness check of all statements. Thus, the test of minimal covering of all graph points and ribs by commands,

which activate graph ribs and therefore data movement to observation points, can be written:

P = [(1)(1 v 4 v 5)(1)] v [(1)(1 v 2 v 5)(1)] v

v [(2 v 3X1)] v [(1 v 2X1)].

Subsequent DNF transformation consists of removal of brackets to obtain complete test that enables to check transactions in a graph, which cover all points and ribs in various combinations:

P = (111 v 141 v 151) v (111 v 121 v 151) v v (21 v 31) v (11 v 12) .

The obtained test is redundant; it is not always acceptable for large size software, because of there is large quantity of test patterns. So, the ability to create minimal length test of given resolution is very important. Such test is formed by solving of the covering problem of all graph points and ribs and activation of code fragments sets. When testing it is supposed that hardware components, used in the software are faultless.

3. Fault detection table making. Fault detection table is oriented on verification of code fragments sets on ribs, which form data activation paths to the observation points (graph points). In compliance with comparison of experimental data of tested software and expected responses the output response vector V is formed. In a case of result failure on an observed line the respective coordinate of the vector V takes on a value “1” for the test pattern under consideration. The fault detection table of code fragments on complete test P = X14Y v X15Y v X2Y v X3Y , where test patterns are written in general form (a set of onedimensional paths), is shown below:

T/ л I11 I22 I23 I31 I32 I41 I44 I45 I51 I52 I55 I61 V

X14Y 1 1 1 1 1 0

X15Y 1 1 1 1 1 1

X2Y 1 1 1 0

X3Y 1 1 1 0

Faults 1 1 1

The symbolic notation Ijk means execution of a statement that is on the rib Ij and has index k. For instance, I22 means execution of statement sequence of the rib I2 at

activation of the path X2Y and production operation that corresponds to the fragment of source program code: else if ((x>=2) && (x<12)) f=2*x-3;

The diagnosis resolution for the test at the value of vector V = (0100) is determined by three possible faults: F = I51I52I55. Value “1” of the vector V for a test-vector under consideration means that when issuing second pattern the activation of respective commands execution is took place. The minimal set of DNF terms, which make out all single faults of program fragments of a register transfer graph, is minimal diagnosis test. Next term set (here it coincide with complete test) makes out faults of all instructions, determined in DNF:

P = (111v141v151) v (111v121v151) v (21v 31) v (11v12). Reduction impossibility is conditional on that removal any term does not provide activation of one or several

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fragments. Then complete and extended fault detection table is made that is formed by a term set above. Every obtained test pattern is divided on parts - terms. First test pattern (111 v 141 v 151) consists of three terms: (111), (141) and (151). Every of them has own position in a column. All possible executable operations, which are designated Iik, where j - rib identifier in a graph, k -statement that transforms data on j-th rib, is distinguished across. The graph path to which a term under consideration is applied is considered. For instance, term (141) is applied to first test pattern that activates the path X14Y. The extended fault detection table is:

Ti\Ii I11 I22 І23 І31 I32 I41 I44 I45 І51 І52 155 І61 V

111, 1 1 1 0

141 1 1 1 0

1511 1 1 1 0

1112 1 1 1 1

121 1 1 1 1

1512 1 1 1 1

211 1 1 0

31 1 1 0

11 1 1 0

212 1 1 0

Every term number means execution of a statement on respective graph rib. First nimber “1” provides activation of the statement {1} Ij, so opposite respective column “1” is put. Column values of the extended fault detection table are moved from the FDT of code fragments that is defined on complete generalized test. But coordinate value is written for every test term. Extended fault detection table enable to show the results of every test pattern execution and to simplify the fault detection procedure with given resolution.

4. Diagnosis. In compliance with numbers of “1’ in the output response vector V quantity of disjunctive CNF terms is formed. Every term is line-by-line writing of faults by logical operation “OR”, which influence on distortion of output functional signals. Then transformation CNF to DNF by the Boolean algebra is carried out:

F = (I11 v I51 v I61)(I11 v I52 v I61)(I11 v I55 V I6t) =

I11 v I11I55 v I11I61 v I11I52 v I11I52155 v I11I52161 v I61I11 v v I11I61I51 v I11I61 v I51I11 v I11I51I55 v I11I51I61 v v I11I51I52 vv I51I52155 v I51I52161 v I51I61111 v v I55I61 v I51I61 v I11I61 v I11I55I61 v I11I61 v v I11I52161 v I52155161 v I52I61 v I61I11 v I61I51 v I61.

To reduce the obtained set of possible faults the Boolean algebra laws are used:

A л A = A; A v B = B v A; (A v B)C = AC v BC;

(A v B) v C = A v (B v C); A v A = A;

(A л B) v A = A; (A v B) л A = A, it enables to obtain the expression:

F = I11v I11I55 v I11I61v I11I52 v I11I52I55 v vI11I52I61vI61I11vI11I61I51vI11I61v vI51I11vI11I51I55vI11I51I61vI11I51I52v vI51I52I55vI51I52I61vI51I61I11vI55I61v vI51I61vI11I61vI11I55I61vI11I61vI11I52I61v v I52I55161v I52I61v I61I11v I61I51v I61 =

= I11v I51I52I55 v I61-

Then such elements I jk from F, which are executed in other test patterns with value Vi = 1, are removed. A set of objects, contained the operations, which transform data at program execution uniquely and correctly, is formed:

H = {X14Y,X2Y,X3Y} = {(141) v (151) v (211) v (31) v

v (11) v (212)} = I11v I22 v I23 v I31v I32 v I44 v I45 v I61-

After the reduction a single DNF term is obtained:

F' = F \ H = (I11v I51I52I55 v I61) \ (I11v I22 v I23 v I31v I32 v I44 v I45 v I61) = I51I52155.

It means that the software functions with error at execution one of the statements {1,2,5} on the rib I5 .

Really, an error takes place on linear program part that is applied to a rib of the statement sequence I5 , namely I51 -execution of subtraction instead of summation.

More exact diagnosis (to within statement) is possible if to use the greater quantity of test points that complicates diagnosis because of necessity to make longer tests. The proposed method enables to analyze software on presence of errors in the code and helps to detect their location. Testing and verification of software is the main problem at programming, and its solving enables to raise software quality and to obviate unforeseen results of its execution. The proposed method is based on representation of software algorithm by the graph structure, where ribs are statement sequences or code fragments, and points are information monitoring points for making of assertions. Creation of minimal quantity of test patterns enables to decrease time of fault detection. At that tests have to cover all possible transactions. Test points quantity has to be minimal and sufficient for diagnosis of given resolution.

IV. Conclusion

The innovative technologies of software and hardware testable design, based on effective test development and verification of digital system-on-a-chip components, are considered.

1. The general directions of utilization of the testable design technologies for digital systems-on-chips in the problems of software testing and verification are shown.

2. The universal model of software and hardware component in the form of directed register transfer and control graph, on which the testable design, test synthesis and analysis problems can be solved, is represented.

3. The metrics of hardware and software testability evaluation (controllability and observability), models of which are represented by directed register transfer and control graphs, is proposed.

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4. The technology of software testing and diagnosis on basis of synthesis the graph register transfer models is proposed.

5. The practical importance of proposed methods and models is high interest of the software companies in innovative solutions of the effective software testing and verification problems above.

References

[1] Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur, “Overview of the IEEE P1500 Standard”, ITC International Test Conference, 2003, pp. 988-997.

[2] Abramovici M., Breuer M.A. and Friedman A.D, “Digital System Testing and Testable Design”, Computer Science Press, 1998, 652 p.

[3] V.I.Hahanov, S.V.Chumachrnko, W.Gharibi, E.Litvinova, “Algebra-logical method for SoC embedded memory repair”, Proceedings of the 15 International Conference «Mixed design of integrated circuits and systems», Poland, 2008, pp. 481-486.

[4] Thatte S.M., Abraham J.A, “Test generation for microprocessors”,

IEEE Trans. Comput., 1980, C-29, No 6, pp. 429-441.

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Vladimir Hahanov - Dean of the Computer Engineering Faculty, Doctor of Science, Professor. IEEE Computer Society Golden Core Member.

1985 - Ph.D, “Digital systems models and testing methods for computer-aided design”, Kharkov National University of Radio Electronics.

1996 - Dr. of Science, “Models and methods of digital microprocessors system for fault simulation and testing service”, Kharkov National University of Radio Electronics.

2003 - till now dean of the Computer Engineering Faculty, Kharkov National University of Radio Electronics.

1997 - till now - professor of Kharkov National University of Radio Electronics. Kharkov Military University, Kharkov Academy of railway transport, Kharkov Academy of Culture, Kharkov Aerospace University. 1988 - 1997 - senior lecturer.

V. Hahanov has 510 publications, 7 books, and 2 patents.

Scientific work:

- Creation of the computer-aided system for logic simulation, test generation, faults diagnosis of digital devices;

- Systems and microprocessor-based structures;

- Two-framed cubic Algebra, cubic form of the graph representation, Cubic models of digital devices, deductive-parallel method of cubic fault simulation, topological deductive back traced parallel fault simulation method, cubic method of test generation;

- Algebra Logic fault localization and memory repair methods of SoC Functionality;

- Software tools (C++, Assembler, Fortran) for research.

High performance fault simulation and test generation development for complete digital systems and networks described hierarchical models. The development is based on Multi-Core architectures;

Design automation for testability with IEEE Boundary Scan standards and debugging tools for specialized microprocessor systems and digital systems processing;

Certification and verification of the hardware and software components of the computer systems and networks;

Design automation for educational applications in the field of computer engineering;

Digital Signal Processing and MPEG stsndards.

Honors:

1996 - “Best methodologist of University”, Ukraine.

2000, 2001 - honors from “Best scientist of Kharkov region”, Ukraine.

2003 - INTEL award of scientific projects competition.

2005 - The best professor of Ukraine.

2005 - Award from President of Ukraine.

2005 - IEEE Diploma for the IEEE conference organization.

2005 - IEEE Computer Society Golden Core Member.

2007 - IEEE Outstanding contribution Award.

Member of three specialized scientific boards for defense of thesis for a Doctor's degree: D 64.052.02 - systems of design automation, D 64.807.02

- information technologies in control systems.

Leader of the scientific seminar “Design automation and diagnosis of computational devices, systems and networks”.

Chairman of the international symposium “IEEE East-West. Design and Test”.

Member of 10 organization committee for the International Conferences

Member of IEEE Computer Society from 2000.

Member of High Examination Board of Ministry of Education of Ukraine.

Scientific supervisor of “Design & Test” R&D Lab.

Chief Scientist of Aldec Inc., cooperation with Cadence, Microsoft, Intel.

E-mail: hahanov@kture.kharkov.ua

Eugenia Litvinova - Assistent Professor, Doctor of philosophy. IEEE Society member.

1985 - Kharkov National University of Radioelectronics, speciality “Radioelectronic Designing and Production”.

1996, Academic degree - candidate of technical science.

2001, Academic status - associate professor.

Senior Lector in Kharkov National University of Radio Electronics, Ukraine.

Over a period of time from 2000 year more 30 scientific publications were made.

Computer Engineering Faculty, Kharkov National University of Radioelectronics, Ukraine, Lenin Ave. 14, Kharkov, Ukraine, 61166, phone: (057) 70-21-421, (057) 70-21-326. E-mail: kiu@kture.kharkov.ua

W. Gharibi - PhD Student of the Kharkov National University of Radio Electronics, Computer Engineering Faculty.

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