Test data generation for LRU cache-memory testing Текст научной статьи по специальности «Химические науки»

Test data generation for LRU cache-memory testing

Evgeni Kornikhin Moscow State University, Russia Email: kornevgen@gmail.com

Abstract—System functional testing of microprocessors deals with many assembly programs of given behavior. The paper proposes new constraint-based algorithm of initial cache-memory contents generation for given behavior of assembly program (with cache misses and hits). Although algorithm works for any types of cache-memory, the paper describes algorithm in detail for basis types of cache-memory only: fully associative cache and direct mapped cache.

I. Introduction

System functional testing of microprocessors uses many assembly programs (test programs). Such programs are loaded to the memory, executed, execution process is logged and analyzed. But modern processors testing requires a lot of test programs. Technical way of test program generation was proposed in [1]. This way based on the microprocessor’s model. Its first stage is systematic generation abstract test programs (test templates). This abstract form doesn’t contain initial state of microprocessor but contain sequence of instructions with arguments (registers) and with test situations (behavior of this instruction; these can be overflow, cache hits, cache misses). The second stage is generation of initial microprocessor state for given test template. This stage is test data generation. Technical way from [1] is useful for aimed testing when aim is expressed by instruction sequence with specific behavior. Initial microprocessor state includes initial values of registers and initial contents of cache-memory. Based on this state the third, final, stage is generation the sequence of instructions to reach initial microprocessor state. These sequence of instructions with test template get ready assembly program. This paper devoted to the second stage, i.e. initial state generation.

Known researches about test data generation problem contain the following methods of its solving:

1) combinatorial methods;

2) ATPG-based methods;

3) constraint-based methods.

combinatorial methods are useful for simple test templates (each variable has explicit directive of its domain, each value in domain is possess) [2]. ATPG-based methods are useful for structural but not functional testing [3]. Constraint-based methods are the most promising methods. Test template is translated to the set of constraints (predicates) with variables which represented test data. Then special solver generates values for variables to satisfy all constraints. This paper contains constraint-based method also. IBM uses constraint-based method in Genesys-Pro [4]. But it works inefficiently on test templates from [1]. Authors of another constraint-based

methods restrict on registers only and don’t consider cache-memory.

II. Test templates description

Test template defines properties of future test program. Test template contains sequence of instructions. Each element of this sequence has instruction name, arguments (registers, addresses, values) and test situation (relation between values of arguments and microprocessor state before execution of instruction). Example of test template description for model instruction set:

REGISTER regl : 32;

REGISTER reg2 : 32;

ADD regl, reg2, reg2

LOAD regl, reg2 @ llMiss, l2Hit

SUB reg2, regl, reg2

This template has 3 instructions - ADD, LOAD and SUB. Template begins from variable definitions (it has name of variable and its bit length). Test situation is specified after ”@”: test situation of the second instruction is ”llMiss, l2Hit”: ”llMiss” means cache miss in first-level cache and ”l2Hit” means cache hit in second-level cache.

Model instruction set contains only 2 memory operation:

• ”LOAD reg, address” loads value from memory by physical address ’’address” to the register ”reg”;

• ”STORE reg, address” stores value from register ”reg” to the memory by physical address ’’address”.

Test data generation is generation of initial values of registers and initial contents of cache-memory. This problem has been solved for common microprocessor cache-memory. The following consists of test data generation for 2 basis cache-memory organizations: fully associative cache with LRU and direct mapped cache. common cache includes aspects from both cache-memory organizations. The rest of paper deals with one-level cache-memory although proposed method can be applied to cache memory with more than one level.

III. Test data generation for fully associative

CACHE

Fully N-associative cache consists of N cells (N means cache associativity). Each cache cell may store data from any memory cell. All cache cells correspond to the different memory cells. Access to memory starts from access to cache. search data in cache performs for each cache cells in parallel. Cache hit means existence data in cache. Cache miss means absence of data in cache. In case of cache miss one cache

■\

x y I z

N

y

1. Fully N-associative cache

cell must be replaced on data from required address by specific replacement strategy. This paper uses LRU replacement strategy (Least Recently Used). According to LRU the least recently used cache cell will be evicted. At the following phrase "evicted address x” means evicted data by address x.

Proposed algorithm based on the following properties of evicted addresses:

1) any evicted address was inserted by instruction from test template with cache miss or was in the initial contents of cache;

2) between replacing and the last access to the same address (cache hit or cache miss) there are accesses to the whole cache without address itself.

Proposed algorithm generates constraints on the following variables:

1) ai,a2, ...,aN - initial contents of cache (its count equals to cache associativity);

2) hits-addresses (addresses of instructions from test templates with cache hit test situation);

3) misses-addresses (addresses of instructions from test templates with cache miss test situation);

4) evicted addresses (evicted addresses of instructions from test templates with cache miss test situation);

5) L0,L1,... - cache states

Each instruction from test template with cache hit gives 1 new variable, and each instruction with cache miss gives 3 new variable (1 for miss address, 1 for evicted address, and 1 for cache state). Proposed algorithm generates constraints for each instruction from test template by the following (N means cache associativity):

1) "initial constraints” are generated one time for any test template: L0 = {a1,a2,...,aN}, \L0\ = N (other words, numbers a1,a2,..., aN are different);

2) ”hit-constraints” are generated for each instruction from test template with cache hit: x e L, when x means address from instruction, L means a current cache state-variable;

3) ”miss-constraints” are generated for each instruction from test template with cache miss (x means evicting address, y means evicted address, L means a current cache state-variable): y e L,x/L,L' = Lu{x}\{y}, lru(y), L' became a current cache state-variable for the next instruction.

y

z

x

Fig.

Constraint lru(y) defines y as the least recently used address.

the last use

pother -4-addresses

v

LRU

Constraint lru(y) is disjunction of constraints corresponded to cases of the last access to the y before its eviction. Each its clause is conjunction of the following constraints (x means the address-variable from the last access to the y):

1) x = y

2) L \ {y} = {x1,x2,..., x„|, where xi, x2,xn are all addresses accessed between accesses to x and y (hits and misses).

The last access to the y can correspond to the previous instruction of test template or to the cell from initial cache state.

Consider an example of test template and its test data generation for 3-associative cache.

LOAD x, y @ Hit STORE u, z @ Miss LOAD z, y @ Hit

Define unique names for variables in test template (each new variable shouldn’t change its value). LOAD gives new version for its first argument. STORE doesn’t generate new version of variables. Define new variable for evicted address from the second instruction (this variable won’t be included to the solution):

LOAD xi, yo @ Hit STORE u0,z0 @ Miss ^ z0 LOAD zi, yo @ Hit

Define variables for initial contents of cache: {a, 3,7} (its count equals to cache associativity).

So the task is looking for values of x0,y0, z0,u0, a, 3,7 according to test template. This task has more than 1 solutions. But any solution is enough.

The first constraints describe cache hits and misses as belong to the current state of cache: y0 {a, 3, 7},

Z0 £ {a, 3,7}, z0 e {a,3,71, y0 e {a,3,7} \ {z0} U {z0} a, 3,7 - different

Define constraint lru(z'0). Candidates of the last access to the this address are y0,7,3,a. The first and the second candidates aren’t suitable because constraint L \ {z0} = X is false because of different compared sets capacity. Remainder candidates give the following disjunction:

hit xi hit x2

miss x3—>y3

Fig. 2.

z0 = 3 A {an I3, 7} \ {z0} = ^, y0}

V

z'0 = a A {an 3, 7} \ {z0} = {3, 7, y0}

Simplify it:

zo = 3 A {a,7} = {7,y0}

V

z00 = a A {3, 7} = {3, 7, y0}

Further simplify:

z00 = 3 A y0 = a

V

z00 = a A y0 {3, 7}

Consider the first clause with the rest of constraints (variable z'0 isn’t needed in solution):

y0 = a

z0 £ {a, 3,7}, a, 3, 7 - different

Note that x0 and u0 don’t take part in constraints. So their values may be arbitrary.

Lets bit length of addresses is 8. So domain of all variable-addresses is from 0 to 255. Satisfying constraints variables can get the following values (these values are not unique): a = y0 = x0 = u0 = 0

3 = 1

7 = 2 z0 = 3

Verify test template execution with computed initial cache state and register values: initial cache state is [2, 1, 0]

LOAD x, 0 - Hit, because 0 e {2,1,0}; according to LRU the next cache state is [0, 2, 1]

STORE 0, 3 - Miss, because 3 £ {0,2,1}; according to LRU 3 goes to cache, 1 is evicted from cache, the next cache state is [3, 0, 2]

LOAD z, 0 - Hit, because 0 {3, 0, 2}

All instructions from test template were executed according to given test situations.

IV. Test data generation for direct mapped cache

y______rR(y) y

z

R(z)

z

x

*_______r R(x)

Fig. 3. Direct mapped cache

Whole memory is divided into non-intersecting areas (regions). Direct mapped cache consists of 1 cell for each region.

Each cache cell may store data only from its region. Access to memory starts from access to cache. Cache hit means successful match cached address with required address in its region. Cache miss means unsuccessful match cached address with required address in its region. In this case data from cache replaced by data from memory by required address.

Proposed algorithm generates constraints on the following variables:

1) a1, a2, a3,... are addresses of the initial cache state (their count is regions’ count);

2) hits-addresses (addresses of instructions from test templates with cache hit test situation);

3) misses-addresses (addresses of instructions from test templates with cache miss test situation);

4) evicted addresses (evicted addresses of instructions from test templates with cache miss test situation);

5) L0,L1,... - cache states

Define function R(y) which for address y returns a set of all cells from the same region as region of y. R satisfies the following properties:

Vx (x e R(x))

Vx Vy (x = y ^ R(x) = R(y))

Vx Vy (R(x) = R(y) ^ x e R(y))

Vx Vy (R(x) = R(y) ^ ye R(x))

Vx Vy (x e R(y) ^ x = y)

Proposed algorithm generates constraints for each instruction by the following way (N means number of regions):

1) ”initial constraints” are generated one time for

each template : \{a1,a2, ...,aN}\ = N (other

words, numbers a1,a2, ...,aN are different),

\{R(a1), R(a2),..., R(aN)}\ = N (other words,

all sets R(a1), R(a2),..., R(aN) are different);

2) ”hits-constraints” are generated for each instruction with cache hit: x L, where x means address from instruction, L means a current variable-state of cache memory;

3) ”miss-constraints” are generated for each instruction with cache miss (x means evicting address, y means evicted address, L means a current variable-state of cache): y e L,x /L,L' = Lu{x}\{y},R(y) = R(x), L' became the current variable-cache state for the next instruction.

Constraints for direct mapped cache differ from constraints for fully associative cache by evicted address constraints only.

Consider test data generation for the already known test template. Lets memory divided into 3 regions depended on remainder from division address to 3 (i.e. R(x) = R(y) 3\(x - y) ).

LOAD x, y @ Hit

STORE u, z @ Miss

LOAD z, y @ Hit

Define unique names for variables in test template (each new variable shouldn’t change its value). LOAD gives new version for its first argument. STORE doesn’t generate new version of variables. Define new variable z'0 for evicted address from the second instruction (this variable won’t be included to the solution):

LOAD xi, yo @ Hit STORE u0, z0 @ Miss ^ z'0 LOAD zi,yo @ Hit

Define variables of initial cache state: {a, 3,7} (one for each region).

So the task is looking for values of xo,yo, zo,uo,a,3,7 according to test template. This task has more than 1 solutions. But any solution is enough.

The first constraints describe cache hits and misses as belong to the current state of cache: yo £ {a, 3,7}, zo £ {a, 3,7},

z0 £ {a,|3,7},

yo £ {a,3,7} \ {zo} u {zo},

R(zo) = R(z'0), a, 3,7 - different R(a), R(3),R(7) - different Simplify this constraints set:

z0 £ {a,l3,7}, yo £ {a,3,7} \ {zo}, zo £ {a, 3,7},

3|(zo - z'o), a, 3,7 - different

R(a), R(3),R(7) - different

Note that xo and uo don’t take part in constraints. So their values may be arbitrary.

Lets bit length of addresses is 8. So domain of all variable-addresses is from 0 to 255. Satisfying constraints variables can get the following values (these values are not unique): a = xo = uo = 0

3 = yo = 1 7 = 2 zo = 3

Verify test template execution with generated initial cache state and register values: initial cache state is L = [(R = 0) ^ 0, (R =1) ^ 1, (R = 2) ^ 2]

LOAD x, 1 - Hit, because R(1) = L[R = (1 mod 3)] STORE 0, 3 - Miss, because R(3) = L[R = (3 mod 3)], 1 is evicted from cache, the next state of cache is L = [(R = 0) ^ 0, (R =1) ^ 3, (R = 2) ^ 2]

LOAD z, 0 - Hit, because R(0) = L[R = (0 mod 3)]

All instructions from test template were executed according to given test situations.

V. Test data generation for common cache

This section consists of illustration only the constraints for common cache.

Define function R(x) as the same as for direct mapped cache.

consider known test template for memory consisted of 3 regions (R(x) = R(y) ^ 3|(x - y)) of 2-associative cache: LOAD x, y @ Hit STORE u, z @ Miss LOAD z, y @ Hit

Define unique variables (and zo0 for evicted address):

y rR(y) y y1

z

Ir(z) 1 z | | z1

x fR(x) 1 x | | x1

Fig. 4. Common cache

LOAD xi,yo @ Hit STORE uo,zo @ Miss ^ zo LOAD zi,yo @ Hit

Define variables for initial cache state: a1, a2 for the first region, 3i, 32 for the second region, 71,72 for the third region. constraints set is the following:

yo e {ai,a2, 31,32,71,72},

zo £ {ai,a2, 3i, 32,71,72},

zo £ {ai,a2,3i,32,7i,72} n R(z'0),

yo e {ai,a2, 31,32,71,72} u {zo} \ {zo},

R(zo) = R(z'o),

a1 ,a2, 31,32,71,72 - different,

R(a1) = R(a2),

R(31) = R(32), r(71) = r(72\

R(a1), R(3i), R(7i) - different

From disjunction for lru(z'o) (one clause is enough):

z'o = 72 A ({a1,a2, 31,32,71, 72}\{z'0})nR(z'0) = {yo}n

R(z'o)

V

Simplify:

yo £ {a1, ...,72}, zo £ {a1, ■■■,72}, zo £ {a1,..., 72} n R(z'o), yo £ {a1, ■■■, 72, zo} \ {zo},

R(zo) = R(z'o), zo = 72,

{71} = {yo} n r(72)

a1 ,a2, 31,32,71,72 - different,

R(a1) = R(a2),

R(31) = R(32),

r(71) = r(72\

R(a1), R(31), R(71) - different Further simplify:

z'o = 72, yo = 71 ,

zo £ {71,72 },

R(zo) = R(72),

a1 ,a2, 31,32,71,72 - different,

R(a1) = R(a2),

R(31) = R(32),

r(71) = r(72\

R(a1), R(31), R(71) - different

Lets bit length of addresses is 8. So domain of all variable-addresses is from 0 to 255. Satisfying constraints variables can get the following values (these values are not unique):

a1 = 0, a2 = 3,

31 = 1,32 =4,

71 = 2,72 = 5,

xo = 0,yo = 2,zo = 7,uo = 0 .

Special algorithms can be used for solving constraints set. These algorithms can take into account the following aspects:

• constraints can be solved symbolically;

• all sets of addresses are finite and subset of all initial cache state addresses union with evicting addresses.

VI. Conclusion

The paper devoted to the test data generation problem. Test data contains initial contents of cache-memory. The paper has proposed the constraint-based algorithm. constraints consists of finite sets variables and sets operations. Test data generation for fully associative cache and direct mapped cache has been considered in details. Proposed algorithm is used in projects of testing MIPS-compatible microprocessors. ECLiPSe is used as constraint solver.

References

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[3] F. Ferrandi, D. Sciuto, M. Beardo, F. Bruschi, An approach to functional testing of vliw architectures // Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT00). P. 2933. 2000.

[4] Y. Lichtenstein, M. Rimon, M. Vinov, M. Behm, J. Ludden, Industrial experience with test generation languages for processor verification // Proceedings of the 41st Design Automation Conference (DAC04). 2004.