CC BY
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Statistical Properties of Spread Spectrum Signals Synchronization System
Inna O. Tkalich, Helen V. Kharchenko and Yegor I. Vdovychenko
Abstract—In this paper the method of digital spread spectrum signals (DSSS) processing concluding digital matched filtration, synchronization and decision making about transmitted signals, FPGA-usage orientated from different vendors is presented. Special attention is attended to the research of synchronization algorithms in the non-Gaussian and nonstationary noise influence conditions. The system synchronization probability-timing characteristics are obtained.
Index Terms— Density of distribution, digital recirculator, DSSS, FPGA, synchronization system
I. Introduction
During receiving signals with long base, one of the main problems is providing high quality characteristics for the synchronization system [1]. It is known that decreasing locking in synchronism time is possible using spread spectrum signals and two-step procedure of synchronization [1]. At once, in the first stage clocking synchronization is provided which consists in determination signal elements convolution monitoring meaning moments, which are the signals either with base [2]
Bel_tel'AFel,
where tel - element duration, sec; AFEL - effective element spectrum bandwidth.
In the second stage the spread spectrum signal matched filtration is performed using signal samples which had been taken in the points of time corresponding signal elements meaning moments. Then, the spread spectrum signal beginning (ending) corresponding meaning moments are determined - i.e. frame synchronization is performed.
Manuscript received April 14, 2009. This work was supported by Ukraine Central State Designs Bureau “Proton” (Ministry of Industrial Policy of Ukraine), Kharkov National University of Radio Electronics, A.Y.Usikov IRE NAS of Ukraine.
Inna O. Tkalich - Researcher of Radio-electronic systems department, Kharkov National University of Radio Electronics, Ukraine (phone: 370-050963-0332; e-mail: nika_zimaleto@mail.ru)
Helen V. Kharchenko - Phd-student of A.Y.Usikov IRE NAS of Ukraine (phone: 370-095-331-1420; e-mail: letter2me@ukr.net)
Yegor I. Vdovychenko - Software engineer of Ukraine Central State Designs Bureau “PROTON” (phone: 370-095-827-6431; e-mail:
vdovvch@vahoo.com)
II. DSSS SYNCHRONIZATION
In the actual communication systems the synchronization subsystem is functioning in the conditions of a prior uncertainty, relatively to the receiving signal parameters, nonGaussian and nonstationary noise influences, and that’s essentially limits the possibility of providing. In the connection with this, it is necessary to use synchronization algorithms efficiency of those would not be dependent on receiving signal intensity and also faintly dependent on kind of noise distribution density parameters for the complex influence, i.e. -on rabastic algorithm.
Clocking synchronization procedure concludes, firstly, in the strong correlation zone determination of spread spectrum signal receiving element and, secondly, in the timing position estimation for the maximum element of convolution, where the maximum signal-to-noise ratio level is detected. For the strong correlation zone determination the following algorithm is offered. The signal clocking interval is divided by L subintervals, each one of them has its own number (address) (see fig. 1): a - conditional beginning of signal interval, b - conditional beginning of the next signal interval.
a r b r
1 2 3 I I I j L ( 1 2 3 j L ,
Fig. 1. The conditional partition of signal interval
It is determined and remembered the address of jth subinterval where the observed process maximum value is situated. If to suppose that the signal convolution element is detected in the jth subinterval, then with probabilities q exactly in this subinterval will be found the observed process maximum value. For the given trustworthiness providing of a sound decision about subinterval address, where the element convolution is presented, the procedure is repeated as long as the address of jth subinterval (or any others subinterval) is repeated m times. Once, the probability of the false synchronization is equal to
Pfs =
(1)
the composite probability of strong correlation interval determination for k intervals is defined by the expression [1]:
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0
k < m;
Pz (k) =
qm + (k - m)Q
m < k < 2m;
k-2m
qm + (k-m)Q-Q £ PE(m-1+j) k > 2m,
(2)
where Q = qm (1-q);
q - is a probability of a sound decision about meaning moment position in the jth interval.
Obviously, the signal energy to power noise spectral density ratio, in the moment of signal element convolution maximum is not high, as far as for the signal receiving in general it is supposed following matched filtration and for the fast and reliable jth subinterval detection is necessary to take steps providing rising element energy ratio to power noise spectral density N0
nEL
At the same time it is necessary to create conditions for the frame synchronization. For this purpose, it is proposed to use the device with structural schema presented in figure 2, where: MF“ 1” - the filter matched with signal element corresponding transmitted logical “1”; MF“0” - the filter matched with signal element corresponding transmitted logical “0”; SLD -square-law detector of envelope.
Fig. 2. Square-law detector of a signal envelope
In the absence of a signal in the output of the matched filter (see fig. 2) [6] instant values of observable process are distributed by the normal law [5] with a variance ct2 = N0 • Eel
W(x) =
1
V2tcc
(3)
In the output of the square-law detector the density of distribution of a signal envelope in the reference moments of time ti is distributed by the exponential law,
W(U = x2) =
1
"2CT2
(4)
and the difference of exponentially distributed random values (see fig. 3) is distributed according to Laplace’s law (double exponential distribution)
M
2ct'
W(y = U2 -U2) =
1 -
1 „_2
4ct2
(5)
X
e
U
e
Fig. 3. Differential channel of synchronization
the cumulative function, in the absence of a signal, equals [4] ¥(t) = - ln (1 + p2 • t2), (6)
where p = 2o2.
Cumulants of the i-order, calculated according to expression (6) may be defined as [4]
Xk =i
X1 = 0;
X 2 = 2P2;
X 2n-1 = 0;
X2n
(2n)!p2n
n
(7)
where n = 1, 2,... .
Cumulants possess two important properties, which allowing executing calculation of cumulants any order for the sum of independent random variables with any weighting factors [9]:
1) The cumulant of a k-order for the multiplication of a random variable y by a constant a is equal to
Xk(ay)=akXk(y) (8)
2) The cumulant of an independent random variables sum is defined by expression
N N
Xk(E Уп) = EXk(yn) (9)
If random variables yi are identically distributed
X k(E Уп) = NXk(y1) (10)
п=1
In consideration of specified above, it is simple to obtaine cumulants of any order in the output of memory device with exponential weight function (recirculation system)
zm =Ё dly1, (11)
and according to expressions (7) - (9) and (11) the cumulants will be equal
X2n =X d^p- = ^ ^Р2П (d
l=0 П П l=0
when d < 1
£ dl = 1 + d + d2 +...
1
1 - d
and
where n = 1, 2,
X2n
1 (2n)! в2п
1 - d n P
(13)
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Under central limit theorem, the distribution of a sum of independent random variables converges to the normal law of distribution. The degree of convergence can be appreciated by coefficient of skewness
k — -
and by kurtosis
Y =
(X2)
X4
(X2)2
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For random variable Z, under (7), (14) and (15) follows
kz = 0;
Yz = 3 (1 - d).
(14)
(15)
(16)
X3
From expression (16) follows, that at 0.97 < d <1 coefficient of kurtosis yZ<0.1, and coefficient of skewness kZ. It allows to use as an approximation of distribution for random variables in the output of recirculation system the law with normal distribution and parameters mZ = 0,
D
Z
2P2 = 8 ,
-----—------C
1 - d 1 - d
In the presence of a signal in one of the receiving channels, it is possible to show [5],[2], that in the output of the signal envelope square-law detector my — E2, and the variance is
equal 4 E2
Dy — 4c4 + — (17)
c2
where C2 — ESN0 2 ' (18)
In the output of the subtracting device (in the input of recirculation system)
mZ — E2
E2 Dz — 4c4(2 + —) C <19)
or under (18) Dz — 4c4 <2 + q2), (20)
where UN:)- (21)
And in the output of recirculation system, respectively,
E2 mz —1-d , (22)
Dz — 1Cd <2+q2), (23)
or Dz — E N° <2 + q2). z 1 - d 4 (24)
Z Setting normalization Zl — —=•, we will receive the den- VP
sity of probability distribution of a random variable in the output of recirculation system as
(Zl-qL)2
W(ZL) —
V2rc
where
qL =
(25)
(26)
|1 -d 4(2 + q2)
The second factor under a radical of expression (26) characterizes losses during non-coherent accumulation subject to signal-to-noise ratio in the input of the square-law detector of envelope.
Dividing a clock interval by L subintervals of integration, and taking into account, that quantity of the independent samples providing sufficient accuracy of a target process representation is approximately equal
N = Bel =Tel • ^ , (27)
we obtain, that the quantity of independent samples of the noise, getting in the interval of integration, is equal
B
Nn —-Ls (28)
During an integration of the input process within limits of an interval, it is easy to show, that
Dz = 4c4(2B- + q2). (29)
Respectively the signal-to-noise ratio in the output of recirculation system may be defined
qL =
1 -d 4 (2Bll + q2)
(30)
The probability of an error during decision-making about actually convolution maximum detection in the subintervals is defined by the formula [3], [5]
1 » _ (Z-qL)2
wJe 2 [Z)]"
P =
dZ,
<31)
where
r - —
F<x) — I e 2 dy - probability integral. (32)
1
2
e
III. FPGA-based synchronization system
Synchronization system realizing worded above method is made in terms of FPGA, using hardware description language VHDL. The VHDL-model is implemented in the crystals of microchips from different vendors such as ALTERA [7], XILINX [8] and others. Fig. 4 presents a schema of the synchronizing system in the registry transfer level implemented in FPGA ALTERA CYCLONE II EP2C70F672C6 using CAD QUARTUS [7].
The system consists of: DD1, DD2 - signal energy storage systems <SESS); DD3 - phase-locked loop system <PLL); DD4 - differential synchronization channel (DSC); DD5 - the block of m-multiple maximum value same address repeatance searching, and synchronization reset when there is no confirmation according to criterion k of n (SYNCH) [13]; DD6 -exact frequency tuning system (EFTS); DD7 - decision support system <DSS).
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SYNCH:DD5
Fig. 4. Synchronization system schema in the RTL level
In the input of synchronizing system during functioning in the consistence of the DSSS processing model device the signals from PDMF channels outputs [6] are followed and in the signal energy stored systems m (m=16) samples located in each subinterval are summarized. On purpose to output the signal for exact frequency tuning the clocking interval is divided by two subintervals in accordance with m/2 (m/2=8) samples correspondingly. Signal predominance in the one of subintervals part selects a direction of frequency tuning.
From the output of differential synchronization channel DD5 the absolute value of accumulated values is followed in the input of digital recirculator based in the module DD5 on CLK_OUT signal falling edge of DD3 module. When projecting using VHDL the digital recirculator may be presented in several ways [11]: as distinct, parameterized data type (array)
- MEMORY is array (0 to 127) of signed (5*N+1 down to 0); either using random access memory library component lpm_ram_dp. In the VHDL-model synthesis result of the synchronization system, in the second case required significantly less logic elements quantity (<1%) comparatively with the first case (=40%) when the digit capacitances are the equivalents.
The recirculator writing address is formed inside of block DD5. The address corresponded to maximum value detection in the clocking interval is remembered and when m-multiple maximum repentance is detected the signal “Synchronization detected” is formed in the output of this block. This signal enables exact frequency tuning system and allows passing clocking impulses in the decision support system DD7.
If the m-multiple address repentance is detected (signal “Synchronization detected” is formed), address monitoring is not stopping. This is necessary for the false synchronization or system failure excluding aroused during functioning. If the signal in the input of the receiver is absent the m-multiple address repentance corresponds to arising of false synchronization which should be canceled. This state detected if among n selections the monitoring address has been repeated less then k times. The probability of false synchronization arising is defined by the formula
= 1 -(1 - Pj)L = 1 -|1 -± QP1 (1 - P)
(33)
where P = L - probability of jth address detection, Pj - probability when jth subinterval address will be repeating k times or more. At once synchronization system transferring in the initial state is performed. The probability of false synchronization occurrence is presented in the table 1.
table 1
The probability of false synchronization occurrence when useful SIGNAL IS ABSENT AND THE VALUES n=32 AND L=128
k=2 k=4 k=8 FT II Os
Pfs 9.65-10-1 1.4310-2 1.58-10-8 0
During useful signal presence in the input of the receiver and the k-multiple address repentance absence among n observations the false synchronization reset will be performed of the correctly detected subinterval. The probability of such an event is defined by expression
Pfr = 1-Ё C‘nP (1 - P)n
(34)
where P is defined by formula (31).
table 2
The Probability of False Synchronization Reset in the Absence of
Useful Signal and the Values n=32 and L =128
h2 Pfr k=2 k=4 k=8
2 0.4 6.86-10-7 6.110-5 1.4810-2
2.5 0.6 1.99-10-12 8.52-10-10 4.54-10-6
3 0.7 0 0 1.0910-11
3.5 0.8 0 0 0
TABLE 3
he Probability of False Synchronization Reset in the Absence
Useful Signal and the Values n=16 and L =128
h2 Pfr k=2 k=4 k=8
2 0.41 2.12-10-3 4.8-10-2 6.6-10-1
3 0.78 1.07-10-9 5.36-10-7 2.35-10-3
3.5 0.89 1.8410-14 5.09-10-11 6.74-10-6
4 0.95 0 0 3.1910-9
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The exact frequency tuning system is meant for the correlation function maximum position regulation in the accumulated samples subinterval middle. For this purpose period addition and subtraction from clocking frequency is performed correspondingly with indication of the frequency tuning direction. Exact frequency tuning system is included in the module DD6 in one clocking frequency fout (fout=20 MHz) is formed by dividing the input frequency fin (fin=80 MHz) by 4. Relative frequency of exact frequency tuning is set according to signal-to-noise ratio level and also according to degree of basic generators instability in the transmitting and receiving side pieces and is controlled using reversible counter.
When reversible counter is zerozied period subtraction is performed as it is shown in the figure 5. When the counter overflowed the period addition is performed as in the figure 6 is shown.
Signal name ■ ■ '9824.72. ■ .982475. ■ 9924.8. ■ 982494. ■ .9924.9
o-TI
d-CLK_80 J~
-d CLK_20 |
Fig. 5. Period subtraction
Signal name ■ 9921.16- ■ 992У.2 - ■4Э27.2+' ■ 9927.26- ■ 5927.Э
D-Tl г
' ^a.K_so _r
■n CLK_20 l l 1 L г l_
Fig. 6. Period addition
Fig. 4 presents phase-locked loop system DD3 meant for frequency synthesizing of a clock signal that is based on a reference clock by the way of dividing input frequency by division factor m. Frequency division by integral factor implementation is quite simple. Fractional division factor can be obtained in several ways [10], simplest is to sequence division factors n and n+1 periodically based on the specified program. Synthesized oscillation spectral purity depends on how rationally the sequence order of the division factors is chosen. Frequency synthesis is presented in [12].
From the output of DD3 signal is clocking module DD5. The decision support system compares samples values which leave accumulations (DD1, DD2) at the falling edge of module DD5 clock pulse moment and gives out the decision about accepted signal.
IV. Conclusion
In this paper the method of spread spectrum signals digital processing which concludes digital matched filtration, synchronization and decision making about transmitted signals, orientated on using FPGA different vendor firms. Digital matched filtration is sufficiently explored and the methods of its realization using FPGA are known [6]. At the same time the large base signals for the systems that act in the non-Gausse and nonstationary noise synchronization methods are insufficiently investigated, and their probability-temporary characteristics practically are not researched. The offered in the paper algorithms of synchronization well implemented to the FPGA crystals. Given above some synchronization system descriptions allow speaking about system parameters optimi-
zation opportunities and expediency of its use in telecommunication systems with the code signals division.
References
[1] V.N. Kharchenko, A.A. Lavrut, T.V. Lavrut The building method of the compound aggregate signals system synchronization // Radioelectronics and computer systems. - 2006. - №5 (17). - С. 193 - 197.(in Russian)
[2] L.Y. Varakin Communication systems with noiselike signals. - М.: Radio and communications, 1985.- 384 ps. (in Russian)
[3] E.D. Viterbi Coherent communications principles. Transl. from English.// Edited by B.R. Levin . - М.: Soviet radio, 1970. - 392 ps. (in Russian)
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[5] V.I. Tihonov Statistical radio engineering. - М.: Radio and communications, 1982. - 624 ps. (in Russian)
[6] H.V. Kharchenko, S.O. Makovetskiy, I.O. Tkalich, O.I. Tsopa, Y.I. Vdovychenko Signal Processing Verification System for the Programmable Digital Matched Filter.// Proceedings of 6-th IEEE East-West Design and Test Symposium. - Kharkov-Lviv: KNURE, 2008.- pp. 243250
[7] D.O. Komolov, R.U. Malk, and U.U. Zobenko, U.S. Fillipov Computer-aided design systems of Altera: MAX+plus II and Quartus II. Brief description and self-teacher. - M.: IP RadioSoft, 2002, 352 pp., (in Russian)
[8] V.V. Semenec, I.V. Hahanova, V.I. Hahanov Digital systems design using VHDL. - Kharkov: KNURE, 2001. -520 pp., (in Russian)
[9] Kramer G. Mathematical methods of Statistics: Transl. from English// Edited by A.N. Kolmogorov. - M.: Mir. 1976. - 495., (in Russian)
[10] V.N. Kharchenko Systems and means of a radio communications. Textbook. - HVVKIURV, 1991. (in Russian).
[11] I.O.Tkalich, H.V. Kharchenko and Y.I.Vdovychenko FPGA-based digital recirculator.//Radio-Electronic and Computer Systems. - Kharkov: KhAI, 2009, submitted for publication.
[12] I.O.Tkalich, H.V. Kharchenko and Y.I.Vdovychenko ASIC-based frequency synthesizer.//Proceedings of 10-th IEEE CADSM Conference. -Polyana-Svalyava, (Zakarpattya), 2009.- pp. 243-250
[13] I.O.Tkalich, H.V. Kharchenko and Y.I.Vdovychenko FPGA-based DSSS synchronization system synthesis.// Applied Radio Electronics. 2009. to be published
Inna O. Tkalich — Researcher of Radio-electronic systems department, Kharkov National University of Radio Electronics, 61166, Kharkov, Lenin Ave,14, Ukraine. Scientific interests: digital systems design. Cell phone:
+380509630332, e-mail: nika_zimaleto@mail.ru
Helen V. Kharchenko — PhD-student of A.Y.Usikov IRE NAS of Ukraine, 61085, Kharkov, Academician Proskury’s street, 12, Ukraine. Scientific interests: code division communication systems, spread spectrum signals digital processing, signals scattering by homogeneities of compound shapes. Cell phone: +380953311420. E-mail: letter2me@ukr.net
Yegor I. Vdovychenko — Software-engineer of Ukraine Central State Designs Bureau “Proton”, 61001, Kharkov, Pl. Vosstaniya, 7/8, Ukraine. Scientific interests: radio technical and television systems, digital systems design. Cell phone: +380958276431. E-mail:
vdovych@yahoo.com
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